CN2935403Y - Wafer-type passive element substrate - Google Patents
Wafer-type passive element substrate Download PDFInfo
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- CN2935403Y CN2935403Y CN 200620004531 CN200620004531U CN2935403Y CN 2935403 Y CN2935403 Y CN 2935403Y CN 200620004531 CN200620004531 CN 200620004531 CN 200620004531 U CN200620004531 U CN 200620004531U CN 2935403 Y CN2935403 Y CN 2935403Y
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- type passive
- substrate
- passive device
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Abstract
The utility model relates to a wafer type passive element base plate, which is a transverse separating line. A plurality of lines is arranged in parallel on the base plate, A plurality of vertical grooves are formed between each two separating lines, an element zone is arranged between the two adjacent grooves and the separating lines, which is used for production of wafer type passive elements; when each element zone is separated during production of the wafer type passive element, the groove can eliminate error after the element zone separation caused by separation processing, and when a electrode plating is carried out for the element zone during the subsequent process, the plating will not affect the conductive effect of the wafer type passive element due to uniformity.
Description
Technical field
The utility model relates to a kind of structure of substrate, particularly relates to a kind of substrate of making the chip type passive device that is applicable to.
Background technology
Because the trend of microminiaturization day by day that is manufactured with of electronic product, so all are main, passive device also all must be along with the dwindling and reduced volume of circuit board size, to comply with the trend of electronic product microminiaturization.
Chip-R with the chip type passive device, along with dwindling of circuit board size, the Chip-R that present specification is length 0.60mm, width 0.30mm, thickness 0.23mm is used in a large number, because the Chip-R volume is little, so it is the scale error that can allow is very strict, general all in 0.03mm; If with another kind of specification is the Chip-R of length 0.40mm, width 0.20mm, thickness 0.23mm, its allowed scale error will be more strict; So for the low again passive device of small size like this and unit price, the yield of product and production efficiency often become the magic weapon of production firm's struggle for existence.
The making flow process of at present general manufacturer wafer resistor sees also shown in Fig. 3 A-K, and it comprises the following steps:
End face and bottom surface at a blank ceramic substrate 10 are scheduled to make in the scope of resistance, be formed with several interlaced lateral separation lines 11 and vertical defiber 12 with cutter earlier, this lateral separation line 11 all is cut into substrate 10 with vertical defiber 12 certain depth, general corresponding lateral separation line 11 up and down or vertically defiber 12 the degree of depth be no more than substrate 10 thickness half for good, and between adjacent lateral separation line 11 and vertical defiber 12, define a plurality of element regions 14 (as shown in Figure 3A);
End face and bottom surface at these element regions 14 are printed with two corresponding main electrodes 15 respectively, this main electrode 15 is printed in two relatively vertically on the edge of defibers 12 of each element region 14 respectively, Chip-R with length 0.60mm, width 0.30mm, thickness 0.23mm specification is an example, the width of main electrode 15 is 0.15mm, treats that main electrode 15 dry back sintering are to be fixed in (shown in Fig. 3 B) on the element region 14;
Between two main electrodes 15 of element region 14 end faces, be printed with a resistive layer 16, treat that resistive layer 16 dry back sintering are to be fixed in (shown in Fig. 3 C) on the element region 14;
Printing one glass sheath 171 on aforementioned electric resistance layer 16 is treated glass sheath 171 dry back sintering and is fixed in (shown in Fig. 3 D) on the resistive layer 16;
With laser resistive layer 16 is repaired, to adjust resistance value (shown in Fig. 3 E);
On first protective layer 17, coat an external protection 181 again, treat external protection 181 dry back sintering and fix it (shown in Fig. 3 F);
Along each vertical defiber 12 substrate 10 is fractureed in regular turn with tool, form several strip substrates 10 ', and strip substrate 10 ' stacked mutually (shown in Fig. 3 G), wherein the element region 14 on the strip substrate 10 ' becomes the Chip-R unit of vertically arranging one by one;
With vacuum splashing and plating mode internal layer electrode 191 (shown in Fig. 3 H) on the main electrode 15 of element region 14 end faces and bottom surface and strip substrate 10 ' side sputter, this internal layer electrode 191 is the main electrodes 15 in order to Connection Element district 14 end faces and bottom surface;
Each strip substrate 10 ' is fractureed along lateral separation line 11, form a plurality of Chip-Rs unit individuality 20 (shown in Fig. 3 I);
These Chip-R unit individualities 20 are put into the plating tube 30 of electroplating bath (not shown) and plating tube 30 is rotated, such as electroplating in the barrel plating mode, electrode pearl clipped wire 31 in making Chip-R unit individual 20 and electroplating tube 30 does not stop collision and contacts, and after the internal layer electrode 191 of Chip-R unit individuality 20 plated an outer electrode 192 (shown in Fig. 3 J), promptly form Chip-R (shown in Fig. 3 K) one by one.
Yet the shortcoming that aforesaid substrate 10 is applied in the Chip-R processing procedure is as follows:
1. because this lateral separation line 11 all is cut into substrate 10 with vertical defiber 12 certain depth is arranged, therefore the time that institute must spend on basic processing procedure is more, and the intensity that is provided with lateral separation line 11 and vertical 12 pairs of substrates 10 of defiber simultaneously damages easily, cause when follow-up printing main electrode 15, resistive layer 16, easily because of rolling to print in substrate 10 surfaces with cylinder, can't the load pressure of rollers roll of substrate 10, thereby make substrate 10 cracked, influence production efficiency and product yield.
2. because the substrate 10 of ceramic material is subjected to the restriction of its molecular crystalline, therefore substrate 10 is fractureed when becoming strip substrate 10 ', its section must be difficult for smooth (as shown in Figure 4), after meeting influences product shaping the admissible error of length, and when carrying out sputter, the internal layer electrode 191 that causes sputter to form is uneven, more feasiblely carry out follow-up barrel plating formula when electroplating, outer electrode 192 thickness that are coated with are difficult for evenly, and then reduce the production yield of Chip-R.
This shows that above-mentioned existing chip type passive device substrate obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem that chip type passive device substrate exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of novel chip type passive device substrate, just becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned existing chip type passive device substrate exists, the design people is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of novel chip type passive device substrate, can improve general existing chip type passive device substrate, make it have more practicality.Through constantly research, design, and, create the utility model that has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present utility model is, overcome the defective that existing chip type passive device substrate exists, and provide a kind of novel chip type passive device substrate, technical problem to be solved is to make its improvement make the employed board structure of chip type passive device, make its production yield and the efficient that can effectively improve the chip type passive device, thereby be suitable for practicality more.
The purpose of this utility model and to solve its technical problem be to adopt following technical scheme to realize.According to a kind of chip type passive device substrate that the utility model proposes, it mainly is to be formed with the lateral separation line that a plurality of are parallel to each other on a substrate, be formed with plural number between each two defiber and wear groove, defining two adjacent wearing between groove and the defiber is an element region in order to making chip type passive device.
The purpose of this utility model and solve its technical problem and also can adopt following technical measures further to realize.
Aforesaid chip type passive device substrate, wherein said substrate are one with the substrate of pottery as base material.
Aforesaid chip type passive device substrate, corresponding on the wherein said substrate to wear groove be further to be formed with a plurality of vertical defibers vertical with the aforementioned lateral defiber.
Aforesaid chip type passive device substrate, wherein said substrate is to be applied to make chip type resistance.
Via as can be known above-mentioned, the utility model relates to a kind of chip type passive device substrate, be on a substrate, to form a plurality of lateral separation lines that are parallel to each other, between each two defiber, be formed with a plurality of grooves of vertically wearing again, two adjacent wearing are defined as an element region between groove and the defiber, in order to make the chip type passive device; When in the processing procedure of chip type passive device, separating each element region, this is worn groove and can prevent to cause man-hour element region to separate the error of back size because of separation adds, and when in successive process, element region being carried out electroplated electrode, electroplate unlikely inhomogeneous and influence the conductive effect of chip type passive device.
By technique scheme, the utility model chip type passive device substrate has following advantage at least: when fractureing substrate of the present utility model in chip type passive device processing procedure, this wears groove can be avoided the fractureing both sides of element region, prevent that the separating shaped back of each element region size from producing error, and follow-uply can plate uniform electrode again when carrying out electrode plating, thereby process rate is promoted.
In sum, the chip type passive device substrate of the utility model novelty can prevent that the separating shaped back of each element region size from producing error, and process rate is promoted.The utlity model has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on structure or function, have technically than much progress, and produced handy and practical effect, and more existing chip type passive device substrate has the effect of enhancement, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solutions of the utility model, for can clearer understanding technological means of the present utility model, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present utility model can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the vertical view of the utility model substrate.
Fig. 2 A-J is the flow chart that substrate of the present utility model is applied to make Chip-R.
Fig. 3 A-K commonly uses the flow chart that substrate is applied to make Chip-R.
Fig. 4 commonly uses the sectional schematic diagram of making in the Chip-R process strip substrate that forms that substrate fractureed.
10: substrate 10 ': the strip substrate
11: lateral separation line 12: vertical defiber
13: wear groove 131: madial wall
14: element region 15: main electrode
16: 17: the first protective layers of resistive layer
170: trim slots 171: the glass sheath
191: internal layer electrode 192: outer electrode
20: Chip-R unit individuality 30: electroplate tube
31: electrode pearl clipped wire
Embodiment
For further setting forth the utility model is to reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, to according to its embodiment of chip type passive device substrate, structure, feature and the effect thereof that the utility model proposes, describe in detail as after.
Explanation by embodiment, when can being to reach technological means that predetermined purpose takes and effect to get one more deeply and concrete understanding to the utility model, yet appended graphic only provide with reference to the usefulness of explanation, be not to be used for the utility model is limited.
See also shown in Figure 1, it is a preferred embodiment about the utility model chip type passive device substrate, it is a substrate 10 in order to making chip type resistance, be formed with a plurality of orthogonal lateral separation lines 11 and vertical defiber 12 on this substrate 10 in the scope of predetermined making resistance, and wear groove 13 in being formed with respectively between the corresponding two lateral separation lines 11 on each vertical defiber 12, defining two adjacent wearing between groove 13 and the lateral separation line 11 is one in order to make the element region 14 of chip type resistance.Described chip type passive device substrate, this substrate is to be applied to make chip type resistance.
Other sees also shown in Fig. 2 A-J, and it is as described below that aforesaid substrate 10 is used for making the step of chip type resistance:
End face and bottom surface at each element region 14 are printed with two main electrodes 15 respectively, treat to be sintered to fix in element region 14 after its drying, and wherein these main electrodes 15 are to be printed in each element region 14 adjacent inner side slot edge (shown in Fig. 2 A) of wearing groove 13 respectively;
In 15 printings of two main electrodes of element region 14 end faces, one resistive layer 16, and constitute with two main electrodes 15 of element region 14 end faces and to electrically contact, treat after resistive layer 16 dryings its sintering to be fixed in the element region 14 (shown in Fig. 2 B);
Printing one first protective layer 17 is treated it to be sintered to fix (shown in Fig. 2 C) after first protective layer, 17 dryings with this resistive layer 16 of covering protection in each element region 14;
Cut out a trim slots 170 with laser in first protective layer 17, adjust resistance value (shown in Fig. 2 D) by these trim slots 170 finishing resistive layers 16;
Republish the end face in one second protective layer, 18 cladding element districts 14, only expose two main electrodes 15 (shown in Fig. 2 E);
With full wafer substrate 10 longitudinally defiber 12 cut, form several strip substrates 10 ', and strip substrate 10 ' stacked mutually (shown in Fig. 2 F), because wearing groove 13 is to be positioned on vertical defiber 12, therefore the unlikely element region 14 adjacent madial walls 131 of wearing groove 13 that cut to during defiber 12 cutting substrates 10 longitudinally are so this madial wall 131 can be kept smooth;
Plate internal layer electrode 191 (shown in Fig. 2 G) with vacuum splashing and plating or steam depositional mode in the main electrode 15 of element region 14 end faces and bottom surface and the madial wall 131 of wearing groove 13, main electrode 15 in order to Connection Element district 14 end faces and bottom surface, because this madial wall 131 of wearing groove 13 is burnishing surfaces, so internal layer electrode 191 can be coated with equably;
Each strip substrate 10 ' is fractureed along lateral separation line 11, form Chip-R unit individuality 20 (shown in Fig. 2 H) one by one;
These Chip-R unit individualities 20 are inserted in the plating tube 30 of electroplating bath (not shown) and make its rotation, and carry out in the barrel plating mode, use after plating outer electrode 192 (shown in Fig. 2 I, J) on the internal layer electrode 191 of each Chip-R unit individuality 20 respectively, promptly form Chip-R one by one, because the surface of internal layer electrode 191 is very evenly smooth, so the outer electrode 192 that is covered on this internal layer electrode also can evenly entirely be coated with.
From the above, by the formed groove of wearing on the substrate of the present utility model, can make the both sides of element region be a smooth tangent plane, so be applied to make in the chip type passive device processing procedure when substrate separated, with the unlikely both sides that have influence on element region, therefore can make the element region both sides keep smooth, when commonly using making chip type passive device with solution, scale error and the uneven shortcoming of electrode plating are caused in irregular element region both sides, and then promote the yield and the make efficiency of chip type passive device product.
The above, it only is preferred embodiment of the present utility model, be not that the utility model is done any pro forma restriction, though the utility model discloses as above with preferred embodiment, yet be not in order to limit the utility model, any those skilled in the art are not in breaking away from the technical solutions of the utility model scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solutions of the utility model, according to technical spirit of the present utility model to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solutions of the utility model.
Claims (3)
1. chip type passive device substrate is characterized in that:
Be formed with the lateral separation line that a plurality of are parallel to each other on a substrate, form plural number between each two defiber and wear groove, setting two adjacent wearing between groove and the defiber is an element region in order to making chip type passive device.
2. chip type passive device substrate according to claim 1 is characterized in that wherein said chip type passive device substrate is one with the substrate of pottery as base material.
3. chip type passive device substrate according to claim 1 is characterized in that wherein said chip type passive device substrate, correspondingly on this substrate wears the groove place and is formed with a plurality of vertical defibers vertical with the aforementioned lateral defiber.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620004531 CN2935403Y (en) | 2006-03-06 | 2006-03-06 | Wafer-type passive element substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620004531 CN2935403Y (en) | 2006-03-06 | 2006-03-06 | Wafer-type passive element substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2935403Y true CN2935403Y (en) | 2007-08-15 |
Family
ID=38352089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620004531 Expired - Fee Related CN2935403Y (en) | 2006-03-06 | 2006-03-06 | Wafer-type passive element substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2935403Y (en) |
-
2006
- 2006-03-06 CN CN 200620004531 patent/CN2935403Y/en not_active Expired - Fee Related
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |