CN2924643Y

CN2924643Y - Data flow acquisition device

Info

Publication number: CN2924643Y
Application number: CN 200620122434
Authority: CN
Inventors: 郭晓川; 牛仁朝
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2006-07-24
Filing date: 2006-07-24
Publication date: 2007-07-18
Anticipated expiration: 2016-07-24

Abstract

The utility model relates to a testing technology, in particular to a data flow acquisition device, which aims at solving the problem of that the prior data flow acquisition device can not generate incentive data flow. The utility model adds a pretreatment circuit of the incentive data flow to the prior data flow acquisition device, which can pre-treat the pre-tested incentive data flow and then save the incentive data flow in the device, and also read out the specific tested incentive data flow through the device and input into the system circuit to generate test data sources, thereby achieving self-detection when a great deal of data flow was input, reducing or avoiding the usage of expensive dedicated testing equipment.

Description

A kind of data stream harvester

Technical field

The utility model relates to measuring technology, particularly a kind of data stream harvester.

Background technology

Along with the development of technology and improving constantly of living standard, current society has become an informationalized society.People are using the present information electronic equipment to handle various information flows more and more continually, data stream satisfies the ever-increasing various demands of people.To the research of various information electronic devices, the time that performance history also further requires to shorten research and development, test, guarantee the quality of research and development, obtain reliable and stable product as early as possible.In order to reach the above object, need and can carry out collection analysis the data stream of various information electronic devices inside, help the problem in location and the solution product development process.

The technical scheme of existing normally used data stream harvester is that the design chips control circuit is controlled various high capacity random access memory (RAM, Random Access Memory) chip in circuit, utilizes the general controls chip to fit into line data stream and gathers.

As shown in Figure 1, be common data stream harvester 100 structural representations, comprising: general controls chip 101, data processing and RAM chip controls circuit 102 and high capacity RAM chip 103, wherein general controls chip 101 for example can be selected: CPU (central processing unit) (CPU, CentralProcessing Unit), digital signal processor (DSP, Digital Signal Processor), single-chip microcomputer etc., high capacity RAM chip 103 is according to performance and requirement, can but be not limited to use dynamic RAM (DRAM, Dynamic Random Access Memory), static RAM (SRAM, Static Random Access Memory) or flash memory (FLASH, Flash Memory).

The course of work of this device is:

101 controls of general controls chip select one the tunnel to gather from several test data stream (1-n), and for example data stream 1, issues acquisition to data processing and RAM chip controls circuit 102;

Wherein, data stream directly is input in the data acquisition pre-process circuit by the hardware signal line, and the data acquisition pre-process circuit is exactly the circuit that data stream is converted to the inner data layout that needs.

General controls chip 101 can by and chip controls circuit 102 between interface circuit (general controls chip interface circuit 1021) select the data stream that will gather, generally be to indicate the data stream of choosing in the acquisition that issues, and the RAM read-write control signal select circuit 1022 to select 1 again from a plurality of by a control word.

Data processing and RAM chip controls circuit 102 are gathered the circuit-switched data stream of choosing, and test data are flow to other processing such as row cache, framing according to different requirements, these test datas are write high capacity RAM chip 103 again;

Various different requirements also are to be provided with by control word, and concrete control word can design using when realizing, for example can remain the data bit width of sampled data stream, the sampling point number that needs to gather, the storage format of sampling point data in RAM etc.

After the test data capacity of image data stream is finished, general controls chip 101 will be stored in data in the high capacity RAM chip and read and dump on the computing machine that is connected again, and by computing machine analysis result is analyzed and exported to the test data of gathering.

The many kinds of modes that are connected with of data stream harvester 100 and computing machine, for example LAN (Local Area Network), serial ports, parallel port etc., computing machine mainly is responsible for analysis result is analyzed and exported to test data.

As shown in Figure 2, data processing among Fig. 1 and RAM chip controls circuit 102 generally comprise following a few partial circuit: general controls chip interface circuit 1021, RAM read-write control signal select circuit 1022, a n data to gather pre-process circuit 10231～1023n, wherein:

Data acquisition pre-process circuit 10231～1023n carries out pre-service respectively to each drive test examination data stream of input, according to the form that the user needs test data is organized, and selects circuit 1022 to select for the RAM read-write control signal;

General also is by control word the form that needs to be set in each data acquisition pre-process circuit 10231～1023n, concrete control word can determine in when design, for example can remain the data bit width of sampled data stream, the sampling point number that needs to gather, the storage format of sampling point data in RAM etc.

As long as the data stream input is arranged among data acquisition pre-process circuit 10231～1023n, just carry out pre-service, the RAM read-write control signal selects circuit 102 therefrom to select one or more good data of pre-service that read according to the indication of general controls chip then.

General controls chip interface circuit 1021 is used to realize and the communication function of 101 of general controls chips, guarantee the internal register of general controls chip 101 energy calling party designs, and control the RAM read-write control signal by these registers and select circuit 1022 to read the circuit-switched data stream of selection;

Internal register can be understood as some containers of placing order, and general controls chip 101 just can be visited these registers by general controls chip interface circuit 1021, promptly can revise these orders.These registers are direct-connected with other parts of data processing and RAM chip controls circuit, and the value of these registers is sent to various piece, have directly just controlled other parts of circuit, realize by access register so also we can say order control.

The RAM read-write control signal selects circuit 1022 to select a road in each data acquisition pre-process circuit 1023 according to the control of general controls chip 101, generate read-write control signal and give high capacity RAM chip 103, realization is to the read-write operation of high capacity RAM chip 103, comprise: the test data stream that road pre-service in the data acquisition pre-process circuit 1023 that reads is good writes high capacity RAM chip 103, perhaps computing machine is read and sent into to the test data of preserving in the high capacity RAM chip 103.

There is following technical disadvantages in this data stream harvester: this device can only be gathered the data stream in the current system, one piece of data stream can't be input in the circuit system to test; When utilizing this device to test, need the outside test data source of giving, in some system, the external testing data source needs special test equipment to provide, and special test equipment price height, being not easy to use and easily cause instrument damage, cost is too high when producing test in enormous quantities; When curstomer`s site was tested, in that do not have under the special test equipment situation can't orientation problem, the oneself in the time of can't realizing needing the input of substantive test data stream detected.

The utility model content

The utility model provides a kind of data stream harvester, to solve the problem that available data stream harvester can't produce excited data stream.

Data stream harvester described in the utility model, comprise first control module, random access memory and be connected second control module between described first control module and the random access memory, this second control module carries out read/write operation according to the order of first control module to random access memory and handles the data of read/write; Wherein said second control module comprises: interface subelement, read-write control signal chooser unit and at least one road excited data stream pre-service subelement, wherein:

Described first control module issues read/write command by described interface subelement to described read-write control signal chooser unit, orders described read-write control signal chooser unit to read the driving source data from the outside and writes the described random access memory; Perhaps, order described read-write control signal chooser unit to read the driving source data of storage in advance from described random access memory, and send into described excited data stream pre-service subelement, described excited data stream pre-service subelement is excited data stream with the driving source data processing and exports to the outside.

Described second control module also comprises: at least one circuit-switched data is gathered pre-process circuit, described first control module issues acquisition to described data acquisition pre-process circuit, receive the data acquisition pre-process circuit collection of acquisition and handle test data stream, simultaneously issue read command to described read-write control signal chooser unit, described read-write control signal chooser unit reads the test data after the processing and writes described random access memory; The described read-write control signal chooser of perhaps described first control module order unit read test data and export to the outside from random access memory.

Described first control module is central processing unit CPU, digital signal processor DSP or single-chip microcomputer.

Described random access memory is static RAM SRAM, dynamic RAM DRAM or flash memory FLASH.

The beneficial effects of the utility model are as follows:

The utility model goes for gathering the data stream of various information electronic devices inside, generate various excited datas source in advance and be stored in device interior, can read when needed and be sent to each circuit module of device interior as excited data stream and test, selftest when realizing the input of substantive test data stream, to help the problem in location and the solution product development process, data stream harvester described in the utility model can reduce, avoid using expensive special test equipment at curstomer`s site.

Description of drawings

Fig. 1 is common data stream harvester structural representation in the prior art;

Fig. 2 is the structural representation of data processing and RAM chip controls circuit in the device shown in Figure 1;

Fig. 3 is the primary structure synoptic diagram of data stream harvester described in the utility model;

Fig. 4 is the structural representation of data processing and RAM chip controls circuit among Fig. 3.

Embodiment

The utility model is for solving the shortcoming of existing normally used data stream harvester, in available data stream harvester, increased the pre-process circuit of excited data stream, can test stimulus data be carried out being saved in this device after the pre-service in advance, and be input to circuit system and produce the test data source by read this specific test stimulus data from this locality, oneself when so just having realized the input of substantive test data stream detects, and can reduce, avoid using expensive special test equipment.

For realizing above-mentioned technical conceive, as shown in Figure 3, the utility model data stream harvester 300 comprises following structure:

General controls chip 301, data processing and RAM chip controls circuit 302 and high capacity RAM chip 303, wherein general controls chip 301 for example can be selected: central processing unit CPU, digital signal processor DSP, single-chip microcomputer etc., high capacity RAM chip 303 is according to performance and requirement, can but be not limited to use dynamic RAM DRAM, static RAM SRAM or flash memory FLASH.

As shown in Figure 4, the utility model mainly data is handled and RAM chip controls circuit 302 improves, and improves back data processing and RAM chip controls circuit 302 primary structures and comprises:

General controls chip interface circuit 3021, RAM read-write control signal select circuit 3022, a n data to gather pre-process circuit 30231～3023n, n excited data stream pre-process circuit 30241～3024n, wherein, excited data stream pre-process circuit 30241～3024n is respectively applied for pre-service such as framing, sequential adjustment is carried out in the test stimulus data source, produces the excited data stream of specific format and order and exports to outside the use.

Specific design when specific form and order depend on needs and application can keep multiple option during design, selects by register when using; Form comprise excited data stream data bit width, number altogether, in RAM, how to store etc.

The course of work of the utility model data stream harvester comprises:

1, storage excited data source

Various specific detecting large volume excited data sources can be stored in the high capacity RAM chip 303 in advance, the storing process in test stimulus data source is: general controls chip 301 read data files on other position such as the debugging control computing machine at first, and this document has been stored the excited data source of test usefulness; Carry out write operation by data processing and 302 couples of high capacity RAM of RAM chip controls circuit chip, data file is write high capacity RAM chip 303, so just the test stimulus data source has been got well in storage in advance in high capacity RAM chip 303; According to different needs, the test stimulus data source can walk abreast and be stored as multichannel;

2, output drive data stream

In test process, read the excited data source of test usefulness, and the excited data stream of forming specific time sequence is given system's other parts and is tested; The output procedure of test stimulus data stream is, general controls chip 301 control datas are handled and 302 couples of high capacity RAM of RAM chip controls circuit chip 303 carries out read operation, read the test stimulus data source of storage and send into corresponding excited data stream pre-process circuit 30241～3024n, excited data stream pre-process circuit 30241～3024n carries out pre-service such as framing, sequential adjustment respectively to the test stimulus data source, produce the excited data stream of specific format and order and export to outside the use.

Compare with prior art, the utility model device still can be finished following function:

3,301 couples of high capacity RAM of general controls chip chip 303 carries out read-write operation

General controls chip 301 is by general controls chip interface circuit 3021, control RAM read-write control signal is selected circuit 3022, and produce read to high capacity RAM chip 303 by the control signals such as read/write of general controls chip 301, so just realized read/write operation to high capacity RAM chip 303.

4, select to gather and write and be stored in the high capacity RAM chip 303 in various data stream

The utility model gives the data acquisition pre-process circuit 30231～3023n the control of high capacity RAM chip 303, is example with data stream 1; Data acquisition pre-process circuit 30231 carries out the data of input traffic 1 processing such as format conversion and produces read to high capacity RAM chip 303; So just realized selecting to gather the function of various data stream.

The transfer of control can come the announcing circuit part by register, during selection, can select simultaneously more than 1 the tunnel, depend on design concrete application, general controls chip 301 is selected the data of gathering according to using system of the present utility model needs, does not have special requirement.

Data stream harvester of the present utility model can utilize field programmable gate array (FPGA, Field-Programmable Gate Arrays) realizes, also can in other dsp chips or other special IC (ASIC, Application Specific Integrated Circuit), realize.

General controls chip in the data stream harvester of the present utility model can wait with DSP, single-chip microcomputer and realize.

High capacity RAM chip in the data stream harvester of the present utility model can be realized with SRAM, also can wait with DRAM, FLASH and realize; Can use special RAM chip to realize, also can use the internal RAM of FPGA, DSP, ASIC etc. to realize.

Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these are revised and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these changes and modification interior.

Claims

1, a kind of data stream harvester, comprise first control module, random access memory and be connected second control module between described first control module and the random access memory, this second control module carries out read/write operation according to the order of first control module to random access memory and handles the data of read/write; It is characterized in that described second control module comprises: interface subelement, read-write control signal chooser unit and at least one road excited data stream pre-service subelement, wherein:

2, data stream harvester as claimed in claim 1, it is characterized in that, described second control module also comprises: at least one circuit-switched data is gathered pre-process circuit, described first control module issues acquisition to wherein said data acquisition pre-process circuit, receive the data acquisition pre-process circuit collection of acquisition and handle test data stream, simultaneously issue read command to described read-write control signal chooser unit, described read-write control signal chooser unit reads the test data after the processing and writes described random access memory; The described read-write control signal chooser of perhaps described first control module order unit read test data and export to the outside from random access memory.

3, data stream harvester as claimed in claim 1 is characterized in that, described first control module is central processing unit CPU, digital signal processor DSP or single-chip microcomputer.

4, data stream harvester as claimed in claim 1 is characterized in that, described random access memory is static RAM SRAM, dynamic RAM DRAM or flash memory FLASH.