CN2896518Y - Chip packing structure - Google Patents

Chip packing structure Download PDF

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Publication number
CN2896518Y
CN2896518Y CNU2006200004573U CN200620000457U CN2896518Y CN 2896518 Y CN2896518 Y CN 2896518Y CN U2006200004573 U CNU2006200004573 U CN U2006200004573U CN 200620000457 U CN200620000457 U CN 200620000457U CN 2896518 Y CN2896518 Y CN 2896518Y
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China
Prior art keywords
wafer
base plate
bonding wires
chip package
package structure
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Expired - Fee Related
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CNU2006200004573U
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Chinese (zh)
Inventor
林俊宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
Original Assignee
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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Priority to CNU2006200004573U priority Critical patent/CN2896518Y/en
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Publication of CN2896518Y publication Critical patent/CN2896518Y/en
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Abstract

A wafer packaging structure includes a first wafer, a circuit base-plate and a two-phase thermoset sticking layer. Wherein, the first wafer is provided with a first upper surface, a first lateral surface and a first lower surface. The circuit base-plate is provided with an upper surface of the base-plate and a lower surface of the base-plate, and the first wafer is in electric connection with the circuit base-plate. Besides, the two-phase thermoset sticking layer is positioned on the upper surface of the base-plate. The two-phase thermoset sticking layer is provided with a first sticking surface and a second sticking surface. Part of the first sticking surface joints with the first lower surface, and the second sticking surface joints with the upper surface of the base-plate, thereby enabling the first wafer to stick to the upper surface of the circuit base-plate, among which the first sticking surface and the second sticking surface is roughly paralleled, and the two-phase thermoset sticking layer is provided with an edge with gradually reducing thickness.

Description

Chip package structure
Technical field
The utility model relates to a kind of semiconductor element, and particularly relevant for a kind of chip package structure.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly are divided into three phases to integrated circuit: the encapsulation (IC package) of the manufacturing of wafer (wafer), the making of integrated circuit (IC process) and integrated circuit etc.Wherein, wafer (chip) is to make and step such as cutting crystal wafer and finishing via wafer manufacturing, circuit design, light shield (mask), and each cuts formed wafer by wafer, after electrically connecting, can with colloid (encapsulant) material wafer be coated (encapsulate) again via weld pad on the wafer (bonding pad) and outside signal.The purpose of encapsulation is to prevent that wafer is subjected to the influence of moisture, heat, noise, and the media that electrically connects between wafer and the external circuit is provided, and so promptly finishes the encapsulation step of integrated circuit.
Please refer to Fig. 1, it illustrates the generalized section of known a kind of chip package structure.Known chip package structure 100 comprises a wafer 110, a circuit base plate (circuit substrate) 120, one adhesion coating (adhesive layer) 130, many bonding wires (bonding wire) 140 and colloid 150.On the structure, wafer 110 is engaged on the circuit base plate 120 by adhesion coating 130, and the material of adhesion coating 130 for example is epoxy resin (epoxy resin); Electrically, a plurality of weld pads 114 on the upper surface 112 of wafer 110 electrically connect with circuit base plate 120 mutually by these bonding wires 140 respectively.In addition, colloid 150 coating wafers 110, adhesion coating 130 and these bonding wires 140, the function of colloid 150 is for protecting these bonding wires 140 to avoid being subjected to the influence of extraneous moisture, heat and noise.
In detail, when wafer 110 to heat and pressing mode when being adhered on the circuit base plate 120 by adhesion coating 130, (fluid) has flowability because epoxy resin is fluid, present irregular so adhesion coating 130 is understood at the following of the extruding of wafer 110, even can present at the intersection of a side 116 of wafer 110 and adhesion coating 130 because the phenomenon of climbing that capillarity produced, this phenomenon of climbing can be because of the different differences to some extent of viscosity of the material of adhesion coating 130.
Yet, owing to when wafer 110 is adhered on the circuit base plate 120 by adhesion coating 130, adhesion coating 130 still has flowability, so pressurization will make adhesion coating 130 overflows other zones to circuit base plate 120 easily for adhesion coating 130, even contamination line base board 120 and the zone that these bonding wires 140 electrically connect mutually, so will reduce the dose rate that encapsulates.In addition, when adhesion coating 130 applies (spread) after on the circuit base plate 120 in advance, the circuit base plate 120 that these can't have been applied adhesion coating 130 is with stack manner transportation or storage, and must as much as possible wafer 110 be adhered on the circuit base plate 120 immediately,, circuit base plate 120 causes the failure of encapsulation procedure otherwise will being polluted or adhere to other foreign matters.
Please refer to Fig. 2, it illustrates the generalized section of known another kind of chip package structure.In order to improve the problems referred to above, another kind of known chip package structure 200 is suggested.Chip package structure 200 and chip package structure 100 different be in, the wafer 210 in the chip package structure 200 is to be adhered on the circuit base plate 220 by adhesive tape (tape) 230.Owing to adhesive tape is to paste (stick) on circuit base plate 220 via cutting in advance, therefore when wafer 210 is adhered on the circuit base plate 220 by adhesive tape 230, even if through pressing process (compression process), adhesive tape 230 still can kept neat edge away from the outside of wafer 210, that is keep the edge external form that cuts in advance, and adhesive tape 230 can overflow to other zones of circuit base plate 220, and then the zone that electrically connects mutually of contamination line base board 220 and these bonding wires 240.
Yet, after adhesive tape 230 is pasted on the circuit base plate 220 in advance, still can't with these the circuit base plate 220 of Continuous pressing device for stereo-pattern 230 with stack manner transportation or store, and must as much as possible wafer 210 be adhered on the circuit base plate 220 immediately,, circuit base plate 220 causes the failure of encapsulation procedure otherwise will being polluted or adhere to other foreign matters.In view of the above, known chip package structure and encapsulation procedure have improved necessity in fact.
Summary of the invention
The purpose of this utility model provides a kind of chip package structure, pollutes the problem that bonding wire electrically connects the zone to solve the adhesion coating overflow.
Another purpose of the present utility model provides a kind of chip package structure, can't be with stack manner transportation or the problem that stores to solve the circuit base plate that has formed adhesion coating.
For reaching above-mentioned or other purposes, the utility model proposes a kind of chip package structure, comprise one first wafer, a circuit base plate and one or two stage thermosetting adhesion coating (two-stage thermosettingadhesive layer).First wafer has one first upper surface, one first side and one first lower surface, and circuit base plate has a upper surface of base plate and a base lower surface, and first wafer electrically connects mutually with circuit base plate.In addition, two stage thermosetting adhesion coatings are positioned on the upper surface of base plate, two stage thermosetting adhesion coatings have one first bonding plane and one second bonding plane, part first bonding plane engages with first lower surface, second bonding plane engages with upper surface of base plate, so that first wafer is adhered on the upper surface of base plate of circuit base plate, wherein first bonding plane and second bonding plane haply (substantially) parallel, and two stage thermosetting adhesion coatings have the edge (tapered edge) that a thickness reduces gradually.
In an embodiment of the present utility model, the first above-mentioned wafer comprises a plurality of weld pads that are positioned on first upper surface.
In an embodiment of the present utility model, the first above-mentioned wafer comprises a plurality of weld pads that are positioned on first upper surface.In addition, above-mentioned chip package structure more comprises many bonding wires, and at least one of these weld pads electrically connects with upper surface of base plate mutually by at least one of these bonding wires.
In an embodiment of the present utility model, the first above-mentioned wafer comprises a plurality of weld pads that are positioned on first upper surface.In addition, above-mentioned chip package structure more comprises many bonding wires, and at least one of these weld pads electrically connects with upper surface of base plate mutually by at least one of these bonding wires.In addition, above-mentioned chip package structure more comprises colloid, and it coats first wafer and these bonding wires at least.
In an embodiment of the present utility model, above-mentioned chip package structure more comprises one second wafer and an adhesion coating.Second wafer has one second upper surface, one second lower surface and is positioned at a plurality of weld pads on second upper surface.Adhesion coating is disposed between first wafer and second wafer, and wherein second lower surface of second wafer engages with first upper surface of first wafer by adhesion coating.
In an embodiment of the present utility model, above-mentioned chip package structure more comprises one second wafer and an adhesion coating.Second wafer has one second upper surface, one second lower surface and is positioned at a plurality of weld pads on second upper surface.Adhesion coating is disposed between first wafer and second wafer, and wherein second lower surface of second wafer engages with first upper surface of first wafer by adhesion coating.In addition, the material of adhesion coating can be identical with the material of two stage thermosetting adhesion coatings.
In an embodiment of the present utility model, above-mentioned chip package structure more comprises one second wafer and an adhesion coating.Second wafer has one second upper surface, one second lower surface and is positioned at a plurality of weld pads on second upper surface.Adhesion coating is disposed between first wafer and second wafer, and wherein second lower surface of second wafer engages with first upper surface of first wafer by adhesion coating.In addition, above-mentioned chip package structure more comprises many bonding wires, and at least one of these weld pads electrically connects with upper surface of base plate mutually by at least one of these bonding wires.
In an embodiment of the present utility model, above-mentioned chip package structure more comprises one second wafer and an adhesion coating.Second wafer has one second upper surface, one second lower surface and is positioned at a plurality of weld pads on second upper surface.Adhesion coating is disposed between first wafer and second wafer, and wherein second lower surface of second wafer engages with first upper surface of first wafer by adhesion coating.In addition, above-mentioned chip package structure more comprises many bonding wires, and at least one of these weld pads electrically connects with upper surface of base plate mutually by at least one of these bonding wires.In addition, above-mentioned chip package structure more comprises colloid, and it coats first wafer, second wafer and these bonding wires at least.
In an embodiment of the present utility model, above-mentioned circuit base plate comprises a perforation.
In an embodiment of the present utility model, above-mentioned circuit base plate comprises a perforation.In addition, two stage thermosetting adhesion coatings for example are the peripheral regions that is positioned at perforation.
In an embodiment of the present utility model, above-mentioned circuit base plate comprises a perforation.In addition, first wafer comprises a plurality of weld pads that are positioned on first lower surface, and perforation exposes these weld pads.
In an embodiment of the present utility model, above-mentioned circuit base plate comprises a perforation.In addition, first wafer comprises a plurality of weld pads that are positioned on first lower surface, and perforation exposes these weld pads.In addition, above-mentioned chip package structure more comprises many bonding wires, and each weld pad electrically connects with base lower surface mutually by at least one of these bonding wires, and these bonding wires pass through perforation.
In an embodiment of the present utility model, above-mentioned circuit base plate comprises a perforation.In addition, first wafer comprises a plurality of weld pads that are positioned on first lower surface, and perforation exposes these weld pads.In addition, above-mentioned chip package structure more comprises many bonding wires, and each weld pad electrically connects with base lower surface mutually by at least one of these bonding wires, and these bonding wires pass through perforation.Moreover above-mentioned chip package structure more comprises colloid, and it inserts perforation to coat first wafer and these bonding wires at least.
In an embodiment of the present utility model, two above-mentioned stage thermosetting adhesion coatings more comprise an annular relief, be surrounded on first side periphery, and first side engages with annular relief, and an end face of the annular relief of contiguous first side is vertical haply with first side.
In an embodiment of the present utility model, two above-mentioned stage thermosetting adhesion coatings comprise solvent-borne type (solvent type) two stages thermosetting adhesion coating or no-solvent type (non-solvent type) two stages thermosetting adhesion coating.
In an embodiment of the present utility model, the material of two above-mentioned stage thermosetting adhesion coatings comprise polyimides (polyimide), benzocyclobutene (benzocyclobutene, BCB) or poly quinoline (polyquinolin).
In an embodiment of the present utility model, two above-mentioned stage thermosetting adhesion coatings comprise ultraviolet hardening (UV-cured type) two stages thermosetting adhesion coating or thermohardening type (heat-curedtype) two stages thermosetting adhesion coating.
For reaching above-mentioned or other purposes, the utility model proposes a kind of chip package structure, comprise one first wafer, one second wafer, one or two a stage thermosetting adhesion coating and a circuit base plate.First wafer has one first upper surface, one first side and one first lower surface, and second wafer has one second upper surface, one second side and one second lower surface.In addition, two stage thermosetting adhesion coatings are between first wafer and second wafer, wherein two stage thermosetting adhesion coatings have one first bonding plane and one second bonding plane, engage with second lower surface to small part first bonding plane, engage with first upper surface to small part second bonding plane, so that second wafer is adhered on first upper surface of first wafer, wherein first bonding plane is parallel haply with second bonding plane, and two stage thermosetting adhesion coatings have the edge that a thickness reduces gradually.In addition, circuit base plate has a upper surface of base plate and a base lower surface, and first wafer configuration is on upper surface of base plate, and first wafer electrically connects with circuit base plate respectively mutually with second wafer.
In an embodiment of the present utility model, above-mentioned chip package structure more comprises an adhesion coating, is disposed between first wafer and the circuit base plate, and wherein first lower surface of first wafer engages with the upper surface of base plate of circuit base plate by adhesion coating.
In an embodiment of the present utility model, the first above-mentioned wafer comprises a plurality of first weld pads that are positioned on first upper surface, and second wafer comprises a plurality of second weld pads that are positioned on second upper surface.
In an embodiment of the present utility model, the first above-mentioned wafer comprises a plurality of first weld pads that are positioned on first upper surface, and second wafer comprises a plurality of second weld pads that are positioned on second upper surface.In addition, above-mentioned chip package structure more comprises many first bonding wires and many second bonding wires.At least one of these first weld pads electrically connects with upper surface of base plate mutually by at least one of these first bonding wires, and at least one of these second weld pads electrically connects with upper surface of base plate mutually by at least one of these second bonding wires.
In an embodiment of the present utility model, the first above-mentioned wafer comprises a plurality of first weld pads that are positioned on first upper surface, and second wafer comprises a plurality of second weld pads that are positioned on second upper surface.In addition, above-mentioned chip package structure more comprises many first bonding wires and many second bonding wires.At least one of these first weld pads electrically connects with upper surface of base plate mutually by at least one of these first bonding wires, and at least one of these second weld pads electrically connects with upper surface of base plate mutually by at least one of these second bonding wires.In addition, above-mentioned chip package structure more comprises colloid, and it coats first wafer, second wafer, these first bonding wires and these second bonding wires at least.
In an embodiment of the present utility model, the first above-mentioned wafer comprises a plurality of first weld pads that are positioned on first lower surface, and second wafer comprises a plurality of second weld pads that are positioned on second upper surface.
In an embodiment of the present utility model, the first above-mentioned wafer comprises a plurality of first weld pads that are positioned on first lower surface, and second wafer comprises a plurality of second weld pads that are positioned on second upper surface.In addition, above-mentioned chip package structure more comprises many bonding wires and a plurality of solder projection.At least one of these second weld pads electrically connects with upper surface of base plate mutually by at least one of these bonding wires, and each first weld pad electrically connects with upper surface of base plate mutually by one of these solder projections.
In an embodiment of the present utility model, the first above-mentioned wafer comprises a plurality of first weld pads that are positioned on first lower surface, and second wafer comprises a plurality of second weld pads that are positioned on second upper surface.In addition, above-mentioned chip package structure more comprises many bonding wires and a plurality of solder projection.At least one of these second weld pads electrically connects with upper surface of base plate mutually by at least one of these bonding wires, and each first weld pad electrically connects with upper surface of base plate mutually by one of these solder projections.In addition, above-mentioned chip package structure more comprises colloid, and it coats first wafer, second wafer, these bonding wires and these solder projections at least.
In an embodiment of the present utility model, two above-mentioned stage thermosetting adhesion coatings more comprise an annular relief, be surrounded on first side periphery, and first side engages with annular relief, and an end face of the annular relief of contiguous first side is vertical haply with first side.
In an embodiment of the present utility model, two above-mentioned stage thermosetting adhesion coatings more comprise an annular relief, be surrounded on second side periphery, and second side engages with annular relief, and an end face of the annular relief of contiguous second side is vertical haply with second side.
In an embodiment of the present utility model, two above-mentioned stage thermosetting adhesion coatings comprise two stage of solvent-borne type thermosetting adhesion coating or two stage of no-solvent type thermosetting adhesion coating.
In an embodiment of the present utility model, the material of two above-mentioned stage thermosetting adhesion coatings comprises polyimides, benzocyclobutene or poly quinoline.
In an embodiment of the present utility model, two above-mentioned stage thermosetting adhesion coatings comprise two stage of ultraviolet hardening thermosetting adhesion coating or two stage of thermohardening type thermosetting adhesion coating.
Based on above-mentioned, because two stage thermosetting adhesion coatings of chip package structure of the present utility model can be cured as the B rank thermosetting adhesion coating of solid-state or gel state in advance, therefore carry out follow-up when wafer being pressure bonded to circuit base plate or wafer being pressure bonded to the fabrication steps of another wafer, two stage thermosetting adhesion coatings can overflow to other zones of circuit base plate or another wafer, and then the zone that electrically connects of contamination line base board or another wafer and bonding wire.In addition, because two stage thermosetting adhesion coatings of chip package structure of the present utility model can be cured as at room temperature the not adhesive B of tool rank thermosetting adhesion coating in advance, therefore applied the circuit base plate of two stage thermosetting adhesion coatings or mode that wafer can pile up and transported or store.
For above-mentioned and other purposes, feature and advantage of the present utility model can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 illustrates the generalized section of known a kind of chip package structure.
Fig. 2 illustrates the generalized section of known another kind of chip package structure.
Fig. 3 illustrates the generalized section of the chip package structure of the utility model first embodiment.
Fig. 4 illustrates the generalized section of the chip package structure of the utility model second embodiment.
Fig. 5 illustrates the generalized section of the chip package structure of the utility model the 3rd embodiment.
Fig. 6 illustrates the generalized section of the chip package structure of the utility model the 4th embodiment.
Fig. 7 illustrates the generalized section of the chip package structure of the utility model the 5th embodiment.
Fig. 8 illustrates the generalized section of the chip package structure of the utility model the 6th embodiment.
100,200,300,400,500,600,700,800: chip package structure
110,210: wafer
112: upper surface
114,318,566,618: weld pad
116: the side
120,220,320,420,620,740: circuit base plate
130,230,570: adhesion coating
140,240,340,540,580,640,750: bonding wire
150,350,550,650,770: hand over body
310,510,610,710,810: the first wafers
312,512,712: the first upper surfaces
314,414,714,814: the first sides
316,616,716: the first lower surfaces
322,522,742: upper surface of base plate
324,624,744: base lower surface
330,430,530,630,730,830: two stages thermosetting adhesion coating
332,732: the first bonding planes
334,734: the second bonding planes
436,836: annular relief
436a, 836a: end face
560,720,820: the second wafers
562,722: the second upper surfaces
564,726: the second lower surfaces
626: perforation
718: the first weld pads
724: the second sides
728: the second weld pads
760: solder projection
D1, d2: width
E, E ': edge
Embodiment
First embodiment
Please refer to Fig. 3, it illustrates the generalized section of the chip package structure of the utility model first embodiment.The chip package structure 300 of first embodiment comprises one first wafer 310, a circuit base plate 320 and one or two stage thermosetting adhesion coating 330.First wafer 310 has one first upper surface 312, one first side 314 and one first lower surface 316, and circuit base plate 320 has a upper surface of base plate 322 and a base lower surface 324, and first wafer 310 electrically connects mutually with circuit base plate 320.In addition, two stage thermosetting adhesion coatings 330 are positioned on the upper surface of base plate 322, two stage thermosetting adhesion coatings 330 have one first bonding plane 332 and one second bonding plane 334, part first bonding plane 332 engages with first lower surface 316, second bonding plane 334 engages with upper surface of base plate 322, so that first wafer 310 is adhered on the upper surface of base plate 322 of circuit base plate 320, wherein first bonding plane 332 is parallel haply with second bonding plane 334, and two stage thermosetting adhesion coatings 330 have the edge E that a thickness reduces gradually.
In first embodiment, first wafer 310 comprises a plurality of weld pads 318 that are positioned on first upper surface 312.In addition, chip package structure 300 more comprises many bonding wires 340 and colloid 350.These weld pads 318 at least one of them by these bonding wires 340 at least one of them and electrically connect mutually with upper surface of base plate 322, colloid 350 then coats first wafer 310 and these bonding wires 340 at least.The function of colloid 350 for these bonding wires 340 of protection avoiding being subjected to the influence of extraneous moisture, heat and noise, and colloid 350 can support these bonding wires 340 and the body that can hand is provided.
In first embodiment, two stage thermosetting adhesion coatings 330 comprise two stage of solvent-borne type thermosetting adhesion coating or two stage of no-solvent type thermosetting adhesion coating, and both difference are that solvent can increase the flowability of two stage thermosetting adhesion coatings 330, and the material of two stage thermosetting adhesion coatings 330 comprises polyimides, benzocyclobutene or poly quinoline.In addition, two stage thermosetting adhesion coatings 330 comprise two stage of ultraviolet hardening thermosetting adhesion coating or two stage of thermohardening type thermosetting adhesion coating, and it solidifies (cured) respectively by the mode of ultraviolet irradiation or heating.
Below processing procedure that first wafer 310 is adhered to by two stage thermosetting adhesion coatings 330 on the upper surface of base plate 322 of circuit base plate 320 be described in detail.At first, two stage thermosetting adhesion coatings 330 are coated on the upper surface of base plate 322, this moment, two stage thermosetting adhesion coatings 330 were A rank (A-stage) thermosetting adhesion coatings, and it has the characteristic of fluid, for example is the characteristic of liquid (liquid) or colloid (glue).In addition, apply the mode that the mode of two stage thermosetting adhesion coatings 330 on upper surface of base plate 322 can adopt stencilization (stenciling), coating (painting), impression (printing), spraying (spraying), rotary coating (spin-coating) or dipping (dipping) etc.
Then, make two stage thermosetting adhesion coatings 330 solidify (pre-cured) in advance in the mode of ultraviolet irradiation or heating the above-mentioned circuit base plate 320 that has applied two stage thermosetting adhesion coatings 330, this moment, two stage thermosetting adhesion coatings 320 were B rank (B-stage) thermosetting adhesion coatings, it has the characteristic of solid (liquid) or gelinite (gel), and at room temperature it does not have adherence.Therefore, the mode that can pile up of circuit base plate 320 is transported or is stored.In addition, if need carry out follow-up when first wafer 310 is adhered to the fabrication steps of circuit base plate 320, first wafer 310 can be laminated in the mode of ultraviolet irradiation or heating with circuit base plate 320 again, so that first wafer 310 is adhered on the upper surface of base plate 322 of circuit base plate 320 by the two stage thermosetting adhesion coatings 310 that have viscosity once again.Via as can be known above-mentioned, in the process of pressing, be in two stage thermosetting adhesion coatings 330 of the state of B rank thermosetting adhesion coating, be difficult for, and then pollute the zone that upper surface of base plate 322 and these bonding wires 340 electrically connect mutually because of pressure overflow other zones to upper surface of base plate 322.
Second embodiment
Please refer to Fig. 4, it illustrates the generalized section of the chip package structure of the utility model second embodiment.The main difference of second embodiment and first embodiment be in, the external form of two stage thermosetting adhesion coatings 430 of chip package structure 400 is different.Two stage thermosetting adhesion coatings 430 more comprise an annular relief 436, it is surrounded on 414 peripheries, first side, and first side 414 engages with annular relief 436, and an end face 436a of the annular relief 436 of contiguous first side 414 is vertical haply with first side 414.
The formation reason of annular relief 436 is that two stage thermosetting adhesion coatings 430 are cured as the carrying out time of the state of B rank thermosetting adhesion coating in advance by the state of A rank thermosetting adhesion coating.If the time under a certain design high temperature (125 degree for example Celsius) is shorter, the degree of two stage thermosetting adhesion coatings 430 partly solidified (partially cured) of state that by the state-transition of A rank thermosetting adhesion coating is B rank thermosetting adhesion coating is less, therefore carry out follow-up first wafer 410 being heated pressing when being adhered to the fabrication steps of circuit base plate 420, the two stage thermosetting adhesion coatings 430 that are positioned at 414 peripheries, first side can form annular relief 436 because of pressure, and the volume of annular relief 436 is bigger.From the above, under if all the other pressing conditions are constant, the volume of annular relief 430 and two stage thermosetting adhesion coatings 430 are cured as the time correlation that state carried out of B rank thermosetting adhesion coating in advance by the state of A rank thermosetting adhesion coating, that is relevant with the partly solidified degree of two stage thermosetting adhesion coatings 430.
The 3rd embodiment
Please refer to Fig. 5, it illustrates the generalized section of the chip package structure of the utility model the 3rd embodiment.The main difference of the 3rd embodiment and above-mentioned these embodiment be in, chip package structure 500 is a polycrystalline chip package, it more comprises one second wafer 560 and an adhesion coating 570.Second wafer 560 has one second upper surface 562, one second lower surface 564 and a plurality of weld pads 566 that are positioned on second upper surface 562.The material of adhesion coating 570 materials and two stage thermosetting adhesion coatings 530 can be identical, adhesion coating 570 is disposed between first wafer 510 and second wafer 560, and wherein second lower surface 564 of second wafer 560 engages with first upper surface 512 of first wafer 510 by adhesion coating 570.In addition, chip package structure 500 more comprises many bonding wires 580, these weld pads 566 at least one of them by these bonding wires 580 at least one of them and electrically connect mutually with upper surface of base plate 522.In addition, chip package structure 500 more comprises colloid 550, and it coats first wafer 510, second wafer 560 and these bonding wires 540,580 at least.
This mandatory declaration be, in the 3rd embodiment, two stage thermosetting adhesion coatings 530 also can have an annular relief (not illustrating), it is all described as second embodiment that it forms reason, external form, position and engagement relationship etc., so repeat no more in this.
The 4th embodiment
Please refer to Fig. 6, it illustrates the generalized section of the chip package structure of the utility model the 4th embodiment.The main difference part of the 4th embodiment and above-mentioned these embodiment is that the circuit base plate 620 of the chip package structure 600 of the 4th embodiment comprises a perforation 626, and two stage thermosetting adhesion coatings 630 for example are the peripheral regions that is positioned at perforation 626.In addition, first wafer 610 comprises a plurality of weld pads 618 that are positioned on first lower surface 616, and perforation 626 exposes these weld pads 618.In addition, chip package structure 600 more comprises many bonding wires 640, each weld pad 618 by these bonding wires 640 at least one of them and electrically connect mutually with base lower surface 624, and these bonding wires 640 are by perforation 626.Moreover chip package structure 600 more comprises colloid 650, and it inserts perforation 626 to coat first wafer 610 and these bonding wires 640 at least.From the above, the volume of the chip package structure 300,400,500 (seeing Fig. 3, Fig. 4 and Fig. 5) of comparable the foregoing description of volume of the chip package structure 600 of the 4th embodiment is littler.
This mandatory declaration be, in the 4th embodiment, two stage thermosetting adhesion coatings 630 also can have an annular relief (not illustrating), it is all described as second embodiment that it forms reason, external form, position and engagement relationship etc., so repeat no more in this.
The 5th embodiment
Please refer to Fig. 7, it illustrates the generalized section of the chip package structure of the utility model the 5th embodiment.The chip package structure 700 of the 5th embodiment is a polycrystalline chip package, and it comprises one first wafer 710, one second wafer 720, one or two stage thermosetting adhesion coating 730 and a circuit base plate 740.First wafer 710 has one first upper surface 712, one first side 714 and one first lower surface, 716, the second wafers 720 and has one second upper surface 722, one second side 724 and one second lower surface 726.
In addition, two stage thermosetting adhesion coatings 730 are between first wafer 710 and second wafer 720, wherein two stage thermosetting adhesion coatings 730 have one first bonding plane 732 and one second bonding plane 734, engage with second lower surface 726 to small part first bonding plane 732, engage with first upper surface 712 to small part second bonding plane 734, so that second wafer 720 is adhered on first upper surface 712 of first wafer 710, wherein first bonding plane 732 is parallel haply with second bonding plane 734, and two stage thermosetting adhesion coatings 730 have the edge E ' that a thickness reduces gradually.
In addition, circuit base plate 740 has a upper surface of base plate 742 and a base lower surface 744, and first wafer 710 is disposed on the upper surface of base plate 742, and first wafer 710 electrically connects with circuit base plate 740 respectively mutually with second wafer 720.
In the 5th embodiment, first wafer 710 comprises a plurality of first weld pads 718 that are positioned on first lower surface 716, and second wafer 720 comprises a plurality of second weld pads 728 that are positioned on second upper surface 722.In addition, chip package structure 700 more comprises many bonding wires 750 and a plurality of solder projections 760.These second weld pads 728 at least one of them by these bonding wires 750 at least one of them and electrically connect mutually with upper surface of base plate 742, and each first weld pad 718 by these solder projections 760 one of them and electrically connect mutually with upper surface of base plate 742.Moreover chip package structure 700 more comprises colloid 770, and it coats first wafer 710, second wafer 720, these bonding wires 750 and these solder projections 760 at least.
Via as can be known above-mentioned, the main difference part of the 5th embodiment and the 3rd embodiment is that first wafer 710 of adjacent lines substrate 740 is to electrically connect mutually with circuit base plate 740 by chip bonding technology (flip chip bondingtechnology).This mandatory declaration be, described for the associated description of two stage thermosetting adhesion coatings 730 of chip package structure 700 as first embodiment, so repeat no more in this.In addition, in the 5th embodiment, two stage thermosetting adhesion coatings 730 also can have an annular relief (not illustrating), it is surrounded on 724 peripheries, second side and engages with second side 724, and an end face (not illustrating) of the annular relief of contiguous second side 724 is then vertical haply with second side 724.Formation reason as for annular relief is described as second embodiment, so also repeat no more in this.
The 6th embodiment
Please refer to Fig. 8, it illustrates the generalized section of the chip package structure of the utility model the 6th embodiment.The main difference of the 6th embodiment and the 5th embodiment be in, the width d1 of first wafer 810 of chip package structure 800 is greater than the width d2 of second wafer 820.In addition, in the 6th embodiment, two stage thermosetting adhesion coatings 830 also can have an annular relief 836, and it is all described as second embodiment that it forms reason and external form etc., so repeat no more in this.Yet, in the 6th embodiment, two stage thermosetting adhesion coatings 830 are if having an annular relief 836, then annular relief 836 is 814 peripheries, first side that are surrounded on first wafer 810, and first side 814 engages with annular relief 836, and an end face 836a of the annular relief 836 of contiguous first side 814 is vertical haply with first side 814.
In sum, chip package structure of the present utility model has following advantage at least:
(1) because two stage thermosetting adhesion coatings of chip package structure of the present utility model can ultraviolet irradiation or the mode of heating and be cured as the B rank thermosetting adhesion coating of solid-state or gel state in advance, therefore carrying out follow-up heat and when wafer being pressure bonded to circuit base plate or wafer being pressure bonded to the fabrication steps of another wafer, two stage thermosetting adhesion coatings can overflow to other zones of circuit base plate or another wafer, and then the zone that electrically connects of contamination line base board or another wafer and bonding wire.
(2), therefore applied the circuit base plate of two stage thermosetting adhesion coatings or mode that wafer can pile up and transported or store because two stage thermosetting adhesion coatings of chip package structure of the present utility model can ultraviolet irradiation or the mode of heating and be cured as at room temperature the not adhesive B of tool rank thermosetting adhesion coating in advance.
Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; anyly have the knack of this skill person; in not breaking away from spirit and scope of the present utility model; when doing a little change and retouching, therefore protection range of the present utility model is as the criterion when looking the claim person of defining.

Claims (10)

1. chip package structure is characterized in that it comprises:
One first wafer has one first upper surface, one first side and one first lower surface;
One circuit base plate has a upper surface of base plate and a base lower surface, and this first wafer electrically connects mutually with this circuit base plate; And
One or two stage thermosetting adhesion coating, be positioned on this upper surface of base plate, this two stages thermosetting adhesion coating has one first bonding plane and one second bonding plane, this first bonding plane of part engages with this first lower surface, this second bonding plane engages with this upper surface of base plate, so that this first wafer is adhered on this upper surface of base plate of this circuit base plate, wherein this first bonding plane is parallel haply with this second bonding plane, and this two stages thermosetting adhesion coating has the edge that a thickness reduces gradually.
2. chip package structure according to claim 1 is characterized in that it more comprises:
Many bonding wires, wherein this first wafer comprises a plurality of weld pads that are positioned on this first upper surface, and at least one of those weld pads electrically connects with this upper surface of base plate mutually by at least one of those bonding wires; And
Colloid coats this first wafer and those bonding wires at least.
3. chip package structure according to claim 1 is characterized in that it more comprises:
One second wafer has one second upper surface, one second lower surface and is positioned at a plurality of weld pads on this second upper surface;
One adhesion coating is disposed between this first wafer and this second wafer, and wherein this second lower surface of this second wafer engages with this first upper surface of this first wafer by this adhesion coating;
Many bonding wires, at least one of those weld pads electrically connects with this upper surface of base plate mutually by at least one of those bonding wires; And
Colloid coats this first wafer, this second wafer and those bonding wires at least.
4. chip package structure according to claim 1, it is characterized in that wherein said circuit base plate comprises a perforation, this two stages thermosetting adhesion coating is the peripheral region that is positioned at this perforation, this first wafer comprises a plurality of weld pads that are positioned on this first lower surface, and this perforation exposes those weld pads, and this chip package structure more comprises:
Many bonding wires, respectively this weld pad electrically connects with this base lower surface mutually by at least one of those bonding wires, and those bonding wires are by this perforation; And
Colloid is inserted this perforation to coat this first wafer and those bonding wires at least.
5. chip package structure according to claim 1, it is characterized in that wherein said two stage thermosetting adhesion coatings more comprise an annular relief, be surrounded on this first side periphery, and this first side engages with this annular relief, and an end face of this annular relief of contiguous this first side is vertical haply with this first side.
6. chip package structure is characterized in that it comprises:
One first wafer has one first upper surface, one first side and one first lower surface;
One second wafer has one second upper surface, one second side and one second lower surface;
One or two stage thermosetting adhesion coating, between this first wafer and this second wafer, wherein this two stages thermosetting adhesion coating has one first bonding plane and one second bonding plane, engage with this second lower surface to this first bonding plane of small part, engage with this first upper surface to this second bonding plane of small part, so that this second wafer is adhered on this first upper surface of this first wafer, wherein this first bonding plane is parallel haply with this second bonding plane, and this two stages thermosetting adhesion coating has the edge that a thickness reduces gradually; And
One circuit base plate has a upper surface of base plate and a base lower surface, and this first wafer configuration is on this upper surface of base plate, and this first wafer electrically connects with this circuit base plate respectively mutually with this second wafer.
7. chip package structure according to claim 6, it is characterized in that wherein said first wafer comprises a plurality of first weld pads that are positioned on this first upper surface, and this second wafer comprises a plurality of second weld pads that are positioned on this second upper surface, and this chip package structure more comprises:
Many first bonding wires, at least one of those first weld pads electrically connects with this upper surface of base plate mutually by at least one of those first bonding wires;
Many second bonding wires, at least one of those second weld pads electrically connects with this upper surface of base plate mutually by at least one of those second bonding wires; And
Colloid coats this first wafer, this second wafer, those first bonding wires and those second bonding wires at least.
8. chip package structure according to claim 6, it is characterized in that wherein said first wafer comprises a plurality of first weld pads that are positioned on this first lower surface, and this second wafer comprises a plurality of second weld pads that are positioned on this second upper surface, and this chip package structure more comprises:
Many bonding wires, at least one of those second weld pads electrically connects with this upper surface of base plate mutually by at least one of those bonding wires;
A plurality of solder projections, respectively this first weld pad electrically connects with this upper surface of base plate mutually by one of those solder projections; And
Colloid coats this first wafer, this second wafer, those bonding wires and those solder projections at least.
9. chip package structure according to claim 6, it is characterized in that wherein said two stage thermosetting adhesion coatings more comprise an annular relief, be surrounded on this first side periphery, and this first side engages with this annular relief, and an end face of this annular relief of contiguous this first side is vertical haply with this first side.
10. chip package structure according to claim 6, it is characterized in that wherein said two stage thermosetting adhesion coatings more comprise an annular relief, be surrounded on this second side periphery, and this second side engages with this annular relief, and an end face of this annular relief of contiguous this second side is vertical haply with this second side.
CNU2006200004573U 2006-01-11 2006-01-11 Chip packing structure Expired - Fee Related CN2896518Y (en)

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