CN2879196Y - chip testing modular - Google Patents
chip testing modular Download PDFInfo
- Publication number
- CN2879196Y CN2879196Y CN 200620003141 CN200620003141U CN2879196Y CN 2879196 Y CN2879196 Y CN 2879196Y CN 200620003141 CN200620003141 CN 200620003141 CN 200620003141 U CN200620003141 U CN 200620003141U CN 2879196 Y CN2879196 Y CN 2879196Y
- Authority
- CN
- China
- Prior art keywords
- testing module
- circuit film
- line layer
- chip testing
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
This utility model is a chip measuring module positioned with a probe clip, which consists of a circuit board and a circuit membrane. The circuit membrane contains a circuit layer, at least running through an electrical conducting hole and several protruding blocks of the circuit membrane. The circuit layer is positioned on the surface of the first layer of the circuit membrane, the protruding blocks are positioned on the surface of the second layer connecting with the first membrane, and arranged in the ejecting area of the circuit membrane, at least one lead of the protruding block going through the electrical conducting hole is connected with the circuit layer.
Description
Technical field
The utility model relates to a kind of testing element (testing device) and test module (testingmodule), and particularly relevant for a kind of chip testing module of using plunger.
Background technology
The test of integrated circuit (IC) chip (integrated circuit chip, IC chip) all is necessary in the different phase of semiconductor technology (semiconductor process).Each IC chip all must be accepted test to guarantee its electrical functionality (electricalfunction) in wafer (wafer) and encapsulation (package) kenel.Along with the reinforcement of chip functions and complicated, also just more important with accurate testing requirement at a high speed.
In wafer kenel test individual chip, its process is called wafer and surveys (wafer sorting).It is to set up temporary transient electrical the contact between chip and ATE (automatic test equipment) that wafer is surveyed.It is the important test of IC design and function that wafer is surveyed, and filters out good IC chip so that carry out before chip separation and the follow-up encapsulation.
Please refer to Fig. 1, it illustrates the side-looking diagrammatic cross-section of existing a kind of chip testing module.Existing chip testing module 100 is suitable for being electrically connected to the tested surface TS of a chip C, and existing chip testing module 100 comprises a plunger (plunger) 110 and a probe (probe card) 120.Plunger 110 comprises a body (body) 112, and it has an ejection part (pushing part) 112a and the 112b of a basic courses department (base part).
Probe 120 comprises a wiring board (circuit board) 122 and one circuit film (membrane) 124.Wiring board 122 has an opening 122a, and the ejection part 112a of body 112 runs through wiring board 122 through opening 122a.Circuit film 124 has a plurality of overlapped line layers (circuit layer) 124a and a plurality of projection (bump) 124b, wherein these line layers 124a more comprises one first line layer L1, it is configured on the one first film surface 124c of circuit film 124, and these line layers 124a more comprises one second line layer L2, it is configured on the one second film surface 124d with respect to first film surface 124c of circuit film 124, and these projections 124b is configured on the part of the ejection zone PA (pushed area) that is positioned at circuit film 124 of the second line layer L2, in order to the tested surface TS of contact chip C.
Circuit film 124 has more a plurality of conductive through hole 124e (only illustrating one), in order to be electrically connected these line layers 124a.Circuit film 124 has more one first dielectric layer 124f; it is configured on the 124c of first film surface; and the first local line layer L1 of covering; in order to protect the first line layer L1; and circuit film 124 has more one second dielectric layer 124g; it is configured on the 124d of second film surface, and covers the second local line layer L2, in order to protect the second line layer L2.
In addition, probe 120 more comprises at least one capacity cell 126, and it is provided on second film surface 124d of circuit film 124.In addition, the above-mentioned first line layer L1 comprises a power circuit or a ground path.
Below for using existing chip testing module 100 to do an explanation for the process that chip C carries out testing electrical property.Please refer to Fig. 1 and Fig. 2, the side-looking diagrammatic cross-section when wherein Fig. 2 chip testing module of illustrating Fig. 1 is carried out testing electrical property.Be subjected to ejection part 112a (it passes the opening 122a of wiring board 122) institute's ejection of the body 112 of plunger 110 at the ejection zone of circuit film 124 PA, and after a pressure holding zone (pressed area) SA that is connected in ejection zone PA of circuit film 124 was held between 112b of basic courses department and the wiring board 122, circuit film 124, wiring board 122 were fixed together to constitute chip testing module 100 with plunger 110.In test process, have relative displacement between chip C and the chip testing module 100, normally chip C is for vertical movement, so that the tested surface TS of these projections 124b contact chip C of circuit film 124, thereby chip C is carried out testing electrical property.
Yet for the existing chip test module, the circuit film is under the design of high-density wiring, and the access path of first line layer is longer, causes its stray inductance (parasitic inductance) value to increase.In addition, be subject to the making ability of the wiring of circuit film, the number that makes the existing chip test module can test for the signal bonding pad on the tested surface of chip (signal pad) will limit to some extent.In addition, when transmitting high-frequency signal, the long access path of first line layer will increase it and insert loss (insertionloss), and then reduce its transfer efficiency.
The utility model content
The purpose of this utility model provides a kind of chip testing module, to promote its test signal quality.
For reaching above-mentioned or other purpose, the utility model proposes a kind of chip testing module, it comprises a plunger and a probe.Plunger comprises that a body and with an ejection part and a basic courses department is disposed at the conductive layer on the surface of ejection part and basic courses department.Probe comprises a wiring board and a circuit film.Wiring board has an opening, and the ejection part of body runs through wiring board through opening.The circuit film has one first line layer, at least one conductive through hole and a plurality of projection that runs through the circuit film.First line layer is configured on the one first film surface of circuit film, and these projections are disposed at respect on the one second film surface on the first film surface and be positioned at an ejection zone of circuit film, the at least one of these projections is electrically connected with first line layer via conductive through hole, and the part contact that is positioned at the ejection zone of first line layer and the part that is positioned at ejection part of electrical connection conductive layer, and at least one conductive layer that is electrically connected to via conductive through hole of these projections.
For above-mentioned and other purpose, feature and advantage of the present utility model can be become apparent, a plurality of embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrates the side-looking diagrammatic cross-section of existing a kind of chip testing module;
Side-looking diagrammatic cross-section when the chip testing module that Fig. 2 illustrates Fig. 1 is carried out testing electrical property;
Fig. 3 illustrates the side-looking diagrammatic cross-section of a kind of chip testing module of the utility model first embodiment;
Side-looking diagrammatic cross-section when the chip testing module that Fig. 4 illustrates Fig. 3 is carried out testing electrical property;
Fig. 5 illustrates the side-looking diagrammatic cross-section of a kind of chip testing module of the utility model second embodiment;
Fig. 6 illustrates the side-looking diagrammatic cross-section of a kind of chip testing module of the utility model the 3rd embodiment;
Fig. 7 illustrates the side-looking diagrammatic cross-section of a kind of chip testing module of the utility model the 4th embodiment.
Description of reference numerals
100,200,300,400,500: the chip testing module
110,210,510: plunger
112,212: body
112a, 212a, 312a, 512a: ejection part
112b, 212b, 512b: basic courses department
120,220,320: probe
122,222,522: wiring board
122a, 222a: opening
222b, 522b: the first plate surface
522c: the second plate surface
124,224,324,524: the circuit film
124a, 224a: line layer
124b, 224b: projection
124c, 224c, 324c: the first film surface
124d, 224d: the second film surface
124e, 224e: conductive through hole
124f, 224f: first dielectric layer
124g, 224g: second dielectric layer
126,226,326,426: capacity cell
212c, 312c: depression
214,514: conductive layer
C: chip
L1: first line layer
L2: second line layer
PA: ejection zone
S: side
SA: pressure holding zone
T: top
TS: be subjected to the side
Embodiment
Please refer to Fig. 3, it illustrates the side-looking diagrammatic cross-section of a kind of chip testing module of the utility model first embodiment.The chip testing module 200 of first embodiment is suitable for being electrically connected to the tested surface TS of a chip C.Chip testing module 200 comprises a plunger 210 and a probe 220.Plunger 210 comprises a body 212 and a conductive layer 214.Body 212 has an ejection part 212a and a 212b of basic courses department, and conductive layer 214 is disposed at the surface of ejection part 212a and the 212b of basic courses department.
Probe 220 comprises a wiring board 222 and a circuit film 224.Wiring board 222 has an opening 222a, and the ejection part 212a of body 212 runs through wiring board 222 through opening 222a.Circuit film 224 has a plurality of overlapped line layer 224a, a plurality of conductive through hole 224e (only illustrating one) and a plurality of projection 224b that run through circuit film 224, wherein these line layers 224a more comprises one first line layer L1, it is configured on the one first film surface 224c of circuit film 224, and these line layers 224a more comprises one second line layer L2, it is configured on the one second film surface 224d with respect to first film surface 224c of circuit film 224, and these projections 224b is configured in the ejection zone PA that second film surface 224d went up and be positioned at circuit film 224, in order to the tested surface TS of contact chip C.In addition, these projections 224b one of them is electrically connected with the first line layer L1 via conductive through hole 224e at least.
Among first embodiment; circuit film 224 has more one first dielectric layer 224f; it is configured on the 224c of first film surface; and the first local line layer L1 of covering; in order to protecting the first line layer L1, and circuit film 224 has more one second dielectric layer 224g, and it is configured on the 224d of second film surface; and cover the second local line layer L2, in order to protect the second line layer L2.Probe 220 more comprises at least one capacity cell 226 (Fig. 3 illustrates 4), its first film surface 224c that is provided in circuit film 224 upward goes up with second film surface 224d and is positioned at outside the PA of ejection zone, and body 212 more can have a depression 212c, it is positioned on the side S of ejection part 212a, is equipped on lip-deep these capacity cells 226 of first film in order to hold.In addition, in first embodiment, the first line layer L1 comprises a power circuit or a ground path.
Below do an explanation for the chip testing module 200 of using first embodiment for the process that chip C carries out testing electrical property.Please refer to Fig. 3 and Fig. 4, the side-looking diagrammatic cross-section when wherein Fig. 4 chip testing module of illustrating Fig. 3 is carried out testing electrical property.Be subjected to ejection part 212a (it passes the opening 222a of wiring board 222) institute's ejection of the body 212 of plunger 210 at the ejection zone of circuit film 224 PA, and after a pressure holding region S A who is connected in ejection zone PA of circuit film 224 is held between 212b of basic courses department and the wiring board 222, circuit film 224, wiring board 222 will be fixed together to constitute chip testing module 200 with plunger 210.
Therefore, the part contact that is positioned at ejection zone PA of the first line layer L1 and be electrically connected the part that is positioned at ejection part 212a of conductive layer 214, and these projections 224b one of them is electrically connected to conductive layer 214 via conductive through hole 224e at least.The part contact that is positioned at pressure holding region S A of the first line layer L1 and the part that is positioned at the 212b of basic courses department of electrical connection conductive layer 214, and contact of the part of the second line layer L2 and electrical interconnection plate 222.
In test process, have relative displacement between chip C and the chip testing module 200, normally chip C is for vertical movement, so that the tested surface TS of these projections 224b contact chip C of circuit film 224, so that chip C is carried out testing electrical property.When the first line layer L1 comprises a power circuit or a ground path, can increase return flow path to reduce stray inductance by the conductive layer 214 that contacts the wiring board 222 and the first line layer L1 simultaneously.
Please refer to Fig. 5 and Fig. 6, it illustrates the side-looking diagrammatic cross-section of a kind of chip testing module of the utility model second embodiment and the 3rd embodiment respectively.The difference of second embodiment and first embodiment is, these capacity cells 326 that the probe 320 of the chip testing module 300 of second embodiment is included, its part can be provided on first film surface 324c in the ejection zone PA of circuit film 324, and body 312 more can have a depression 312c, it is positioned on the top T of ejection part 312a, in order to hold above-mentioned these capacity cells 326 that are positioned at the ejection zone PA of circuit film 324.Yet, but the position matched combined that sets these capacity cells 326 of the position that sets these capacity cells 226 of first embodiment and second embodiment, the position of these capacity cells 426 that the chip testing module 400 of visible the 3rd embodiment of its array mode is set.
Please refer to Fig. 7, it illustrates the side-looking diagrammatic cross-section of a kind of chip testing module of the utility model the 4th embodiment.The difference of the 4th embodiment and first embodiment is, the circuit film 224 of the chip testing module 200 of first embodiment is to be fixed on first plate surface 222b of wiring board 222, yet the circuit film 524 of the chip testing module 500 of the 4th embodiment is to be fixed on second plate surface 522c of wiring board 522, that is the part of first line layer (not illustrating) contacts and be electrically connected to wiring board 522.In addition, the 512b of basic courses department that is adjacent to ejection part 512a of plunger 510 does not then see through circuit film 524 and directly is fixed on first plate surface 522b of wiring board 522, and the part that is positioned at the 512b of basic courses department of conductive layer 514 will directly contact and the connection pad (not illustrating) of first plate of electrical interconnection plate 522 surface 522b.
In sum, plunger of the present utility model has following advantage at least with the chip testing module of using it:
(1) owing to disposes conductive layer on the surface of plunger of the present utility model, therefore when the testing electrical property chip, the line layer of conductive layer and circuit film contacts with each other, the return flow path of using the line layer that increases the circuit film with shorten its access path, and then make the stray inductance value of line layer of circuit film reduce, insert the loss reduction and cross-talk lowers.
(2), therefore increase regioselectivity and the number that capacity cell is disposed at the circuit film because the body of plunger of the present utility model has the depression that can hold capacity cell.
(3) because the ground path of circuit film can provide extra return flow path by the conductive layer of plunger, thus the design flexibility of the configuration of circuit film can be increased, to improve test quantity for the signal bonding pad of chip.
Though the utility model discloses as above with a plurality of embodiment; right its is not in order to limit the utility model; any those skilled in the art; in not breaking away from spirit and scope of the present utility model; when can doing a little change and retouching, therefore protection domain of the present utility model with appending claims the person of being defined be as the criterion.
Claims (10)
1. chip testing module is characterized in that comprising:
One plunger comprises:
One body has an ejection part and a basic courses department; And
One conductive layer is disposed at the surface of this ejection part and this basic courses department; And
One probe comprises:
One wiring board has an opening, and this ejection part of this body runs through this wiring board through this opening; And
One circuit film, has one first line layer, at least one conductive through hole and a plurality of projection that runs through this circuit film, wherein this first line layer is configured on the one first film surface of this circuit film, those projections are disposed at respect on the one second film surface on this first film surface and be positioned at an ejection zone of this circuit film, the at least one of those projections is electrically connected with this first line layer via this conductive through hole, and the part that is positioned at this ejection zone of this first line layer contacts and is electrically connected the part that is positioned at this ejection part of this conductive layer, and at least one of those projections is electrically connected to this conductive layer via this conductive through hole.
2. chip testing module as claimed in claim 1, it is characterized in that, this probe more comprises at least one capacity cell, it is provided on this first film surface of this circuit film and is positioned at outside this ejection zone, and this body has more a depression, it is positioned on the side of this ejection part, in order to hold this capacity cell.
3. chip testing module as claimed in claim 1, it is characterized in that, this probe more comprises at least one capacity cell, it is provided on this first film surface of this circuit film and is positioned at this ejection zone, and this body has more a depression, it is positioned on the top of this ejection part, in order to hold this capacity cell.
4. chip testing module as claimed in claim 1 is characterized in that this probe more comprises at least one capacity cell, and it is provided on this second film surface of this circuit film.
5. chip testing module as claimed in claim 1 is characterized in that, the part of this first line layer contacts and be electrically connected to this wiring board.
6. chip testing module as claimed in claim 1 is characterized in that, the part of this wiring board contacts and be electrically connected the part that is positioned at this basic courses department of this conductive layer.
7. chip testing module as claimed in claim 1 is characterized in that, the part of this first line layer contacts and be electrically connected to the part that is positioned at this basic courses department of this conductive layer.
8. chip testing module as claimed in claim 1 is characterized in that, this circuit film comprises one second line layer, and it is disposed on this second film surface of this circuit film.
9. chip testing module as claimed in claim 8 is characterized in that, the part of this second line layer contacts and be electrically connected to this wiring board.
10. chip testing module as claimed in claim 8 is characterized in that, this circuit film comprises a plurality of line layers, and it comprises this first line layer and this second line layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620003141 CN2879196Y (en) | 2006-02-22 | 2006-02-22 | chip testing modular |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620003141 CN2879196Y (en) | 2006-02-22 | 2006-02-22 | chip testing modular |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2879196Y true CN2879196Y (en) | 2007-03-14 |
Family
ID=37861616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620003141 Expired - Lifetime CN2879196Y (en) | 2006-02-22 | 2006-02-22 | chip testing modular |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2879196Y (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101949961A (en) * | 2010-08-16 | 2011-01-19 | 中国电子科技集团公司第五十五研究所 | Direct current offset probe card for radio frequency test |
| CN102387657A (en) * | 2010-08-31 | 2012-03-21 | 鸿富锦精密工业（深圳）有限公司 | Circuit board |
| CN103487607A (en) * | 2012-06-07 | 2014-01-01 | 矽品精密工业股份有限公司 | Test device and test method |
| CN105182142A (en) * | 2015-10-16 | 2015-12-23 | 苏州赛腾精密电子股份有限公司 | Probe testing device |
| CN112185926A (en) * | 2020-09-10 | 2021-01-05 | 上海华虹宏力半导体制造有限公司 | Chip bonding pad leading-out device and method |
-
2006
- 2006-02-22 CN CN 200620003141 patent/CN2879196Y/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101949961A (en) * | 2010-08-16 | 2011-01-19 | 中国电子科技集团公司第五十五研究所 | Direct current offset probe card for radio frequency test |
| CN101949961B (en) * | 2010-08-16 | 2012-09-12 | 南京国博电子有限公司 | Direct current offset probe card for radio frequency test |
| CN102387657A (en) * | 2010-08-31 | 2012-03-21 | 鸿富锦精密工业（深圳）有限公司 | Circuit board |
| CN103487607A (en) * | 2012-06-07 | 2014-01-01 | 矽品精密工业股份有限公司 | Test device and test method |
| CN105182142A (en) * | 2015-10-16 | 2015-12-23 | 苏州赛腾精密电子股份有限公司 | Probe testing device |
| CN112185926A (en) * | 2020-09-10 | 2021-01-05 | 上海华虹宏力半导体制造有限公司 | Chip bonding pad leading-out device and method |
| CN112185926B (en) * | 2020-09-10 | 2023-04-28 | 上海华虹宏力半导体制造有限公司 | Chip bonding pad leading-out device and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070314 |
|
| EXPY | Termination of patent right or utility model |