CN2867714Y - Multiplex sine pulsewidth modulation pulse generator and frequency transformer - Google Patents
Multiplex sine pulsewidth modulation pulse generator and frequency transformer Download PDFInfo
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- CN2867714Y CN2867714Y CN 200620053852 CN200620053852U CN2867714Y CN 2867714 Y CN2867714 Y CN 2867714Y CN 200620053852 CN200620053852 CN 200620053852 CN 200620053852 U CN200620053852 U CN 200620053852U CN 2867714 Y CN2867714 Y CN 2867714Y
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Abstract
The utility model relates to a device for generating multiple modulated pulses with sine pulse width. The device comprises a digital signal processing module and a pulse generating unit. The digital signal processing module comprises an input end and a pulse period signal output end. The pulse generating unit comprises a timer and multiple counters. The timer includes a pulse period signal input end connected to the pulse period signal output end of the digital signal processing module and a timing signal output end. Each counter includes a pulse period signal input end connected to the pulse period signal output end, a timing signal input end connected to the timing signal output end of the timer, and a pulse signal output end. The device can achieve dynamic distribution of group number of the output pulse signals. The utility model also provides a transducer used for the device.
Description
[technical field]
The utility model relates to a kind of pulse generating device and adopts the frequency converter of this pulse generating device, relates in particular to a kind of multichannel sinusoidal pulse width modulation pulse generating device and adopts the frequency converter of this multichannel sinusoidal pulse width modulation pulse generating device.
[background technology]
At present, in middle and high pressure frequency conversion field, frequency convertor system based on the modular framework, in order to produce sinusoidal pulse width modulation (the Sinusoidal Pulse-WidthModulation that multichannel has strict phase relation, SPWM) drive waveforms, generally adopt microprogram control unit (Micro ControllerUnit, MCU) mode that combines with timing chip.The micro-programming controller produces basic sinusoidal pulse width modulation number of pulses, is written to the programmable Timer chip then as 8253, produces into pulse by timing chip, finally produces the pulse that multichannel has certain phase difference by the multi-disc timing chip.
The shortcoming that adopts above-mentioned prior art mode to exist is as follows: first, the corresponding fixing group output of each timing chip, so wanting multichannel output is the timing chip of right quantity of will arranging in pairs or groups, when being applied to different output groups and counting, need to change different timing chips, have nothing in common with each other as the timing chips of 3 groups, 6 groups and 10 groups collocation; The second, because output is that hardware is connected with timing chip,, can't satisfy as redundancy so can not realize dynamic-configuration to the group number of output signal, error protections etc. need dynamically to change the requirement of configuration set.
[utility model content]
Be pulse generating device application flexibility difference that overcomes the employing of prior art frequency convertor system and the defective that can't realize the group of output signal is counted dynamic-configuration, the utility model provides a kind of can the realization count the multichannel sinusoidal pulse width modulation pulse generating device of dynamic-configuration to the group of output signal.
The utility model also provides a kind of frequency converter that adopts above-mentioned multichannel sinusoidal pulse width modulation pulse generating device.
A kind of technical scheme that the utility model provides for solving the problems of the technologies described above is: a kind of multichannel sinusoidal pulse width modulation pulse generating device is provided, this device comprises digital signal processing module and pulse generation unit, this digital signal processing module comprises input and pulse-period signal output, this pulse generation unit comprises timer and a plurality of counter, this timer comprises the pulse-period signal input and the timing signal output of the pulse-period signal output that is connected to this digital signal processing module, and each counter comprises the pulse-period signal input of the pulse-period signal output that is connected to this digital signal processing module, be connected to the timing signal input end and the pulse signal output end of the timing signal output of this timer.
The utility model also provides a kind of frequency converter with master control borad, the master control borad of this frequency converter comprises power supply, clock oscillator, multichannel sinusoidal pulse width modulation pulse generating device and memory, this power supply is a clock oscillator, multichannel sinusoidal pulse width modulation pulse generating device and memory provide operating voltage, this clock oscillator clocking also provides to multichannel sinusoidal pulse width modulation pulse generating device, this multichannel sinusoidal pulse width modulation pulse generating device comprises digital signal processing module and pulse generation unit, this digital signal processing module comprises input and pulse-period signal output, the signal that this memory receives and storage is exported by the pulse-period signal output of this digital signal processing module, this pulse generation unit comprises timer and a plurality of counter, this timer comprises the pulse-period signal input and the timing signal output of the pulse-period signal output that is connected to this digital signal processing module, and each counter comprises the pulse-period signal input of the pulse-period signal output that is connected to this digital signal processing module, be connected to the timing signal input end and the pulse signal output end of the timing signal output of this timer.
Compared with prior art, multichannel sinusoidal pulse width modulation pulse generating device of the present utility model is owing to adopt this digital signal processing module in conjunction with the pulse generation unit that comprises timer and a plurality of counters, utilize this digital signal processing module digital processing ability efficiently and pulse generation unit high-speed parallel disposal ability, the function that can realize ideal, the pulse generation unit can be reshuffled flexibly by timer and a plurality of counter, being suitable for different sinusoidal pulse width modulation group numbers needs, need not to change hardware, promptly realize the group of output pulse signal is counted dynamic-configuration.As mentioned above, the utility model adopts the frequency converter of this multichannel sinusoidal pulse width modulation pulse generating device to simplify the program of product seriation, can realize the dynamic-configuration to the group number of output pulse signal simultaneously.
[description of drawings]
Fig. 1 is the module diagram of the utility model multichannel sinusoidal pulse width modulation pulse generating device;
Fig. 2 is the module diagram that the utility model adopts the frequency converter master control borad of multichannel sinusoidal pulse width modulation pulse generating device shown in Figure 1.
[embodiment]
Seeing also Fig. 1, is the schematic diagram of a kind of execution mode of the utility model multichannel sinusoidal pulse width modulation pulse generating device.This multichannel sinusoidal pulse width modulation pulse generating device comprises Digital Signal Processing (Digital Signal Processing, DSP) module 10 and field programmable gate array (Field-Programmable Gate Array, FPGA) 20.This digital signal processing module 10 comprises velocity setting end S0, other given sides S1, process feedback end S2, other feedback ends S4 and pulse-period signal output terminals A D, and this velocity setting end S0, other given sides S1, process feedback end S2, other feedback ends S4 are signal input part.This field programmable gate array 20 comprises timer 2 00 and a plurality of counter 210, this timer 2 00 comprises pulse-period signal input ADI and timing signal output T, and each counter comprises pulse-period signal input ADI, timing signal input end TI, pulse signal output end SPWMX and SPWMY.The pulse-period signal input ADI of this pulse-period signal output terminals A D, this timer and the pulse-period signal input ADI of each counter are with the performance of address/data bus form.
This digital signal processing module 10 is according to the given data of giving of velocity setting end S0 and other given sides S1, and the feedback data of combined process feedback end S2 and other feedback ends S4 calculates the suitable 32-bit number signal of current output, and by this pulse-period signal output terminals A D output, the pulse period of this 32-bit number signal indication impulse waveform.
This field programmable gate array 20 is the pulse generation unit, this timer 2 00 receives the 32-bit number signal in the cycle of this indicating impulse waveform by pulse-period signal input ADI, and by the 24 digit pulse control signals of timing signal output T output corresponding to the cycle of this impulse waveform.The timing signal input end TI count pick up control signal of each counter 210, the pulse-period signal input ADI of each counter 210 receives the 32-bit number signal by the cycle of the impulse waveform of these digital signal processing module 10 outputs, and each counter 210 is counted the numerical signal that this digital signal processing module 10 writes under counting controling signal control, highest order with this counter 210 is exported as pulse, and is exported by the pulse signal output end SPWMX and the SPWMY of this counter 210.
As mentioned above, 10 responsible numerical operations of this digital signal processing module, the waveform generation Task Distribution is produced to this field programmable gate array 20, each counter 210 receives the 32 bit value data that this digital signal processing module 10 writes, under the control of the synchronous timing signal that this timer 2 00 is exported, produce the impulse waveform of the sinusoidal pulse width modulation corresponding by inner sequential logic then with 32 bit value data.
In the present embodiment, this multichannel sinusoidal pulse width modulation pulse generating device adopts this digital signal processing module 10 in conjunction with field programmable gate array 20, utilize these digital signal processing module 10 digital processing abilities efficiently and field programmable gate array 20 high-speed parallel disposal abilities, change the pulse producing method into the multichannel independent mode by master-slave mode.Each road pulse is by independently circuit generation, and phase relation strict between each road guarantees by high-frequency clock.Therefore the phase place that produces multiplex pulse is accurate, high conformity.
Owing to adopt this digital signal processing module 10 in conjunction with field programmable gate array 20, utilize these digital signal processing module 10 digital processing abilities efficiently and field programmable gate array 20 high-speed parallel disposal abilities, the function that can realize ideal.Field programmable gate array 20 can be reshuffled flexibly, and being suitable for different sinusoidal pulse width modulation group numbers needs, and need not to change hardware, promptly realizes the group of output signal is counted dynamic-configuration.The product of seriation also can sharing system control circuit board.Save development cost and maintenance costs.
Seeing also Fig. 2, is the module diagram of frequency converter master control borad that adopts the multichannel sinusoidal pulse width modulation pulse generating device of above-mentioned execution mode.This frequency converter is a 6000V high voltage converter, and its master control borad comprises digital signal processing module 10, field programmable gate array 20 and power supply 30, clock oscillator 40, digital quantity input unit 50, analog input unit 60, communication interface 70, internal storage location 80, memory 90 and the pulse output unit 5 in the above-mentioned execution mode.This power supply 30 uses linear voltage stabilization IC to produce 5V and the 2.5V working power that becomes to need, and this power supply 30 provides 5V working power for digital signal processing module 10, clock oscillator 40, digital quantity input unit 50, analog input unit 60, communication interface 70, internal storage location 80 and memory 90, and this power supply 30 provides 2.5V working power for field programmable gate array 20.Modules such as this digital signal processing module, field programmable gate array 20, internal storage location 80, memory 90 connect with bus.
Adopting clock oscillator 40 to produce the 40M clock signal of system provides to this digital signal processing module 10 and field programmable gate array 20.Various given and feedback signals are input in the digital signal processing module 10 with data-signal by digital quantity input unit 50 and analog input unit 60, this digital signal processing module 10 carries out work at host computer and touch-screen under by the monitoring of communication interface 70, under running status, digital signal processing module 10 is according to given signal, calculation of parameter goes out the number of pulses of current sinusoidal pulse width modulation, write field programmable gate array 20 by bus, produce the impulse waveform output of many group sinusoidal pulse width modulation by field programmable gate array 20.
This master control borad can be realized various configurations, and configuration is directly downloaded in the field programmable gate array 20 by online downloader and is configured, and by disposing 6 groups that can satisfy under the 6000V, also can satisfy 10 groups of 10KV.In fact can realize from 3 to 10 groups configurable group of number.Can realize simultaneously the dynamic-configuration under set group by the mode of digital signal processing module 10 software controls.For example: under the 6000V configuration, when one group of power model breaks down, can dynamically shield the fault group, realize 5 groups of derate operations, not interrupt user load work.This also can realize on the redundancy feature simultaneously.
Claims (10)
1. multichannel sinusoidal pulse width modulation pulse generating device, it is characterized in that: comprise digital signal processing module and pulse generation unit, this digital signal processing module comprises input and pulse-period signal output, this pulse generation unit comprises timer and a plurality of counter, this timer comprises the pulse period address/data bus of the received pulse cycle timing signal output that is connected to this digital signal processing module, and each counter comprises the received pulse periodic signal output pulse period address/data bus that is connected to this digital signal processing module, be connected to the timing signal input end and the pulse signal output end of the timing signal output of this timer.
2. multichannel sinusoidal pulse width modulation pulse generating device as claimed in claim 1 is characterized in that: the pulse-period signal input of this pulse-period signal output, this timer and the pulse-period signal input of each counter are all with the performance of address/data bus form.
3. multichannel sinusoidal pulse width modulation pulse generating device as claimed in claim 1, it is characterized in that: this digital signal processing module calculates pulse-period signal for given data and feedback data and is exported by the pulse-period signal output according to what its input received, the pulse-period signal input of this timer receives this pulse-period signal, and the generation synchronizing clock signals is exported by timing signal output.
4. multichannel sinusoidal pulse width modulation pulse generating device as claimed in claim 3, it is characterized in that: each counter receives this pulse-period signal by its pulse-period signal input, receive this synchronizing clock signals by its timing signal input end, and by the pulse signal output end output impulse waveform corresponding with this pulse-period signal.
5. multichannel sinusoidal pulse width modulation pulse generating device as claimed in claim 3, it is characterized in that: the input of this digital signal processing module comprises given data terminal and feedback signal terminal, input to given data by this given data terminal, by this feedback signal terminal input feedback data.
6. frequency converter with master control borad, the master control borad of this frequency converter comprises power supply, clock oscillator, multichannel sinusoidal pulse width modulation pulse generating device and memory, this power supply is a clock oscillator, multichannel sinusoidal pulse width modulation pulse generating device and memory provide operating voltage, this clock oscillator clocking also provides to multichannel sinusoidal pulse width modulation pulse generating device, it is characterized in that: this multichannel sinusoidal pulse width modulation pulse generating device comprises digital signal processing module and pulse generation unit, this digital signal processing module comprises input and pulse-period signal output, the signal that this memory receives and storage is exported by the pulse-period signal output of this digital signal processing module, this pulse generation unit comprises timer and a plurality of counter, this timer comprises the pulse-period signal input and the timing signal output of the pulse-period signal output that is connected to this digital signal processing module, and each counter comprises the pulse-period signal input of the pulse-period signal output that is connected to this digital signal processing module, be connected to the timing signal input end and the pulse signal output end of the timing signal output of this timer.
7. frequency converter as claimed in claim 6, it is characterized in that: this digital signal processing module calculates pulse-period signal for given data and feedback data and is exported by the pulse-period signal output according to what its input received, the pulse-period signal input of this timer receives this pulse-period signal, and the generation synchronizing clock signals is exported by timing signal output, each counter receives this pulse-period signal by its pulse-period signal input, receive this synchronizing clock signals by its timing signal input end, and by the pulse signal output end output impulse waveform corresponding with this pulse-period signal.
8. frequency converter as claimed in claim 7, it is characterized in that: this frequency converter further comprises digital signal input unit and analog signal input unit, offer this digital signal processing module by this digital signal input unit and analog signal input unit for given data and feedback data, the input of this digital signal processing module comprises given data terminal and feedback signal terminal, input to given data by this given data terminal, by this feedback signal terminal input feedback data.
9. frequency converter as claimed in claim 7 is characterized in that: the pulse-period signal input of this pulse-period signal output, this timer and the pulse-period signal input of each counter are all with the performance of address/data bus form.
10. frequency converter as claimed in claim 7 is characterized in that: this frequency converter further comprises the communication interface that is connected with ancillary equipment.
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CN 200620053852 CN2867714Y (en) | 2006-01-13 | 2006-01-13 | Multiplex sine pulsewidth modulation pulse generator and frequency transformer |
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CN 200620053852 CN2867714Y (en) | 2006-01-13 | 2006-01-13 | Multiplex sine pulsewidth modulation pulse generator and frequency transformer |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101802746B (en) * | 2007-09-20 | 2013-11-27 | 罗伯特·博世有限公司 | Circuit arrangement for signal reception and generation and method for operating said circuit arrangement |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101802746B (en) * | 2007-09-20 | 2013-11-27 | 罗伯特·博世有限公司 | Circuit arrangement for signal reception and generation and method for operating said circuit arrangement |
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