CN102244385A - DVR (dynamic voltage restorer) control system based on DSP (digital signal processor) chip and FPGA (field programmable gate array) chip - Google Patents
DVR (dynamic voltage restorer) control system based on DSP (digital signal processor) chip and FPGA (field programmable gate array) chip Download PDFInfo
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- CN102244385A CN102244385A CN2010101718923A CN201010171892A CN102244385A CN 102244385 A CN102244385 A CN 102244385A CN 2010101718923 A CN2010101718923 A CN 2010101718923A CN 201010171892 A CN201010171892 A CN 201010171892A CN 102244385 A CN102244385 A CN 102244385A
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Abstract
The invention discloses a DVR (dynamic voltage restorer) control system based on a DSP (digital signal processor) chip and an FPGA (field programmable gate array) chip, comprising a central data processing board, a data acquisition board, a cascaded unit scheduling board, a communication interface board, a power board and a drive pulse generation board, wherein the central data processing board, the data acquisition board, the cascaded unit scheduling board and the communication interface board realize data communication by buses; the buses comprise a 16-bit data bus and a 12-bit address bus; and the drive pulse generation board is connected with the cascaded unit scheduling board by an optical fiber so as to realize the data communication. The DVR control system can meet the requirements of quick dynamic response and high computational accuracy and realize the stable data communication as well.
Description
Technical field
The present invention relates to dynamic electric voltage recovery device (the DynamicVoltage Restorer in electric power system and the power electronic technology, DVR) control system, particularly relate to a kind of based on DSP (Digital SignalProcessing, digital signal processing chip) and the dynamic electric voltage recovery device control system of FPGA (Field Programmable Gate Array, field programmable gate array) chip.
Background technology
In all electrical energy power quality disturbances (variation in voltage, harmonic wave, transient state, three-phase are asymmetric etc.), electric voltage dropping occupies very big ratio, become influence the distinct issues of electric load safe operation it
。Electric voltage dropping mainly is that the short trouble of transmission ﹠ distribution supply line causes, and is difficult to fundamentally avoid.In new high-tech industry, many equipment are quite responsive to variation in voltage, and as integrated circuit production line, Digit Control Machine Tool and large data memory device etc., electric voltage dropping can make these users suffer heavy losses.
Dynamic electric voltage recovery device (DVR) not only can be eliminated electric voltage dropping or jump, and can improve harmonic voltage and three-phase asymmetrical voltage, fault current limiting, help to reduce the quality of power supply and worsen economic losses such as caused production interruption, device damage and product rejection, be considered to solve at present the most economic, the effective custom power device of electric voltage dropping problem.At present, mainly concentrate on the aspects such as detection, the output calculating of bucking voltage and dynamic electric voltage tracking Control of voltage about the research of DVR, novel detection method and Novel Control are more and more higher for the requirement of the computational accuracy of control system and computational speed.On the other hand, for the big capacity DVR of middle pressure that adopts the cascade connection multi-level topological structure, how to unify to dispatch between the receipts or other documents in duplicate at different levels unit or mutually intercommunication also be the difficult point that control system faces, existing control system is difficult to satisfy the high request that calculates, and can not realize unified scheduling or intercommunication mutually.
Summary of the invention
Technical problem to be solved by this invention provides a kind of dynamic electric voltage recovery device control system based on DSP and fpga chip, and it can satisfy the requirement of fast dynamic response and high computational accuracy, and can realize stable data communication.
The present invention solves above-mentioned technical problem by following technical proposals: a kind of dynamic electric voltage recovery device control system based on DSP and fpga chip, it is characterized in that, it comprises the central data disposable plates, data acquisition board, cascade cell scheduling plate, communication interface board, power panel and driving pulse generation plate, the central data disposable plates, data acquisition board, cascade cell scheduling plate and communication interface board are realized data communication by bus, bus comprises a sixteen bit data/address bus and one ten two digit address bus, and driving pulse generation plate is connected with cascade cell scheduling plate to realize data communication by optical fiber.
Preferably, described central data disposable plates comprises first dsp chip, second dsp chip, first fpga chip, first power management module and first crystal oscillating circuit, first power management module is connected with first crystal oscillating circuit, first crystal oscillating circuit is connected with first dsp chip, the 2nd DSP and first fpga chip, and first dsp chip, second dsp chip are connected with first fpga chip with an address wire by a data wire separately.
Preferably, described data acquisition board comprises second fpga chip and first modulus conversion chip, the first signal shaping modulate circuit, second source administration module, second crystal oscillating circuit, second fpga chip is connected with first modulus conversion chip, second crystal oscillating circuit, second source administration module, and the first signal shaping modulate circuit is connected with first modulus conversion chip.
Preferably, described cascade cell scheduling plate comprises the 3rd fpga chip, the 3rd power management module, the 3rd crystal oscillating circuit, first optical fiber driving circuit, the 3rd fpga chip is connected with first optical fiber driving circuit, the 3rd power management module, the 3rd crystal oscillating circuit, and the 3rd power management module also is connected with first optical fiber driving circuit.
Preferably, described communication interface board comprises the 3rd dsp chip, the 4th fpga chip, the 4th crystal oscillating circuit, the RS485 interface, the RS23 interface, the CAN interface, USB interface, the HMI interface, SIM interface and Ethernet interface, the 4th crystal oscillating circuit and the 4th fpga chip, the 3rd dsp chip connects, the 4th crystal oscillating circuit provides external clock for the 4th fpga chip and the 3rd dsp chip, the 4th fpga chip and RS485 interface, the data wire of RS232 interface and SIM interface all has separate connection, the 4th fpga chip and USB interface, the shared data wire of HMI interface and Ethernet interface, the 3rd dsp chip links to each other with the data wire of CAN interface, realizes data communication by a shared data/address bus between the 4th fpga chip and the 3rd dsp chip.
Preferably, described driving pulse generation plate comprises the 5th fpga chip, second modulus conversion chip, secondary signal shaping modulate circuit, the 5th crystal oscillating circuit, the 4th power management module, second optical fiber driving circuit, the 5th crystal oscillating circuit is connected with the 5th fpga chip, the 4th power management module is connected with the 4th fpga chip, secondary signal shaping modulate circuit is connected with second modulus conversion chip, and the 5th fpga chip is connected with second modulus conversion chip, second optical fiber driving circuit.
Positive progressive effect of the present invention is: one, utilize two high performance digital signal process chip to realize the control of dynamic electric voltage recovery device, also satisfied the requirement of high computational accuracy when realizing the control system fast dynamic response; Two, the detection of all electrical quantitys of control system is all finished under the control of fpga chip, and sample rate is fast, precision is high, and does not need participating in directly of dsp chip; Three, cascade cell scheduling plate carries out data communication by optical fiber and driving pulse generation plate, thereby control H bridge cascade unit in real time, obtain the state information of cascade unit simultaneously, realize the isolation between low voltage control system and the high pressure hydraulic actuator, strengthened the stability and the reliability of control system operation; Four, the circuit board in the low voltage control system has adopted plug type design flexibly, and data acquisition board and cascade cell scheduling plate can increase and decrease by plugging according to the real system needs.
Description of drawings
Fig. 1 is the principle schematic that the present invention is based on the dynamic electric voltage recovery device control system of DSP and fpga chip.
Fig. 2 is the principle schematic that the present invention is based on the central data disposable plates in the dynamic electric voltage recovery device control system of DSP and fpga chip.
Fig. 3 is the principle schematic that the present invention is based on the data acquisition board in the dynamic electric voltage recovery device control system of DSP and fpga chip.
Fig. 4 is the principle schematic that the present invention is based on the cascade cell scheduling plate in the dynamic electric voltage recovery device control system of DSP and fpga chip.
Fig. 5 is the principle schematic that the present invention is based on the communication interface board in the dynamic electric voltage recovery device control system of DSP and fpga chip.
Fig. 6 is the principle schematic that the present invention is based on the power panel in the dynamic electric voltage recovery device control system of DSP and fpga chip.
Fig. 7 is the principle schematic that the present invention is based on the driving pulse generation plate in the dynamic electric voltage recovery device control system of DSP and fpga chip.
Embodiment
Provide preferred embodiment of the present invention below in conjunction with accompanying drawing, to describe technical scheme of the present invention in detail.
As shown in Figure 1, the dynamic electric voltage recovery device control system that the present invention is based on DSP and fpga chip comprises central data disposable plates 11, data acquisition board 12, cascade cell scheduling plate 13, communication interface board 14, power panel 15 and driving pulse generation plate 16.In the dynamic electric voltage recovery device control system+the 24V power supply provides by power panel 15, and+3.3V power supply is provided by central data disposable plates 11.Central data disposable plates 11, data acquisition board 12, cascade cell scheduling plate 13 and communication interface board 14 are realized data communication by bus 10, and bus 10 comprises a sixteen bit data/address bus (DB0～DB15) and one ten two digit address bus (DA0～DA11).Driving pulse generation plate 16 is connected with cascade cell scheduling plate 13 to realize data communication by optical fiber 17.
As shown in Figure 2, the central data disposable plates comprises first dsp chip (main dsp chip), second dsp chip (from dsp chip), first fpga chip, first power management module and first crystal oscillating circuit.32 floating point DSP chips of high-performance (model is TMS320F28335) that first dsp chip, second dsp chip adopt Texas Instruments are as central processing unit, and first fpga chip (model is EP3C40F324I7) is responsible for the address bus and the data/address bus of control The whole control system.First power management module is connected with first crystal oscillating circuit, and first power management module is from the backplane slot power taking, and general+24V is converted to+send into backplane slot behind the 3.3V, for other circuit boards provide+the 3.3V power supply.First crystal oscillating circuit is connected with first dsp chip, the 2nd DSP and first fpga chip and provides external clock for these three chips.First dsp chip, second dsp chip are separately by sixteen bit data wire (DB0～DB15) and one ten two digit address line (DA0～DA11) be connected with first fpga chip.Both can realize mutual communication between first dsp chip, second dsp chip, also can carry out exchanges data by MCBSP interface (a kind of multichannel buffered serial port) by the data relay of first fpga chip.First dsp chip, second dsp chip are done comprehensive judgement according to feedback signals such as the current voltage of system, electric current, fault-signal and running statuses, calculate PWM (Pulse WidthModulation, pulse-width modulation) duty ratio and generate the PWM duty cycle control signal and be sent to cascade cell scheduling plate.Second dsp chip is as the backup of data processing, share the calculation task of first dsp chip, first fpga chip is according to the order of first dsp chip, second dsp chip, the time-sharing multiplex of control data bus and address bus, thereby the data communication between realization central data disposable plates and data acquisition board, cascade cell scheduling plate and the communication interface board.
As shown in Figure 3, data acquisition board comprises second fpga chip (model is EP1C6Q240C8) and first modulus conversion chip (model is AD7656), the first signal shaping modulate circuit, second source administration module, second crystal oscillating circuit.External voltage, current sensor signal at first insert the first signal shaping modulate circuit, after filtering, shaping, send into first analog-digital chip, second fpga chip is connected with first modulus conversion chip, second crystal oscillating circuit, second source administration module, and the first signal shaping modulate circuit is connected with first modulus conversion chip.Second fpga chip is by sheet choosing (CS), reset (reset), the work of reading (RD), conversion signal controlling first modulus conversion chips such as (convert), first modulus conversion chip can be gathered six tunnel analog signals simultaneously, converts thereof into behind the digital quantity signal again by sixteen bit data wire (AD0～AD15) send in second fpga chip.When first fpga chip on the central data processing plate discharged data/address bus to data acquisition board, second fpga chip on the data acquisition board was responsible for data such as system voltage, electric current are delivered to data/address bus.The second source administration module is from the backplane slot power taking, and general+24V power source conversion is ± be external voltage sensor, current sensor power supply behind the 15V power supply, and general+3.3V power source conversion is for being that second fpga chip is powered behind+1.5V the power supply.Second crystal oscillating circuit provides external clock for second fpga chip.
As shown in Figure 4, cascade cell scheduling plate comprises the 3rd fpga chip (model is EP3C40F324I7), the 3rd power management module, the 3rd crystal oscillating circuit, first optical fiber driving circuit, the 3rd fpga chip is connected with first optical fiber driving circuit, the 3rd power management module, the 3rd crystal oscillating circuit, and the 3rd power management module also is connected with first optical fiber driving circuit.Cascade cell scheduling plate carries out exchanges data by the data/address bus on the backplane slot, address bus and central data disposable plates, carries out data communication with each driving pulse generation plate respectively by optical fiber.The 3rd fpga chip is read (or writing) system data bus according to the moment of the first fpga chip defined on the central data disposable plates.The signal of telecommunication that the 3rd FPGA on the cascade cell scheduling plate sends is converted to light signal through first optical fiber driving circuit, be sent to driving pulse generation plate by optical fiber port, optical signals first optical fiber driving circuit that sends from driving pulse generation plate is converted to the signal of telecommunication and sends into the 3rd fpga chip simultaneously, thereby realizes the data communication between cascade cell scheduling plate and the driving pulse generation plate.The 3rd fpga chip is according to the control signal of central data disposable plates, calculate the phase shifting angle of each H bridge cascade unit, the data message of PWM duty ratio and phase shifting angle is sent to corresponding driving pulse generation plate, receive the fault message and the running state information of driving pulse generation plate feedback simultaneously, a cascade cell scheduling plate can be controlled 12 blocks of driving pulse generation plates at most simultaneously.The 3rd power management module is from the backplane slot power taking, and general+24V power source conversion is for being the power supply of first optical fiber driving circuit behind the+5V, and general+3.3V power source conversion is for being that the 3rd fpga chip is powered behind+the 1.5V.The 3rd crystal oscillating circuit provides external clock for the 3rd fpga chip.
As shown in Figure 5, communication interface board comprises the 3rd dsp chip (model is TMS320F2812), the 4th fpga chip (model is EP1C6Q240C8), the 4th crystal oscillating circuit, RS485 (a kind of serial interface standard) interface, RS232 (a kind of serial interface standard) interface, CAN (ControllerAreaNetwork, controller local area network) interface, USB (Universal Serial Bus, USB) interface, HMI (Human Machine Interface, man-machine interface) interface, communication interfaces such as SIM (SubscriberIdentity Module, client identification module) interface and Ethernet (Ethernet) interface.The 4th crystal oscillating circuit is connected with the 4th fpga chip, the 3rd dsp chip, and the 4th crystal oscillating circuit provides external clock for the 4th fpga chip and the 3rd dsp chip.The data wire of the 4th fpga chip and RS485 interface, RS232 interface and SIM interface all has separate connection, the shared data wire of the 4th fpga chip and USB interface, HMI interface and Ethernet interface, thus realize bidirectional data communication.The 3rd dsp chip links to each other with the data wire of CAN interface, can with its realization bidirectional data communication, link to each other simultaneously, thereby realize sequencing control that data are communicated by letter with the control line of communication interfaces such as USB interface, HMI interface, SIM interface and Ethernet interface.Realize data communication by a shared data/address bus 141 between the 4th fpga chip and the 3rd dsp chip, the 4th fpga chip obtains the operation information of DVR control system from the base plate data/address bus, send external equipment to by ports such as RS485 interface, RS232 interface, SIM interface, USB interface, HMI interface and Ethernet interfaces, simultaneously also send this operation information to the 3rd dsp chip, the 3rd dsp chip sends external equipment to by the CAN interface again.On the other hand, the 4th fpga chip receives external control signal by each communication interface, and sends it to the central data disposable plates by the base plate data/address bus.
Power panel is from Switching Power Supply access+24V, and filtering is common-mode voltage wherein, and carries out over-voltage over-current protection, sends in the backplane slot, for data acquisition board, cascade cell scheduling plate and communication interface board provide+the 24V power supply again.
As shown in Figure 6, driving pulse generation plate comprises the 5th fpga chip (model is EP1C6T144C6), second modulus conversion chip (model is AD7656), secondary signal shaping modulate circuit, the 5th crystal oscillating circuit, the 4th power management module, second optical fiber driving circuit, the 5th crystal oscillating circuit is connected with the 5th fpga chip, the 4th power management module is connected with the 4th fpga chip, secondary signal shaping modulate circuit is connected with second modulus conversion chip, and the 5th fpga chip is connected with second modulus conversion chip, second optical fiber driving circuit.The 5th crystal oscillating circuit provides external clock for the 5th fpga chip.The 4th power management module carries out the voltage regulation filtering conditioning from Switching Power Supply access ± 15V with+5V power supply, and general+5V be converted to+3.3V and+1.5V is that the 4th fpga chip is powered.The external voltage transducer is provided ± the 15V power supply by driving pulse generation plate, inserts second modulus conversion chip behind the sensor signal process secondary signal shaping modulate circuit.The operating state of second modulus conversion chip is controlled by the 5th fpga chip with the operation sequential, and the Sensor Analog Relay System conversion of signals is to be admitted in the 5th fpga chip after the sixteen bit digital signal.
As shown in Figure 1, every block of driving pulse generation plate 16 is controlled four IGBT (Insulated Gate Bipolar Transistor, the three bipolar-type power pipes insulate) drive circuit 18 on the H bridge inverter corresponding to a H bridge cascade unit 19.The phase shifting angle of the PWM duty ratio that the 5th fpga chip provides according to the central data disposable plates, this H bridge cascade unit and the Dead Time of system requirements go out four road corresponding cascade unit triggers pulses by the phase-shifting carrier wave algorithm computation.Driving pulse generation plate is sent to the IGBT drive circuit with trigger impulse, triggers four IGBT drive circuits on the Cascade H bridge after treatment, and the IGBT drive circuit feeds back to driving pulse generation plate with the IGBT fault-signal simultaneously.
As shown in Figure 7, adopt the plug type design on central data disposable plates, data acquisition board, cascade cell scheduling plate, communication interface board and the power panel, have identical first connector 211 and second connector 212, be listed on the different slots of same base plate 21 by these two connectors are slotting.According to the needs of real system, can increase slotting data acquisition board and cascade cell scheduling plate on the base plate to reach the purpose of growth data collection and increase cascade unit number.Comprise on first connector 211+the 3.3V power supply, ground wire (GND), ten two digit address bus DA0～DA11, sixteen bit data/address bus DB0～DB15 and some choosings, read/write enable port.Include on second connector 212+24V power supply and ground wire (GND).First fpga chip on the central data disposable plates is by the choosing of the sheet on first connector 211, read/write enable port, constantly data/address bus is discharged respectively to central data disposable plates, data acquisition board, cascade cell scheduling plate and communication interface board in difference and to carry out read-write operation, realize the data communication of whole system.
The operation principle that the present invention is based on the dynamic electric voltage recovery device control system of DSP and fpga chip is: in each control cycle, first dsp chip of central data disposable plates, second dsp chip data/address bus by backplane slot is from the running status of data acquisition board and cascade cell scheduling plate reading system electric current and voltage and receipts or other documents in duplicate at different levels unit.When detecting the voltage instantaneous mutation, first dsp chip, second dsp chip calculate the PWM duty ratio rapidly according to system voltage instantaneous value, phase place and DC bus-bar voltage etc., are sent to cascade cell scheduling plate via the data/address bus of backplane slot.Control signal and PWM duty ratio that the 3rd fpga chip on the cascade cell scheduling plate is sent according to the central data disposable plates, the driving pulse generation plate of each cascade unit of unified scheduling.The control signal that the 4th fpga chip on the driving pulse generation plate is sent according to cascade cell scheduling plate, calculate the pwm switching signal of receipts or other documents in duplicate at the corresponding levels unit separately, be sent to the IGBT drive circuit after adding the dead band, control opening and turn-offing of relevant IGBT drive circuit, thereby the output bucking voltage suppresses the sudden change of voltage.Because the present invention adopts the common sharing system calculation task of 32 floating point DSPs of two high-performance, thereby computational speed is fast, precision is high, on the other hand, the data acquisition and the data communication of system are controlled by fpga chip, do not need the participation of dsp chip, improve systematic sampling speed and precision greatly, realized the fast dynamic response of system.
Though more than described the specific embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, under the prerequisite that does not deviate from principle of the present invention and essence, can make numerous variations or modification to these execution modes.Therefore, protection scope of the present invention is limited by appended claims.
Claims (6)
1. dynamic electric voltage recovery device control system based on DSP and fpga chip, it is characterized in that, it comprises central data disposable plates, data acquisition board, cascade cell scheduling plate, communication interface board, power panel and driving pulse generation plate, central data disposable plates, data acquisition board, cascade cell scheduling plate and communication interface board are realized data communication by bus, bus comprises a sixteen bit data/address bus and one ten two digit address bus, and driving pulse generation plate is connected with cascade cell scheduling plate to realize data communication by optical fiber.
2. the dynamic electric voltage recovery device control system based on DSP and fpga chip as claimed in claim 1, it is characterized in that, described central data disposable plates comprises first dsp chip, second dsp chip, first fpga chip, first power management module and first crystal oscillating circuit, first power management module is connected with first crystal oscillating circuit, first crystal oscillating circuit is connected with first dsp chip, the 2nd DSP and first fpga chip, and first dsp chip, second dsp chip are connected with first fpga chip with an address wire by a data wire separately.
3. the dynamic electric voltage recovery device control system based on DSP and fpga chip as claimed in claim 1, it is characterized in that, described data acquisition board comprises second fpga chip and first modulus conversion chip, the first signal shaping modulate circuit, second source administration module, second crystal oscillating circuit, second fpga chip is connected with first modulus conversion chip, second crystal oscillating circuit, second source administration module, and the first signal shaping modulate circuit is connected with first modulus conversion chip.
4. the dynamic electric voltage recovery device control system based on DSP and fpga chip as claimed in claim 1, it is characterized in that, described cascade cell scheduling plate comprises the 3rd fpga chip, the 3rd power management module, the 3rd crystal oscillating circuit, first optical fiber driving circuit, the 3rd fpga chip is connected with first optical fiber driving circuit, the 3rd power management module, the 3rd crystal oscillating circuit, and the 3rd power management module also is connected with first optical fiber driving circuit.
5. the dynamic electric voltage recovery device control system based on DSP and fpga chip as claimed in claim 1, it is characterized in that, described communication interface board comprises the 3rd dsp chip, the 4th fpga chip, the 4th crystal oscillating circuit, the RS485 interface, the RS23 interface, the CAN interface, USB interface, the HMI interface, SIM interface and Ethernet interface, the 4th crystal oscillating circuit and the 4th fpga chip, the 3rd dsp chip connects, the 4th crystal oscillating circuit provides external clock for the 4th fpga chip and the 3rd dsp chip, the 4th fpga chip and RS485 interface, the data wire of RS232 interface and SIM interface all has separate connection, the 4th fpga chip and USB interface, the shared data wire of HMI interface and Ethernet interface, the 3rd dsp chip links to each other with the data wire of CAN interface, realizes data communication by a shared data/address bus between the 4th fpga chip and the 3rd dsp chip.
6. the dynamic electric voltage recovery device control system based on DSP and fpga chip as claimed in claim 5, it is characterized in that, described driving pulse generation plate comprises the 5th fpga chip, second modulus conversion chip, secondary signal shaping modulate circuit, the 5th crystal oscillating circuit, the 4th power management module, second optical fiber driving circuit, the 5th crystal oscillating circuit is connected with the 5th fpga chip, the 4th power management module is connected with the 4th fpga chip, secondary signal shaping modulate circuit is connected with second modulus conversion chip, the 5th fpga chip and second modulus conversion chip, second optical fiber driving circuit connects.
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Application publication date: 20111116 |