CN2828985Y - Testing device of computer make-up principle and system structure - Google Patents
Testing device of computer make-up principle and system structure Download PDFInfo
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- CN2828985Y CN2828985Y CN 200520119057 CN200520119057U CN2828985Y CN 2828985 Y CN2828985 Y CN 2828985Y CN 200520119057 CN200520119057 CN 200520119057 CN 200520119057 U CN200520119057 U CN 200520119057U CN 2828985 Y CN2828985 Y CN 2828985Y
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Abstract
The utility model relates to the experimental provision of a kind of Principles of Computer Composition and system architecture, belongs to computer teaching experimental apparatus technical field.This device comprises the single-chip microcomputer of the operational order that is used for receiving the personal computer debugged program, by installing the central processing unit that the user designs and tests, be used to store the storer of the program that the function of central processing unit is tested, the bus transceiver of tri-state bus driver and ternary output.The advantage of the utility model device is, promptly satisfy replication experiment and satisfy open, innovation formula experiment again, the user can design various common CP U, the CPU with flowing water function, the CPU with cache function, super scalar CPU on the utility model device, and successfully the CPU that designs is tested.
Description
Technical field
The utility model relates to the experimental provision of a kind of Principles of Computer Composition and system architecture, belongs to computer teaching experimental apparatus technical field.
Background technology
Principles of Computer Composition and Computer Systems Organization all are the very important basic courses of university.The experimental provision of Principles of Computer Composition has some kinds in the market, Science ﹠ Educational Instrument Factory, Tsinghua Univ.'s TEC-2000 Experiment System of Computer Composition of producing for example, its structured flowchart as shown in Figure 1, Beijing University of Science ﹠ Engineering reaches and wins the TDN-CM++ computing machine that EL-JY computer architecture teaching experimental system that Science and Technology Ltd. produces and Tangdu Science and Educational Instruments Development LLC, Xi'an produce and form and the system architecture teaching experiment system.The TEC-2000 Experiment System of Computer Composition, its structured flowchart as shown in Figure 1.Form an experimental calculation machine by central processing unit (hereinafter to be referred as CPU) and watchdog routine and static random read-write (RAM) storer, debugging software in experimental calculation machine and the personal computer machine is by the RS232 communication, and the debugging software in the personal computer machine is by the debugging of RS232 communication and command experimental calculation machine.The experimental calculation machine is owing to the watchdog routine of having used curing, so the instruction set of experimental calculation machine is fixed.Because CPU is made of 1 on-site programmable gate array FPGA, system architecture is that fix, unmodifiable.Owing to adopted the debugging software on experimental calculation machine and the personal computer machine to debug the experimental calculation machine, can't accomplish the CPU in the experimental provision is carried out the control of half time clock and 1 time clock by the mode of RS232 communication.Especially adopt the watchdog routine of solidifying, instruction set and system architecture are immutable, therefore are unfavorable for bringing into play students'creative.
Summary of the invention
The purpose of this utility model is the experimental provision of design a kind of Principles of Computer Composition and system architecture, carries out design and the detection of the open C PU that instruction set can change at any time on this experimental provision, realizes the changeability of cpu system structure.
The Principles of Computer Composition that the utility model proposes and the experimental provision of system architecture comprise single-chip microcomputer, central processing unit, storer, the first, second, third and the 4th tri-state bus driver, the bus transceiver of the first and second ternary outputs; Wherein
(1) single-chip microcomputer is used for receiving the operational order of personal computer debugged program, and the result that carries out of loopback operational order, and operational order is used for central processing unit is tested;
(2) central processing unit is designed and is tested by the device user, and the clock of central processing unit is provided by single-chip microcomputer;
(3) storer is used to store program and operation result thereof that the function to central processing unit that the said apparatus user writes is tested;
(4) first tri-state bus drivers are used to connect or disconnect the register data bus between single-chip microcomputer and the central processing unit and the logic of single-chip data bus and are connected;
(5) second tri-state bus drivers, the CPU memory address bus that is used to be switched on or switched off between central processing unit and the storer is connected with logic between the memory address bus;
(6) the 3rd tri-state bus drivers are used to be switched on or switched off single-chip microcomputer and are connected with the logic of single-chip data bus with CPU memory address bus between the central processing unit;
(7) the 4th tri-state bus drivers are used to be switched on or switched off single-chip microcomputer and are connected with the logic of single-chip microcomputer address bus with memory address bus between the storer;
The bus transceivers of (8) first ternary outputs are used to be switched on or switched off central processing unit and are connected with the logic of memory data bus with cpu data bus between the storer;
The bus transceivers of (9) second ternary outputs are used to be switched on or switched off single-chip microcomputer and are connected with the logic of memory data bus with single-chip data bus between the storer;
Above-mentioned single-chip microcomputer links to each other with central processing unit by register address bus, cpu clock line, link to each other by the bus transceiver of single-chip data bus with the second ternary output, link to each other with the first, the 3rd tri-state bus driver respectively by the single-chip data bus, link to each other with the 4th tri-state bus driver by the single-chip microcomputer address bus; Above-mentioned central processing unit links to each other with first tri-state bus driver by the register data bus, link to each other by the bus transceiver of cpu data bus, link to each other with second, third tri-state bus driver respectively by the CPU memory address bus with the first ternary output; Above-mentioned storer links to each other with the bus transceiver of first, second ternary output respectively by memory data bus, links to each other with the second, the 4th tri-state bus driver respectively by memory address bus.
The Principles of Computer Composition that the utility model proposes and the experimental provision of system architecture, have and not only satisfy replication experiment but also satisfy advantage open, the experiment of innovation formula, the user can design various common CP U, has the CPU of flowing water function on the utility model device, CPU, the super scalar CPU with high-speed cache (cache) function, and successfully the CPU that designs is tested, compared with the prior art, has better teaching efficiency.Adopt the experimental provision of Principles of Computer Composition of the present utility model and system architecture, realized design and the detection of the open C PU that instruction set that the current experiments device can not be finished can change at any time, realize the changeability of cpu system structure; Realization is carried out half clock and 1 clock and the control of operation continuously to CPU; Realization is to the detection of each internal register of CPU.
Description of drawings
Fig. 1 is the structured flowchart of prior art.
Fig. 2 is the structured flowchart of the experimental provision of the Principles of Computer Composition that the utility model proposes and system architecture.
Fig. 3 (1) and Fig. 3 (2) are the circuit diagrams of an embodiment of the utility model experimental provision.
Embodiment
The structured flowchart of the Principles of Computer Composition that the utility model proposes and the experimental provision of system architecture as shown in Figure 2, comprise single-chip microcomputer K2, central processing unit K9, storer K10, the first, second, third and the 4th tri-state bus driver K3, K7, K8, K5, the bus transceiver K6 and the K4 of the first and second ternary outputs; Wherein
(1) single-chip microcomputer K2 is used for receiving the operational order of personal computer debugged program, and the result that carries out of loopback operational order, and operational order is used for central processing unit K9 is tested;
(2) central processing unit K9 is designed and is tested by the device user, and the clock of central processing unit K9 is provided by single-chip microcomputer;
(3) storer K10 is used to store program and operation result thereof that the function to central processing unit K9 that the said apparatus user writes is tested;
(4) first tri-state bus driver K3 are used to connect or disconnect the register data bus between single-chip microcomputer and the central processing unit and the logic of single-chip data bus and are connected;
(5) second tri-state bus driver K7, the CPU memory address bus that is used to be switched on or switched off between central processing unit and the storer is connected with logic between the memory address bus;
(6) the 3rd tri-state bus driver K8 are used to be switched on or switched off single-chip microcomputer and are connected with the logic of single-chip data bus with CPU memory address bus between the central processing unit;
(7) the 4th tri-state bus driver K5 are used to be switched on or switched off single-chip microcomputer and are connected with the logic of single-chip microcomputer address bus with memory address bus between the storer;
The bus transceiver K6 of (8) first ternary outputs are used to be switched on or switched off central processing unit and are connected with the logic of memory data bus with cpu data bus between the storer;
The bus transceiver K4 of (9) second ternary outputs are used to be switched on or switched off single-chip microcomputer and are connected with the logic of memory data bus with single-chip data bus between the storer;
Above-mentioned single-chip microcomputer K2 links to each other with central processing unit K9 by register address bus, cpu clock line, bus transceiver K4 with the second ternary output links to each other by the single-chip data bus, link to each other with the first, the 3rd tri-state bus driver K3, K8 respectively by the single-chip data bus, link to each other with the 4th tri-state bus driver K5 by the single-chip microcomputer address bus; Above-mentioned central processing unit K9 links to each other with the first tri-state bus driver K3 by the register data bus, bus transceiver K6 with the first ternary output links to each other by cpu data bus, links to each other with second, third tri-state bus driver K7, K8 respectively by the CPU memory address bus; Above-mentioned storer K10 links to each other with bus transceiver K6, the K4 of first, second ternary output respectively by memory data bus, links to each other with the second, the 4th tri-state bus driver K7, K5 respectively by memory address bus.
In the utility model experimental provision with the personal computer of chip microcontroller RS232 communication on debugged program, the method that adopts rule file and assembly language program(me) to combine, by the instruction set of rule file definition CPU, for the changeability of instruction set and cpu system structure provides pacing items; By the test procedure of assembly language file design CPU, under the commander of debugging software, the use test program is tested the CPU of user's design.
CPU in the utility model device is made of a slice field programmable gate array logic (hereinafter to be referred as FPGA) device, mode by software download can download to the CPU of various different system structures such as common CP U, the CPU with flowing water function, the CPU with cache function, super scalar CPU in the fpga chip, Single-chip Controlling CPU does not need the watchdog routine of solidifying.
Debugging software on the personal computer is by the operation of RS232 communication and command single-chip microcomputer, and single-chip microcomputer is encased in the bus transceiver K4 of the cpu test program on the personal computer machine by the 4th tri-state bus driver K5 and the second ternary output among the storer K10.Single-chip microcomputer is by cpu test program and test result among the bus transceiver K4 readout memory K10 of the 4th tri-state bus driver K5 and the second ternary output, by the RS232 communication test procedure and test result delivered to debugged program on the personal computer machine.Single-chip microcomputer provides the clock of CPU, and clock once can be one, half or continuous clock, and half clock is meant that clock once or by low is uprised once by high step-down.CPU passes through the bus transceiver K6 of the second tri-state bus driver K7 and the first ternary output from storer K10 reading command and data, perhaps writes data to storer.Single-chip microcomputer is specified the address of register among the CPU, reads register data among the CPU by the first tri-state bus driver K3, by the RS232 communication data in the register is delivered to debugged program on the personal computer.
Below in conjunction with accompanying drawing, introduce an embodiment of the present utility model in detail.
K1 is the debugging software in the personal computer in Fig. 2.It is made up of three parts, the test procedure of the rule file of defined instruction collection form, the instruction set programming of formulating according to rule file and be responsible for and single-chip microcomputer K2 communication and command to the part of cpu test.Rule file and test procedure all are not to use the person to work out, the user at first writes out rule file, determine the instruction set of self-designed CPU, write out the test procedure of compilation form then, the instruction set that debugged program is determined according to rule file is compiled into test procedure the target program of binary format.Debugging software sends various debug commands by the RS232 communication to single-chip microcomputer, the test procedure (test procedure hereinafter all refers to the test procedure of binary format) of binary format is encased among the storer K10, test procedure reads back from storer K10, whether the checkout program correctly is encased among the storer K10, read and be kept at test result among the storer K10, the debug commands such as value that carry out single step run, the operation of half clock, breakpoint are set, run to breakpoint and read register among the CPU.
K2 is a single-chip microcomputer.It receives the order that the debugging software K1 in the personal computer sends by the RS232 communication, according to these order single-chip microcomputers test procedure is encased among the storer K10, test procedure reads back from storer K10, whether the checkout program correctly is encased among the storer K10, read and be kept at test result among the storer K10, the debug commands such as value that carry out single step run, half clock operation, breakpoint are set, run to breakpoint and read register among the CPU, thus realize the debugging of the CPU K10 in the fpga chip.Single-chip microcomputer provides to storer K10 by tri-state bus driver K5 reading, writing address is provided, and by the data of bus transceiver K4 in storer K10 write data or memory read K10 of three-state output, realizes the reading and writing of single-chip microcomputer to storer K10.Single-chip microcomputer is specified register address among the CPU K10 by the register address bus, reads the value in the CPU register of appointment by tri-state bus driver K3.Single-chip microcomputer monitors the CPU memory address bus by three-state driver K8, and the clock that provides by cpu clock alignment CPU K10 with single-chip microcomputer is realized the control to the cpu test program run.
K3 is a tri-state bus driver.When single-chip microcomputer K2 reads register value among the CPUK10, tri-state bus driver K3 enables, register data bus and single-chip data bus are connected, and other times tri-state bus driver K3 forbids, register data bus and single-chip data bus are isolated.
K4 is the bus transceiver of ternary output.When single-chip microcomputer K2 reading and writing storer K10, enable the bus transceiver of ternary output, memory data bus and single-chip data bus are connected and the tri-state bus driver K5 that enables realizes the reading and writing of single-chip microcomputer to storer jointly.The bus transceiver K4 of the ternary output of other times forbids, memory data bus and single-chip data bus are isolated.
K5 is a tri-state bus driver.When single-chip microcomputer K2 reading and writing storer K10, tri-state bus driver K5 enables, single-chip microcomputer address bus and memory address bus are connected, single-chip microcomputer K2 provides the K10 reading, writing address of storer by tri-state bus driver K5 and the bus transceiver K4 of the three-state that enables output realizes the reading and writing of single-chip microcomputer K2 to storer jointly.Other times tri-state bus driver K5 forbids, single-chip microcomputer address bus and memory address bus are isolated.
K6 is the bus transceiver of ternary output.When CPU K9 reading and writing storer K10, the bus transceiver K6 of ternary output enables, and connection cpu data bus and memory data bus and the tri-state bus driver K7 that enables realize the reading and writing of CPU K9 to storer K10 together.The bus transceiver K7 of the ternary output of other times forbids, cpu data bus and memory data bus are isolated.
K7 is a tri-state bus driver.When CPU K9 reading and writing storer K10, tri-state bus driver K7 enables, CPU memory address bus and memory address bus are connected, CPU K9 provides the storage address of reading and writing by tri-state bus driver K7 to storer, realizes the reading and writing of CPUK9 to storer K10 jointly with the bus transceiver K6 of the three-state output that enables.Other times tri-state bus driver K7 forbids, CPU memory address bus and memory address bus are isolated.
K8 is a tri-state bus driver.When single-chip microcomputer K2 need read the value of CPU memory address bus, enable tri-state bus driver K8, forbid tri-state bus driver K3, forbid the bus transceiver K4 of ternary output.When single-chip microcomputer K2 does not read the value of CPU memory address bus, forbid tri-state bus driver K8.
K9 is the CPU of the user's design among the FPGA.The clock of CPU K9 is provided by single-chip microcomputer K2.Single-chip microcomputer K2 specifies register address by CPU register address bus to CPU K9, reads the register value of appointment from CPU K10 by tri-state bus driver K3.CPU K9 sends storage address by tri-state bus driver K7 to storer K10, and the bus transceiver K6 that exports by three-state carries out reading and writing to storer K10.Single-chip microcomputer K2 reads the CPU memory address bus by tri-state bus driver K8.
K10 is a storer.Storer K10 accepts the reading and writing of single-chip microcomputer K2 and CPU K9.When single-chip microcomputer K2 reading and writing storer K10, the bus transceiver K4 of ternary output enables, and connects single-chip data bus and memory data bus, and the bus transceiver K6 of ternary output forbids, isolates cpu data bus and memory data bus; Tri-state bus driver K5 enables, and connects single-chip microcomputer address bus and memory address bus, and tri-state bus driver K7 forbids, isolates CPU memory address bus and memory address bus; Thereby realize the reading and writing of single-chip microcomputer K2 to storer K10.When CPU K9 reading and writing storer K10, the ternary bus transceiver K6 that exports enables, and connects cpu data bus and memory data bus, and the bus of ternary output sends reception K5 forbids, isolates single-chip data bus and memory data bus; Tri-state bus driver K7 enables, and connects CPU memory address bus and memory address bus, and tri-state bus driver K5 forbids, isolates single-chip microcomputer address bus and memory address bus; Thereby realize the reading and writing of CPUK9 to storer.
In Fig. 3 (1) and (2):
Single-chip microcomputer K2 among Fig. 2 is made up of the electrochemical capacitor C1 of crystal oscillator CY, the capacity 10 μ F of single chip computer AT 89S52 U1, oscillation frequency 11.0592MHz among Fig. 3 (1), resistance R 3, single-chip microcomputer reset button KD3, level shifting circuit MAX233 U3,9 needle socket U4, eight D type transparent latch 74LS373 U5,3-8 code translator 74LS138 U6 and the generic array logic GAL16V8 U7 of resistance 1K ohm.
AT89S52 U1 is the single-chip microcomputer of 8 D0-D7 of a data bus, 16 A0-A15 of address bus, wherein the least-significant byte A0-A7 of address bus and data bus D0-D7 are time-sharing multiplexs, use latch signal ALE that the least-significant byte A0-A7 of address bus is separated from data bus D0-D7,74LS373 U5 finishes the function of the least-significant byte A0-A7 that isolates address bus, and low 3 A8-A10 in the least-significant byte A0-A7 of address bus and the most-significant byte form single-chip microcomputer address bus A0-A10 jointly.High 5 of address bus are not used as address bus, they as control signal S1, S2, S3 ,/SELMDL and/SELMDL uses.S1, S2 and S3 through 3-8 code translator 74LS138 U6 decoding back generation/SELFAL ,/SELFAH ,/SELREGL and/SELREGH; When/when SELFAL is low level, enable the least-significant byte FA0-FA7 and the single-chip data bus D0-D7 of 74LS244 U16, connection cpu address bus; When/when SELFAH is low, enable 74LS244 U15, connect the most-significant byte FA8-FA8 and the single-chip data bus D0-D7 of cpu address bus; When/when SELMDL is low level, enable 74LS245 U13, connect single-chip data bus D0-D7 and memory data bus least-significant byte RD0-RD7; When/when SELMDH is low level, enable 74LS245 U12, connect single-chip data bus D0-D7 and memory data bus most-significant byte RD8-RD15./ SELMDL and/SELMDH directly uses as control signal on the one hand, is connected to GAL16V8 U7 on the other hand and produces other control signals; When/when SELMDL is low level, enable 74LS245 U13, connect the least-significant byte RD0-RD7 of single-chip data bus D0-D7 and memory data bus; When/when SELMDH is low level, enable 74LS245 U12, connect the most-significant byte RD8-RD15 of single-chip data bus D0-D7 and memory data bus.Serial communication signals RXD and TXD that AT89S52 U1 produces are sent to MAX233 U3, be used for the personal computer machine on debugging software K1 carry out the RS232 communication.The ale signal of AT89S52 U1 output is sent to 74LS373 U5, and the memory address bus on the single-chip data bus D0-D7 is separated, and forms the least-significant byte A0-A7 of memory address bus.AT89S52 (U1) produces/and WRD/WWR memory read, write signal be sent to GAL16V8 U7 together with common reading and writing and the chip selection signal that produces storer HM6116 U10 and U11 of other signals.AT89S52 U1 produces/and the RAMCTL signal is sent to 74LS245 U19 and U20, is sent to 74LS244 U17 and U18, is sent to GAL16V8 U7.When/when RANCTL is low level, enable 74LS245 U19 and U20, connect cpu data bus FD0-FD15 and memory data bus RD0-RD15; Enable 74LS244 U17 and U18, connect low 11 FA0-FA10 of cpu address bus and memory address bus RA0-RA10.Be sent to GAL16V8 U7 /RAMCTL produces RAMCTL after GAL16V8 U7 is anti-phase.The CPUCLK of AT89S52 U1 output is sent to the clock of CPU U14 as CPU.The REGA0-REGA5 of AT89S52 U1 output is sent to CPU U14 as register address.There is the FLASH storer (being commonly referred to as flash memory) of a 8K byte AT89S52 U1 inside, storage watchdog routine, the operation of watchdog routine commander AT89S52 U1.
CY is a crystal oscillator that oscillation frequency is 11.0592MHz, and it provides the clock of AT89S52.
C1 is the electric capacity of one 10 μ F, and R3 is the resistance of a resistance 2K ohm, and they produce+the required reset signal of AT89S52 U1 when 5 volts of power supplys power up jointly.
KD3 is a single-chip microcomputer reset button, presses reset button, produces the reset signal of an AT89S52 U1.
Level translator MAX233 U3 is one will become to meet RXD and the TXD signal that RS232 communication level requires with the TXD conversion of signals from the RXD that RS232 communication level requires that do not meet of AT89S52 U1.
U4 is one 9 needle socket, the RS232 communication cable that the debugging software communication uses on connection and the personal computer machine.
U5 is latch 74LS373.As the ALE from AT89S52 U1 when being high, U5 latchs the memory address signal that comprises on the single-chip data bus D0-D7, generates the least-significant byte FA0-FA7 of single-chip microcomputer address bus.
U6 is a 3-8 code translator 74LS138, it will be decoded into from signal S0, S1 and the S2 of AT89S52 U1/SELFAL ,/SELFAH ,/SELREGL and/SELREGH.When/when SELFAL is low level, enable 74LS244 U16, connect the least-significant byte FA0-FA7 and the single-chip data bus D0-D7 of cpu address bus.When/when SELFAH is low level, enable 74LS244 U15, connect the most-significant byte FA8-FA15 and the single-chip data bus D0-D7 of cpu address bus.When/when SELREGL is low level, enable 74LS244 U21, connect the least-significant byte REGD0-REGD7 and the single-chip data bus D0-D7 of register bus.When/when SELREGH is low level, enable 74LS244 U22, connect the most-significant byte REGD8-REGD15 and the single-chip data bus D0-D7 of register data bus.
U7 is gate array logic device GAL16V8.It will from signal/SELMDL of AT89S52 U1 ,/SELMDH ,/RAMCTL ,/MRD ,/MWR, from signal/CPURD of CPU U14 ,/CPUWR through combinational logic decoding convert to signal/RAM1 ,/RAM2, RAMCTL ,/RWR and/ROE./ RAM1 is the chip selection signal of HM6116 U10, when/when RAM1 is low level, choose HM6116 U10./ RAM2 is the chip selection signal of HM6116 U11, when/when RAM2 is low level, choose HM6116 U11./ ROE is the read signal of HM6116 U10 and U11, and low level is effective./ RWR is the write signal of HM6116 U10 and U11, and low level is effective.When RAMCTL is low level, enable 74LS244 U8 and U9, connect single-chip microcomputer address bus A0-A10 and memory address bus RA0-RA10.
The first tri-state bus driver K3 among Fig. 2 is made up of two 74LS244 U21 among Fig. 3 (2) and U22.When/when SELREGL is low level, enable 74LS244 U21, with the least-significant byte REGD0-REGD7 and the single-chip data bus D0-D7 connection of register data bus; When/when SELREGH is low level, enable 74LS244 U22, with the most-significant byte REGD8-REGD15 and the single-chip data bus D0-D7 connection of register data bus./ SELREGL and/SELREGH produces by 74LS138 U6.
The bus transceiver (K4) of the ternary output of second among Fig. 2 is made up of two 74LS245 U12 among Fig. 3 (1) and U13.When/when SELMDL was low level, 74LS245 U13 enabled, with the least-significant byte RD0-RD7 connection of single-chip data bus D0-D7 and memory data bus; When/when SELMDH was low level, 74LS245 U12 enabled, with the most-significant byte RD8-RD15 connection of single-chip data bus D0-D7 and memory data bus./ MRD control data transmission direction, when/when MRD is low level, from memory data bus to the single-chip data bus transmissioning data; When/when MRD is high level, from transmitting data to single-chip data bus driver data bus./ SELMDL ,/SELMDH and/MRD produces by single chip computer AT 89S52 U1.
The 4th tri-state bus driver K5 among Fig. 2 is by being made up of two 74LS244 U8 and U9 among Fig. 3 (1).When RAMCTL was low level, 74LS244 U8 and U9 enabled, and connected single-chip microcomputer address bus A0-A10 and memory address bus.RAMCTL is produced by GAL16V8 U7, and it is that single chip computer AT 89S52 U1 provides/RAMCTL anti-phase.
The bus transceiver K6 of the ternary output of first among Fig. 2 is made up of two 74LS245 U19 among Fig. 3 (2) and U20.When/when RAMCTL was low level, 74LS245 U19 and U20 enabled, and connected cpu data bus FD0-FD15 and memory data bus RD0-RD15.When/when CPURD was low level, data were sent to cpu data bus from memory data bus; When/when CPURD was high level, data were sent to memory data bus from cpu data bus./ RAMCTL is by being provided by single chip computer AT 89S52 U1, and/CPURD is provided by CPU U14.
The second tri-state bus driver K7 among Fig. 2 is made up of two 74LS244 U17 among Fig. 3 (2) and U18.When/when RAMCTL was low level, two 7,4LS,244 17 and U18 enabled, the FA0-FA10 of cpu address bus and the RA0-RA10 of memory address bus are connected./ RAMCTL is provided by single chip computer AT 89S52 U1
The 3rd tri-state bus driver K8 among Fig. 2 is made up of two 74LS244 U21 among Fig. 3 (2) and U22.When/when SELREGL was low level, 74LS244 U21 enabled, and the least-significant byte REGD0-REGD7 of register data bus and single-chip data bus D0-D7 connect.When/when SELREGH was low level, 74LS244 U22 enabled, and the most-significant byte REGD8-REGD15 of register data bus and single-chip data bus D0-D7 connect./ SELREGL and/SELREGH can not be a low level simultaneously, they are produced by 74LS138 U6.
CPU K9 among Fig. 2 is exactly the CPU U14 among Fig. 3 (2), and it is that a slice capacity is 100,000 a FPGA device, and model is EP1K100.The CPU of user design downloads in the EP1K100 device back and constitutes CPU to be tested such as, the system architecture of CPU inside can vary, but its outside input and output pin must be tested with the consistent ability of pin of U14 regulation among Fig. 3 (2) with the clock pin.The clock CPUCLK of CPU (at pin 79) is directly provided by single chip computer AT 89S52 U1.FA0-FA15 is a cpu address bus, and the reading, writing address of storer is provided; FD0-FD15 is a cpu data bus, the data of write store is provided or reads data from storer.REGA0-REGA15 is the register address bus, is directly provided by single chip computer AT 89S52 U1, is used to specify the address of register among the CPU; REGD0-REGD15 is the register data bus, and CPU passes through it to single chip computer AT 89S52 U1 output register data./ CPURD (on U14 pin 10) and/CPUWR (on U14 pin 11) is respectively memory read, the write signal that CPU produces.
Storer K10 is made up of two HM6116 U10 among Fig. 3 (1) and U11 among Fig. 2.HM6116 is the static random read-write device, and each HM6116 capacity is 2048 bytes, and two HM6116 are parallel to have connected and composed the storer of 16 of one 11 bit address, word length.Address RA0-RA11 has constituted memory address bus.Data D0-D15 has constituted memory data bus, and wherein D0-D7 is the memory data bus least-significant byte, and D8-D15 is the storer most-significant byte.Single-chip microcomputer U1 can only carry out the reading and writing operation to a HM6116 at every turn, and CPU U14 carries out the reading and writing operation to two HM6116 simultaneously.Chip selection signal/RAM1 of two HM6116 ,/RAM2, read signal/ROE, write signal/RWR is produced by GAL16V8 U8.
Claims (1)
1, the experimental provision of a kind of Principles of Computer Composition and system architecture, it is characterized in that this experimental provision comprises single-chip microcomputer, central processing unit, storer, the first, second, third and the 4th tri-state bus driver, the bus transceiver of the first and second ternary outputs; Wherein
(1) single-chip microcomputer is used for receiving the operational order of personal computer debugged program, and the result that carries out of loopback operational order, and operational order is used for central processing unit is tested;
(2) central processing unit is designed and is debugged by the device user, and the clock of central processing unit is provided by single-chip microcomputer;
(3) storer is used to store program and operation result thereof that the function to central processing unit that the said apparatus user writes is tested;
(4) first tri-state bus drivers are used to connect or disconnect the register data bus between single-chip microcomputer and the central processing unit and the logic of single-chip data bus and are connected;
(5) second tri-state bus drivers, the CPU memory address bus that is used to be switched on or switched off between central processing unit and the storer is connected with logic between the storage address;
(6) the 3rd tri-state bus drivers are used to be switched on or switched off single-chip microcomputer and are connected with the logic of single-chip data bus with CPU memory address bus between the central processing unit;
(7) the 4th tri-state bus drivers are used to be switched on or switched off single-chip microcomputer and are connected with the logic of single-chip microcomputer address bus with memory address bus between the storer;
The bus transceivers of (8) first ternary outputs are used to be switched on or switched off central processing unit and are connected with the logic of memory data bus with cpu data bus between the storer;
The bus transceivers of (9) second ternary outputs are used to be switched on or switched off single-chip microcomputer and are connected with the logic of memory data bus with single-chip data bus between the storer;
Above-mentioned single-chip microcomputer links to each other with central processing unit by register address bus, cpu clock line, link to each other by the bus transceiver of single-chip data bus with the second ternary output, link to each other by single-chip data bus and first, the 3rd tri-state bus driver, link to each other with the 4th tri-state bus driver by the single-chip microcomputer address bus; Above-mentioned central processing unit links to each other with first tri-state bus driver by the register data bus, link to each other by the bus transceiver of cpu data bus, link to each other with second, third tri-state bus driver respectively by the CPU memory address bus with the first ternary output; Above-mentioned storer links to each other with the bus transceiver of first, second ternary output respectively by memory data bus, links to each other with the second, the 4th tri-state bus driver respectively by memory address bus.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100514391C (en) * | 2005-09-16 | 2009-07-15 | 清华大学科教仪器厂 | Experimental apparatus for computer composition principle and system structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100514391C (en) * | 2005-09-16 | 2009-07-15 | 清华大学科教仪器厂 | Experimental apparatus for computer composition principle and system structure |
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