CN2802729Y

CN2802729Y - Picture element unit storage capacitor of silicon-base liquid rystal display chip

Info

Publication number: CN2802729Y
Application number: CN 200420029969
Authority: CN
Inventors: 代永平; 耿卫东; 刘艳艳; 王颖; 孙钟林
Original assignee: Nankai University
Current assignee: Nankai University
Priority date: 2004-10-19
Filing date: 2004-10-19
Publication date: 2006-08-02
Anticipated expiration: 2014-10-19

Abstract

The utility model relates to a storage capacitor, especially a storage capacitor used in LCOS chip picture element unit of an integrated circuit, which belongs to the micro-electronics application technical field of the subject of information science technology. The storage capacitor is an NMOS type structure, comprising a silicon dioxide insulating layer, a P type silicon substratum layer, an A point, a B point, a single level polysilicon, a first layer polysilicon, a grid oxide layer, an N type inversion layer and a n+ contact area, etc., omitting a layer of polysilicon. Each unit picture element needs to be equipped with a storage capacitor with high density; utilizing the high specific capacitance value of the grid oxide layer and connecting an NMOS source drain electrode to the ground can form the storage capacitor with high density, therefore the LCOS chip can be produced by using the technology of standard single level polysilicon CMOS device, such at least two light-etching mask plates can be spared, and a plurality of steps in the manufacturing process can be reduced, so the storage capacitor is provided with obvious economic benefit for increasing the output of production and reducing the cost.

Description

The pixel cell holding capacitor of silicon base liquid crystal display chip

Technical field

The utility model relates to a kind of holding capacitor, especially for the holding capacitor of LCOS chip pixel unit in the integrated circuit, belongs to the microelectronic applications technical field of information science technology subject.

Background technology

In recent years, LCD is at display quality, all there has been the development of leap large scale and high-res aspect, popular technology is Liquiid crystal on silicon (lcos) display (Liquid Crystal on Silicon, be called for short LCOS, be called CMOS-LCD again), this is a kind of novel reflective miniature LCD Display Technique, it is utilization LVSI technology making driving substrate---LCOS chip on monocrystalline silicon piece at first, plate metal level then and be used as speculum formation CMOS substrate, at last with the CMOS substrate with contain on the transparency electrode glass substrate and fit, pour into liquid crystal again, the liquid crystal cell that is packaged into is a kind of " sandwich structure "---monocrystal silicon substrate sheet and sheet glass " folder " (encapsulation) one deck liquid crystal material that is coated with the ITO nesa coating.Therefore, LCOS is designed to respond fast light valve, by modulating each pixel the reflection of incident light degree is realized that (gray scale) image shows.(Chris Chinnock. " Microdisplays and Manufacturing Infrastructure Mature at SID2000 " " Information Display ", 2000 9, P18).

The circuit structure of LCoS chip can be divided into the line scanning driver, column data drivers and display element matrix (active NMOS matrix).(and along the charging of the orientation of molecule, when a certain amount of electric charge accumulated on the pixel, liquid crystal will be by the electric field orientation that is applied because liquid crystal material itself also has electric capacity.When having changed the voltage that is added in pixel, cause the variation of liquid crystal capacitance, liquid crystal molecule is reorientation then, and this has just realized the display image variation.The electric charge on the liquid crystal capacitance leaks less than 5% (JSPS the 142nd committee volume, Huang Ximin, yellow glow in per frame period in order to keep, the melting of Lee translated " liquid crystal device handbook, aircraft industry publishing house, 1992, P442), need to use the high density storage capacitance.On the other hand, because liquid crystal material needs AC driving, usually public electrode as the reference level, (as: frame period in cycle at a fixed time, line period etc.) in, keep the polarity of voltage be added on each pixel opposite with respect to public electrode voltages polarity, the voltage that the result offers liquid crystal cell on time average near zero, reduce flip-flop as far as possible, can in case liquid crystal aging degenerate.

Summary of the invention

The purpose of this utility model provides a kind of pixel cell holding capacitor of silicon base liquid crystal display chip, and the electric charge leakage that overcomes on the electric capacity is bigger, prevents that accumulate from holding the problem that liquid crystal aging degenerates, and provides a kind of highdensity storage capacitance.

The technical solution of the utility model: the pixel cell holding capacitor of this silicon base liquid crystal display chip, it is the nmos type structure, comprise silicon dioxide insulating layer, P type layer-of-substrate silicon, A point, B point, single level polysilicon, the 1st layer of polysilicon, gate oxide, be characterized in: it also comprises n type inversion layer, n+ contact zone, has saved the 1st layer of polysilicon 12; The silicon dioxide insulating layer 7 of leveling is on P type layer-of-substrate silicon 8, A point 9 and B point 10 that opening is cup-shaped separately are embedded in the silicon dioxide insulating layer, connecting single level polysilicon 11 below the B point, be covered with gate oxide 13 below the single level polysilicon, being n+ contact zone 15 in the P type layer-of-substrate silicon below gate oxide one side, is n type inversion layer 14 below the n+ contact zone.

The beneficial effects of the utility model:

Thereby this invention has the advantage that the minimizing technique process reduces production costs, and adopts this method in the storage capacitance design of LCOS display chip, is reduced by at least two reticle, simplifies manufacture craft, has effectively reduced production cost.This invention is used for Tianjin key research project " LCoS miniscope spare key component and systematic research ", and (bullets: 013184111) the LCOS display chip drives in the design of matrix pixel circuit, make individual layer Si-gate CMOS technology just can realize the production of LCOS display chip, following table is relevant individual layer Si-gate cmos process flow and required lithography mask version, and technology is obviously succinct:

MASKNO. Mask No. mask level number	Engineering name Process engineering name	Reticle is shared
MASKNO. Mask No. mask level number	Engineering name Process engineering name	Reticle is shared	02	Field
01	Nwell		02	Field
01	Nwell		13	Pwell
04	Gate Poly		13	Pwell
04	Gate Poly		26	LDDBF2	With 08 SDBF2 version
09	SDAs		26	LDDBF2	With 08 SDBF2 version
09	SDAs		08	SDBF2
05	Contact		08	SDBF2
05	Contact		19	Contact-P	With 09 SDAs version
06	1Al		19	Contact-P	With 09 SDAs version
06	1Al		37	Via
36	2Al		37	Via
36	2Al		41	Via2
40	3AL		41	Via2

Description of drawings

Fig. 1: double level polysilicon capacitor arrangement

Fig. 2: nmos type capacitor

Wherein:

7, silicon dioxide (SiO ₂) exhausted 13, gate oxide

Edge layer 14, n type inversion layer

8, P type silicon (Si) substrate layer 15, n+ contact zone

9, A point

10, B point

11, the 2nd layer of polysilicon

12, the 1st layer of polysilicon

Embodiment

Below in conjunction with accompanying drawing the utility model is described in further detail:

The pixel cell holding capacitor of this silicon base liquid crystal display chip, it is the nmos type structure, comprise silicon dioxide insulating layer, P type layer-of-substrate silicon, A point, B point, single level polysilicon, the 1st layer of polysilicon, gate oxide, be characterized in: it also comprises n type inversion layer, n+ contact zone, has saved the 1st layer of polysilicon 12; The silicon dioxide insulating layer 7 of leveling is on P type layer-of-substrate silicon 8, A point 9 and B point 10 that opening is cup-shaped separately are embedded in the silicon dioxide insulating layer, connecting single level polysilicon 11 below the B point, be covered with gate oxide 13 below the single level polysilicon, being n+ contact zone 15 in the P type layer-of-substrate silicon below gate oxide one side, is n type inversion layer 14 below the n+ contact zone.

A storage capacitance in parallel with LC driving electrode is arranged on each pixel unit of silicon base liquid crystal display chip, and its effect is to replenish pixel capacitance to prolong the charge storage time.The effect of storage capacitance is the dielectric relaxation time that increases liquid crystal pixel, until being longer than for 1 frame period significantly.Do like this and can obtain two important benefits.At first, obtaining the required addressing voltage that adds of saturated brightness from liquid crystal layer reduces significantly.Secondly, it is constant substantially that brightness kept in whole 1 frame period, and therefore, its mean flow rate is than the height that does not have electric capacity.

In conventional cmos technology, widely used capacitor arrangement as shown in Figure 1, its 11,12 forms two conductive plates, and 7 are the intermediate dielectric with VCD method deposition, non-linear and the precision of this capacitor is all fine, capacitance density is also bigger, but complicated on the LCOS chip technology realizes:

(1) needs to make double level polysilicon;

(2) need independently electric capacity lithography mask version;

(3) need to increase special etching levelling process, comprise increasing lithography mask version and etching technics is eliminated the extra chip surface fluctuating that produces of double level polysilicon etc.

The utility model technology adopts mos capacitance fabrication techniques storage capacitance.A kind of feasible capacitor structure as shown in Figure 2, this electric capacity constitutes by 12,13.N+ contact zone 15 is linked to metal connecting line with n type inversion layer 14, provide electronics by 9 to 14.In addition, 8 and 15 while ground connection have been eliminated the phenomenon that occurs the depletion layer parasitic capacitance between 14 and 8.In each pixel unit of silicon base liquid crystal display chip, because the threshold voltage V of liquid crystal material _TLCThreshold voltage V greater than the MOS device _TMOS, the therefore outer voltage total energy of driving guarantees in the circuit that 10 DC potential is than 9 height.The then capacity of this electric capacity and independent from voltage, directly with 13 dielectric layers of making mos capacitance, capacitance density is consistent with double level polysilicon electric capacity.

In the lower individual layer Si-gate autoregistration MOS technology of production cost, the utility model adopts a kind of feasible storage capacitance device structure of mos capacitance fabrication techniques as shown in Figure 2, and this electric capacity constitutes by 12,13.Adopt self-registered technology, inject with ion and make a n+ contact zone 15,, work as voltage again and reach threshold voltage V both as the ohmic contact of metal connecting line _TMOSWhen the time n type inversion layer 14 occurred, 15 were linked to metal connecting line with 14, provide electronics by 9 to 14.In addition, 8 and 15 while ground connection have been eliminated the phenomenon that occurs the depletion layer parasitic capacitance between 14 and 8.Therefore, if 10 DC potential is always than 9 height in circuit, the then capacity of this electric capacity and independent from voltage, directly with 13 dielectric layers of making mos capacitance, capacitance density is consistent with double level polysilicon electric capacity.And in each pixel unit of silicon base liquid crystal display chip, because the threshold voltage V of liquid crystal material _TLCThreshold voltage V greater than the MOS device _TMOS, the therefore outer voltage total energy of driving guarantees in the circuit that 10 DC potential is than 9 height.

Relevant storage capacitance device structure-design technique main points are:

1. the display chip pixel unit circuit is produced on 8;

2. make reservoir capacitor with N type metal-oxide-semiconductor;

3. 8 and 15 of reservoir capacitor ground connection simultaneously in each pixel cell.

The LCOS display chip is made: technological process is consistent with standard single level polysilicon cmos device technology.

Display chip pixel storage capacitance is made: consistent with the technological requirement of making NMOS in the standard single level polysilicon cmos device technology.Storage capacitance partly is the NMOS pipe of a gate electrode shape irregularity, and its drain contact hole, source combines, and while ground connection.

Later process: consistent with the technological requirement of making silicon-base liquid crystal display device.

Claims

1. the pixel cell holding capacitor of a silicon base liquid crystal display chip, it is the nmos type structure, comprise silicon dioxide insulating layer, P type layer-of-substrate silicon, A point, B point, single level polysilicon, the 1st layer of polysilicon, gate oxide, it is characterized in that: it also comprises n type inversion layer, n+ contact zone, has saved the 1st layer of polysilicon (12); The silicon dioxide insulating layer (7) of leveling is on P type layer-of-substrate silicon (8), A point (9) and B point (10) that opening is cup-shaped separately are embedded in the silicon dioxide insulating layer, connecting single level polysilicon (11) below the B point, be covered with gate oxide (13) below the single level polysilicon, being n+ contact zone (15) in the P type layer-of-substrate silicon below gate oxide one side, is n type inversion layer (14) below the n+ contact zone.