CN2798103Y

CN2798103Y - Network intelligent electric energy quantity monitor

Info

Publication number: CN2798103Y
Application number: CN 200520020920
Authority: CN
Inventors: 佟为明; 刘勇; 李凤阁; 宋雪雷; 赵志衡; 张文义
Original assignee: 佟为明
Priority date: 2005-05-31
Filing date: 2005-05-31
Publication date: 2006-07-19
Anticipated expiration: 2015-05-31

Abstract

The utility model relates to a network intelligent monitor for the quantity of electric energy and relates to the technical field of quantity monitoring for electric energy. The utility model solves the problems of few functions, poor real-time performance, poor ability of intelligent analysis, single network communication interface, big volume and high cost existing in the present monitor for the quantity of electric energy. A three-phase alternating current voltage/current to be measured is input to the detection input end of a voltage/current conversion and sampling circuit 1. The frequency, voltage and current signal output ends of the voltage/current conversion and sampling circuit 1 are respectively connected with two input end of a DSP/MPU central control circuit 2. The output and the input ends of the DSP/MPU central control circuit 2 are connected with the input and the output ends of an RS232 communication interface circuit 4. The output and the input ends of the DSP/MPU central control circuit 2 are connected with the output and the input ends of an RS485 communication interface circuit 5. The bus output and input end of the DSP/MPU central control circuit 2 and the bus input and output end of a Device Net communication interface circuit 6 are connected with the bus input and output end of an Ether Net communication interface circuit 7. Two control bus output ends of the DSP/MPU central control circuit 2 are respectively connected with the control bus input ends of the Device Net communication interface circuit 6 and the Ether Net communication interface circuit 7. The reset output end of the DSP/MPU central control circuit 2 is connected with the input end of a communication interface reset circuit 8. Two reset signal output ends of the communication interface reset circuit 8 are respectively connected with the reset signal input ends of the Device Net communication interface circuit 6 and the Ether Net communication interface circuit 7. The utility.

Description

The network-enabled intelligent equipment for monitoring power quality

Technical field:

The utility model relates to the electric energy quality monitoring technical field, specifically is a kind of network-enabled intelligent equipment for monitoring power quality.

Background technology:

Power quality problem has become the hot issue of power industry extensive concern, has only the quality of power supply is effectively monitored, and real and reliable foundation could be provided for the comprehensive regulation, control and the improvement of the quality of power supply.At present, the equipment for monitoring power quality on the market mainly has the following disadvantages: (1) system real time is poor, and the time frequency analysis means fall behind, and does not possess the ability of real-time monitoring transient power quality disturbance and transient electric-energy quality disturbance; (2) limited to the identification and the classification capacity of disturbance, the lack of wisdom analytic function can not provide the information that can be directly used in decision-making to the user; (3) network communications capability is limited, and network communication interface is single, and the communication mode very flexible be difficult for to realize remote monitoring, data sharing and assesses for a long time and predict; (4) owing to adopt PC mostly, cause installation cost higher as the field monitoring analysis tool; (5) device configuration flexibility, versatility is poor, does not fit into the operation of general environment.

The utility model content:

The purpose of this utility model be have in order to solve existing equipment for monitoring power quality that function is few, real-time is poor, the intellectual analysis ability, network communication interface is single, volume is big, cost is high, the problem of conformability difference, and then provides a kind of network-enabled intelligent equipment for monitoring power quality.It is made up of voltage/current conversion and sample circuit 1, DSP/MPU central control circuit 2, remote signalling/remote control circuit 3, RS232 communication interface circuit 4, RS485 communication interface circuit 5, DeviceNet communication interface circuit 6, EtherNet communication interface circuit 7, communication interface reset circuit 8; Tested three-phase alternating voltage/electric current is input to the detection input end of voltage/current conversion and sample circuit 1, the voltage/current conversion is connected the frequency signal input end of DSP/MPU central control circuit 2 with the frequency signal output terminal of sample circuit 1, the voltage/current conversion is connected the digital signal input end of the expression electric current and voltage of DSP/MPU central control circuit 2 with the digital signal output end of the expression electric current and voltage of sample circuit 1, the voltage/current conversion is connected the analog to digital conversion control signal output ends of DSP/MPU central control circuit 2 with the analog to digital conversion signal input end of sample circuit 1, the remote signalling of DSP/MPU central control circuit 2/remote signal I/O connects the remote signalling/remote signal I/O of remote signalling/remote control circuit 3, the RS232 communication data I/O of DSP/MPU central control circuit 2 connects the data input/output terminal of RS232 communication interface circuit 4, the RS485 communication data I/O of DSP/MPU central control circuit 2 connects the data I/O of RS485 communication interface circuit 5, the data address bus I/O of DSP/MPU central control circuit 2, the data address bus input/output terminal of DeviceNet communication interface circuit 6 connects the data address bus input/output terminal of EtherNet communication interface circuit 7, the first control bus output terminal of DSP/MPU central control circuit 2 connects the control bus input end of DeviceNet communication interface circuit 6, the second control bus output terminal of DSP/MPU central control circuit 2 connects the control bus input end of EtherNet communication interface circuit 7, the reseting data output terminal of DSP/MPU central control circuit 2 connects the input end of communication interface reset circuit 8, the first reset signal output terminal of communication interface reset circuit 8 connects the reset signal input end of DeviceNet communication interface circuit 6, and the second reset signal output terminal of communication interface reset circuit 8 connects the reset signal input end of EtherNet communication interface circuit 7.Principle of work: the voltage/current conversion becomes digital signal to the analog signal conversion of the voltage of tested three-phase alternating voltage/electric current, electric current, frequency with sample circuit 1, after 2 pairs of above-mentioned digital signal datas of DSP/MPU central control circuit carry out comprehensive computing, analysis and processing, obtain the electric energy quality monitoring data, and be real-time transmitted to outside Centralized Monitoring center by RS232 communication interface circuit 4 or RS485 communication interface circuit 5 or DeviceNet communication interface circuit 6 or EtherNet communication interface circuit 7; Communication interface reset circuit 8 will detect in real time to the duty of DeviceNet communication interface circuit 6, EtherNet communication interface circuit 7 simultaneously, when abnormality such as DeviceNet communication interface circuit 6 or the 7 appearance deadlocks of EtherNet communication interface circuit, communication interface reset circuit 8 will send reset enable signal DeviceNet communication interface circuit 6 or EtherNet communication interface circuit 7 restarts, and reenter in the normal operating conditions (also can hand-reset).Having adopted High Performance DSP processor and embedded MPU processor in the central control circuit in the utility model is core, makes the advantage that the utlity model has multi-functional, high real-time, high precision, high-intelligentization, multi-network interface; Simultaneously can introduce embedded real-time operating system, and simplify the development of embedded application process,, be convenient to system maintenance and secondary development to improve the reliability and stability of system as Software Development Platform.

Description of drawings:

Fig. 1 is an integrated circuit structural representation of the present utility model, and Fig. 2 is the electrical block diagram of DeviceNet communication interface circuit 6, and Fig. 3 is the electrical block diagram of communication interface reset circuit 8.

Embodiment:

Embodiment one: in conjunction with Fig. 1 present embodiment is described, it is made up of voltage/current conversion and sample circuit 1, DSP/MPU central control circuit 2, remote signalling/remote control circuit 3, RS232 communication interface circuit 4, RS485 communication interface circuit 5, DeviceNet communication interface circuit 6, EtherNet communication interface circuit 7, communication interface reset circuit 8; Tested three-phase alternating voltage/electric current is input to the detection input end of voltage/current conversion and sample circuit 1, the voltage/current conversion is connected the frequency signal input end of DSP/MPU central control circuit 2 with the frequency signal output terminal of sample circuit 1, the voltage/current conversion is connected the digital signal input end of the expression electric current and voltage of DSP/MPU central control circuit 2 with the digital signal output end of the expression electric current and voltage of sample circuit 1, the voltage/current conversion is connected the analog to digital conversion control signal output ends of DSP/MPU central control circuit 2 with the analog to digital conversion signal input end of sample circuit 1, the remote signalling of DSP/MPU central control circuit 2/remote signal I/O connects the remote signalling/remote signal I/O of remote signalling/remote control circuit 3, the RS232 communication data I/O of DSP/MPU central control circuit 2 connects the data input/output terminal of RS232 communication interface circuit 4, the RS485 communication data I/O of DSP/MPU central control circuit 2 connects the data I/O of RS485 communication interface circuit 5, the data address bus I/O of DSP/MPU central control circuit 2, the data address bus input/output terminal of DeviceNet communication interface circuit 6 connects the data address bus input/output terminal of EtherNet communication interface circuit 7, the first control bus output terminal of DSP/MPU central control circuit 2 connects the control bus input end of DeviceNet communication interface circuit 6, the second control bus output terminal of DSP/MPU central control circuit 2 connects the control bus input end of EtherNet communication interface circuit 7, the reseting data output terminal of DSP/MPU central control circuit 2 connects the input end of communication interface reset circuit 8, the first reset signal output terminal of communication interface reset circuit 8 connects the reset signal input end of DeviceNet communication interface circuit 6, and the second reset signal output terminal of communication interface reset circuit 8 connects the reset signal input end of EtherNet communication interface circuit 7.3 effects of remote signalling/remote control circuit are to receive external switch amount signal and send control, warning or trip signal to the outside; The chip model that RS232 communication interface circuit 4 is selected for use is MAX3232; The chip model that RS485 communication interface circuit 5 is selected for use is MAX3485, and its communication protocol can be selected Modbus communication protocol for use; The chip model that EtherNet communication interface circuit 7 is selected for use is RTL8019AS.

Embodiment two: in conjunction with Fig. 1 present embodiment is described, voltage/current conversion described in the embodiment one and sample circuit 1 are made up of voltage/current transformer circuit 1-1, amplifying circuit 1-2, level adjusting circuit 1-3, A/D change-over circuit 1-4, zero cross detection circuit 1-5, frequency multiplication of phase locked loop circuit 1-6; Tested three-phase alternating voltage/electric current is input to the detection input end of voltage/current transformer circuit 1-1, the zero cross signal output terminal of voltage/current transformer circuit 1-1 connects the signal input part of zero cross detection circuit 1-5, the signal output part of zero cross detection circuit 1-5 connects the signal input part of frequency multiplication of phase locked loop circuit 1-6, the synchronous signal output end of frequency multiplication of phase locked loop circuit 1-6 connects the synchronous signal input end of A/D change-over circuit 1-4, the current signal output end of voltage/current transformer circuit 1-1 connects the input end of amplifying circuit 1-2, the output terminal of amplifying circuit 1-2 connects the current signal input end of level adjusting circuit 1-3, the voltage signal output end of voltage/current transformer circuit 1-1 connects the voltage signal input end of level adjusting circuit 1-3, and the output terminal of level adjusting circuit 1-3 connects the input end of analog signal of A/D change-over circuit 1-4.That voltage/current transformer circuit 1-1 selects for use is 100V/1.768V and 5A/1.768V, the chip model that amplifying circuit 1-2 selects for use is LM6144, the chip model that level adjusting circuit 1-3 selects for use is LM6144, the chip model that A/D change-over circuit 1-4 selects for use is ADS8364, the chip model that zero cross detection circuit 1-5 selects for use is LM6144, and the chip model that frequency multiplication of phase locked loop circuit 1-6 selects for use is MM74HC4046.DSP/MPU central control circuit 2 is made up of dsp processor 2-1, dual port RAM circuit 2-2, MPU processor 2-3, first memory 2-4, second memory 2-5, EPLD logical device 2-6, liquid crystal display circuit 2-7, keyboard circuit 2-8; The signal output part of frequency multiplication of phase locked loop circuit 1-6 connects the frequency detecting input end of dsp processor 2-1, the data-signal output terminal of A/D change-over circuit 1-4 connects the electric current and voltage data-signal input end of dsp processor 2-1, the analog to digital conversion control data input end of A/D change-over circuit 1-4 connects the analog to digital conversion control data output terminal of EPLD logical device 2-6, the remote signalling of dsp processor 2-1/remote signal I/O connects the remote signalling/remote signal I/O of remote signalling/remote control circuit 3, the first data address bus I/O of dsp processor 2-1 connects the data address bus I/O of first memory 2-4, the second data address bus I/O of dsp processor 2-1 connects the first data address bus I/O of dual port RAM circuit 2-2, the second data address bus I/O of dual port RAM circuit 2-2 connects the first data address bus I/O of MPU processor 2-3, the second data address bus I/O of MPU processor 2-3 connects the data address bus I/O of second memory 2-5, the control address output end of main of dsp processor 2-1 connects the first control address bus input end of EPLD logical device 2-6, the control address output end of main of MPU processor 2-3 connects the second control address bus input end of EPLD logical device 2-6, the first control bus output terminal of EPLD logical device 2-6 connects the control bus input end of first memory 2-4, the second control bus output terminal of EPLD logical device 2-6 connects the control bus input end of second memory 2-5, the 3rd control bus output terminal of EPLD logical device 2-6 connects the control bus input end of dual port RAM circuit 2-2, the 5th control bus output terminal of EPLD logical device 2-6 connects the control bus input end of EtherNet communication interface circuit 7, the video data output terminal of MPU processor 2-3 connects the input end of liquid crystal display circuit 2-7, the Keyboard Control input end of MPU processor 2-3 connects the output terminal of keyboard circuit 2-8, the RS232 communication data I/O of MPU processor 2-3 connects the data input/output terminal of RS232 communication interface circuit 4, the RS485 communication data I/O of MPU processor 2-3 connects the data I/O of RS485 communication interface circuit 5, and the 4th data address bus I/O of MPU processor 2-3 connects the data address bus input/output terminal of EtherNet communication interface circuit 7.The chip model that dsp processor 2-1 selects for use is TMS320F2812, the chip model that dual port RAM circuit 2-2 selects for use is IDT70V9289L, the chip model that MPU processor 2-3 selects for use is S3C44B0X, the chip model that first memory 2-4 selects for use is IS61LV6416L and AT28BV256, the chip model that second memory 2-5 selects for use is HY57V641620 and HY29LV160, the chip model that EPLD logical device 2-6 selects for use is EPM7128, and the model that liquid crystal display circuit 2-7 selects for use is LCBA7Z211M2.

Embodiment three: in conjunction with Fig. 2 present embodiment is described, DeviceNet communication interface circuit 6 described in the embodiment one is made up of level transferring chip U1, DeviceNet control chip U2, the first optocoupler U3, the second optocoupler U4, CAN transceiver U5, crystal oscillator T, socket RJ, first resistance R 1, second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, first capacitor C 1, second capacitor C 2; The pin 30 of level transferring chip U1, pin 32, pin 33, pin 35 ends connect the pin 62 of EPLD logical device 2-6 respectively, pin 63, pin 65, pin 67 ends, the pin 37 of level transferring chip U1, pin 38, pin 40, pin 41, pin 43, pin 44, pin 46, pin 47 ends connect the pin 130 of MPU processor 2-3 respectively, pin 131, pin 132, pin 133, pin 134, pin 135, pin 136, pin 137 ends, the pin 2 of level transferring chip U1, pin 3, pin 5, pin 6, pin 8, pin 9, pin 11, pin 12 ends connect the pin 23 of DeviceNet control chip U2 respectively, pin 24, pin 25, pin 26, pin 27, pin 28, pin 1, pin 2 ends, the pin 14 of level transferring chip U1, pin 16, pin 17, pin 19 ends connect the pin 4 of DeviceNet control chip U2 respectively, pin 3, pin 5, pin 6 ends, the pin 25 of level transferring chip U1, pin 48, pin 28, pin 34, pin 39, pin 45, pin 21, pin 15, pin 10, pin 4 ends are ground connection all, the pin 31 of level transferring chip U1, pin 42, pin 18, pin 7, pin 24 ends all connect power supply+VCC end, the pin 8 of DeviceNet control chip U2, pin 21, pin 15, pin 11 ends are ground connection all, the pin 12 of DeviceNet control chip U2, pin 18, pin 22 ends all connect power supply+vdd terminal, pin 9 ends of DeviceNet control chip U2, the end of crystal oscillator T connects an end of second capacitor C 2, the other end of second capacitor C 2 connects an end and the ground connection of first capacitor C 1, the other end of first capacitor C 1, the other end of crystal oscillator T connects pin 10 ends of DeviceNet control chip U2, pin 13 ends of DeviceNet control chip U2 connect an end of first resistance R 1, the other end of first resistance R 1 connects pin 3 ends of the first optocoupler U3, pin 2 termination powers+vdd terminal of the first optocoupler U3, pin 8 ends of the first optocoupler U3, one end of the 5th resistance R 5 connects an end of the 6th resistance R 6 and connects power supply+VDD1 end, the other end of the 5th resistance R 5 connects pin 7 ends of the first optocoupler U3, the other end of the 6th resistance R 6 connects pin 6 ends of the first optocoupler U3 and connects pin 1 end of CAN transceiver U5, pin 19 ends of DeviceNet control chip U2, one end of second resistance R 2 connects pin 6 ends of the second optocoupler U4, pin 7 ends of the second optocoupler U4 connect an end of the 3rd resistance R 3, pin 8 ends of the second optocoupler U4, the other end of second resistance R 2 connects the other end of the 3rd resistance R 3 and connects power supply+vdd terminal, the pin 5 end ground connection of the second optocoupler U4, pin 2 termination powers of the second optocoupler U4+VDD1 end, pin 3 ends of the second optocoupler U4 connect an end of the 4th resistance R 4, the other end of the 4th resistance R 4 connects pin 4 ends of CAN transceiver U5, pin 3 termination powers of CAN transceiver U5+VDD1 end, the pin 2 end ground connection of CAN transceiver U5, pin 8 ends of CAN transceiver U5 connect an end of the 7th resistance R 7, the other end ground connection of the 7th resistance R 7, the pin 6 of CAN transceiver U5, pin 7 ends connect the pin 2 of socket RJ respectively, pin 4 ends.The model that level transferring chip U1 selects for use is SN74LVTH16245A, and the model that DeviceNet control chip U2 selects for use is SJA1000.

Embodiment four: in conjunction with Fig. 3 present embodiment is described, communication interface reset circuit 8 described in the embodiment one is made up of level transferring chip U6, the 3rd optocoupler U7, the 4th optocoupler U8, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R the 10, the 11 resistance R the 11, the 12 resistance R 12, the 3rd capacitor C 3, the 4th capacitor C 4, the first pushbutton switch SWP1, the second pushbutton switch SWP2; Pin 47 ends of level transferring chip U6 connect pin 13 ends of the MPU processor 2-3 in the DSP/MPU central control circuit 2, the pin 24 of level transferring chip U6, pin 25, pin 48, pin 4, pin 10, pin 15, pin 21, pin 28, pin 34, pin 39, pin 45 ends are ground connection all, the pin 1 of level transferring chip U6, pin 7, pin 18, pin 31, pin 42 ends all connect power supply+VCC end, pin 2 ends of level transferring chip U6, pin 2 ends of the 3rd optocoupler U7 connect pin 2 ends of the 4th optocoupler U8, pin 1 end of the 3rd optocoupler U7 connects an end of the 9th resistance R 9, the other end of the 9th resistance R 9 connects power supply+VCC end, pin 3 ends of the 3rd optocoupler U7, one end of the 3rd capacitor C 3 connects an end and the ground connection of the first pushbutton switch SWP1, pin 4 ends of the 3rd optocoupler U7, one end of the tenth resistance R 10, the other end of the 3rd capacitor C 3 connects the other end of the first pushbutton switch SWP1 and connects pin 17 ends of DeviceNet control chip U2, another termination power+vdd terminal of the tenth resistance R 10, pin 1 end of the 4th optocoupler U8 connects an end of the 8th resistance R 8, the other end of the 8th resistance R 8 connects power supply+VCC end, pin 3 ends of the 4th optocoupler U8, one end of the 12 resistance R 12, one end of the 4th capacitor C 4 connects an end of the 11 resistance R 11 and connects the reset signal input end of EtherNet communication interface circuit 7, the other end ground connection of the 12 resistance R 12, pin 4 ends of the 4th optocoupler U8, the other end of the 4th capacitor C 4 connects the end of the second pushbutton switch SWP2 and connects power supply+vdd terminal, and the other end of the second pushbutton switch SWP2 connects the other end of the 11 resistance R 11.The model that level transferring chip U6 selects for use is SN74LVTH16245A.

Claims

1, network-enabled intelligent equipment for monitoring power quality is characterized in that it is made up of voltage/current conversion and sample circuit (1), DSP/MPU central control circuit (2), remote signalling/remote control circuit (3), RS232 communication interface circuit (4), RS485 communication interface circuit (5), DeviceNet communication interface circuit (6), EtherNet communication interface circuit (7), communication interface reset circuit (8); Tested three-phase alternating voltage/electric current is input to the detection input end of voltage/current conversion and sample circuit (1), the voltage/current conversion is connected the frequency signal input end of DSP/MPU central control circuit (2) with the frequency signal output terminal of sample circuit (1), the voltage/current conversion is connected the digital signal input end of the expression electric current and voltage of DSP/MPU central control circuit (2) with the digital signal output end of the expression electric current and voltage of sample circuit (1), the voltage/current conversion is connected the analog to digital conversion control signal output ends of DSP/MPU central control circuit (2) with the analog to digital conversion signal input end of sample circuit (1), the remote signalling of DSP/MPU central control circuit (2)/remote signal I/O connects the remote signalling/remote signal I/O of remote signalling/remote control circuit (3), the RS232 communication data I/O of DSP/MPU central control circuit (2) connects the data input/output terminal of RS232 communication interface circuit (4), the RS485 communication data I/O of DSP/MPU central control circuit (2) connects the data I/O of RS485 communication interface circuit (5), the data address bus I/O of DSP/MPU central control circuit (2), the data address bus input/output terminal of DeviceNet communication interface circuit (6) connects the data address bus input/output terminal of EtherNet communication interface circuit (7), the first control bus output terminal of DSP/MPU central control circuit (2) connects the control bus input end of DeviceNet communication interface circuit (6), the second control bus output terminal of DSP/MPU central control circuit (2) connects the control bus input end of EtherNet communication interface circuit (7), the reseting data output terminal of DSP/MPU central control circuit (2) connects the input end of communication interface reset circuit (8), the first reset signal output terminal of communication interface reset circuit (8) connects the reset signal input end of DeviceNet communication interface circuit (6), and the second reset signal output terminal of communication interface reset circuit (8) connects the reset signal input end of EtherNet communication interface circuit (7).

2, network-enabled intelligent equipment for monitoring power quality according to claim 1 is characterized in that voltage/current conversion and sample circuit (1) be made up of voltage/current transformer circuit (1-1), amplifying circuit (1-2), level adjusting circuit (1-3), A/D change-over circuit (1-4), zero cross detection circuit (1-5), frequency multiplication of phase locked loop circuit (1-6); Tested three-phase alternating voltage/electric current is input to the detection input end of voltage/current transformer circuit (1-1), the zero cross signal output terminal of voltage/current transformer circuit (1-1) connects the signal input part of zero cross detection circuit (1-5), the signal output part of zero cross detection circuit (1-5) connects the signal input part of frequency multiplication of phase locked loop circuit (1-6), the synchronous signal output end of frequency multiplication of phase locked loop circuit (1-6) connects the synchronous signal input end of A/D change-over circuit (1-4), the current signal output end of voltage/current transformer circuit (1-1) connects the input end of amplifying circuit (1-2), the output terminal of amplifying circuit (1-2) connects the current signal input end of level adjusting circuit (1-3), the voltage signal output end of voltage/current transformer circuit (1-1) connects the voltage signal input end of level adjusting circuit (1-3), and the output terminal of level adjusting circuit (1-3) connects the input end of analog signal of A/D change-over circuit (1-4).

3, network-enabled intelligent equipment for monitoring power quality according to claim 1 is characterized in that DSP/MPU central control circuit (2) is made up of dsp processor (2-1), dual port RAM circuit (2-2), MPU processor (2-3), first memory (2-4), second memory (2-5), EPLD logical device (2-6), liquid crystal display circuit (2-7), keyboard circuit (2-8); The signal output part of frequency multiplication of phase locked loop circuit (1-6) connects the frequency detecting input end of dsp processor (2-1), the data-signal output terminal of A/D change-over circuit (1-4) connects the electric current and voltage data-signal input end of dsp processor (2-1), the analog to digital conversion control data input end of A/D change-over circuit (1-4) connects the analog to digital conversion control data output terminal of EPLD logical device (2-6), the remote signalling of dsp processor (2-1)/remote signal I/O connects the remote signalling/remote signal I/O of remote signalling/remote control circuit (3), the first data address bus I/O of dsp processor (2-1) connects the data address bus I/O of first memory (2-4), the second data address bus I/O of dsp processor (2-1) connects the first data address bus I/O of dual port RAM circuit (2-2), the second data address bus I/O of dual port RAM circuit (2-2) connects the first data address bus I/O of MPU processor (2-3), the second data address bus I/O of MPU processor (2-3) connects the data address bus I/O of second memory (2-5), the control address output end of main of dsp processor (2-1) connects the first control address bus input end of EPLD logical device (2-6), the control address output end of main of MPU processor (2-3) connects the second control address bus input end of EPLD logical device (2-6), the first control bus output terminal of EPLD logical device (2-6) connects the control bus input end of first memory (2-4), the second control bus output terminal of EPLD logical device (2-6) connects the control bus input end of second memory (2-5), the 3rd control bus output terminal of EPLD logical device (2-6) connects the control bus input end of dual port RAM circuit (2-2), the 5th control bus output terminal of EPLD logical device (2-6) connects the control bus input end of EtherNet communication interface circuit (7), the video data output terminal of MPU processor (2-3) connects the input end of liquid crystal display circuit (2-7), the Keyboard Control input end of MPU processor (2-3) connects the output terminal of keyboard circuit (2-8), the RS232 communication data I/O of MPU processor (2-3) connects the data input/output terminal of RS232 communication interface circuit (4), the RS485 communication data I/O of MPU processor (2-3) connects the data I/O of RS485 communication interface circuit (5), and the 4th data address bus I/O of MPU processor (2-3) connects the data address bus input/output terminal of EtherNet communication interface circuit (7).

4, network-enabled intelligent equipment for monitoring power quality according to claim 1 is characterized in that DeviceNet communication interface circuit (6) is made up of level transferring chip (U1), DeviceNet control chip (U2), first optocoupler (U3), second optocoupler (U4), CAN transceiver (U5), crystal oscillator (T), socket (RJ), first resistance (R1), second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 7th resistance (R7), first electric capacity (C1), second electric capacity (C2); The pin 30 of level transferring chip (U1), pin 32, pin 33, pin 35 ends connect the pin 62 of EPLD logical device (2-6) respectively, pin 63, pin 65, pin 67 ends, the pin 37 of level transferring chip (U1), pin 38, pin 40, pin 41, pin 43, pin 44, pin 46, pin 47 ends connect the pin 130 of MPU processor (2-3) respectively, pin 131, pin 132, pin 133, pin 134, pin 135, pin 136, pin 137 ends, the pin 2 of level transferring chip (U1), pin 3, pin 5, pin 6, pin 8, pin 9, pin 11, pin 12 ends connect the pin 23 of DeviceNet control chip (U2) respectively, pin 24, pin 25, pin 26, pin 27, pin 28, pin 1, pin 2 ends, the pin 14 of level transferring chip (U1), pin 16, pin 17, pin 19 ends connect the pin 4 of DeviceNet control chip (U2) respectively, pin 3, pin 5, pin 6 ends, the pin 25 of level transferring chip (U1), pin 48, pin 28, pin 34, pin 39, pin 45, pin 21, pin 15, pin 10, pin 4 ends are ground connection all, the pin 31 of level transferring chip (U1), pin 42, pin 18, pin 7, pin 24 ends all connect power supply (+VCC) end, the pin 8 of DeviceNet control chip (U2), pin 21, pin 15, pin 11 ends are ground connection all, the pin 12 of DeviceNet control chip (U2), pin 18, pin 22 ends all connect power supply (+VDD) end, pin 9 ends of DeviceNet control chip (U2), one end of crystal oscillator (T) connects an end of second electric capacity (C2), the other end of second electric capacity (C2) connects an end and the ground connection of first electric capacity (C1), the other end of first electric capacity (C1), the other end of crystal oscillator (T) connects pin 10 ends of DeviceNet control chip (U2), pin 13 ends of DeviceNet control chip (U2) connect an end of first resistance (R1), the other end of first resistance (R1) connects pin 3 ends of first optocoupler (U3), pin 2 termination powers of first optocoupler (U3) (+VDD) hold, pin 8 ends of first optocoupler (U3), one end of the 5th resistance (R5) connect an end of the 6th resistance (R6) and connect power supply (+VDD1) end, the other end of the 5th resistance (R5) connects pin 7 ends of first optocoupler (U3), the other end of the 6th resistance (R6) connects pin 6 ends of first optocoupler (U3) and connects pin 1 end of CAN transceiver (U5), pin 19 ends of DeviceNet control chip (U2), one end of second resistance (R2) connects pin 6 ends of second optocoupler (U4), pin 7 ends of second optocoupler (U4) connect an end of the 3rd resistance (R3), pin 8 ends of second optocoupler (U4), the other end of second resistance (R2) connect the other end of the 3rd resistance (R3) and connect power supply (+VDD) end, the pin 5 end ground connection of second optocoupler (U4), pin 2 termination powers of second optocoupler (U4) (+VDD1) hold, pin 3 ends of second optocoupler (U4) connect an end of the 4th resistance (R4), the other end of the 4th resistance (R4) connects pin 4 ends of CAN transceiver (U5), pin 3 termination powers of CAN transceiver (U5) (+VDD1) hold, the pin 2 end ground connection of CAN transceiver (U5), pin 8 ends of CAN transceiver (U5) connect an end of the 7th resistance (R7), the other end ground connection of the 7th resistance (R7), the pin 6 of CAN transceiver (U5), pin 7 ends connect the pin 2 of socket (RJ) respectively, pin 4 ends.

5, network-enabled intelligent equipment for monitoring power quality according to claim 1 is characterized in that communication interface reset circuit (8) is made up of level transferring chip (U6), the 3rd optocoupler (U7), the 4th optocoupler (U8), the 8th resistance (R8), the 9th resistance (R9), the tenth resistance (R10), the 11 resistance (R11), the 12 resistance (R12), the 3rd electric capacity (C3), the 4th electric capacity (C4), first pushbutton switch (SWP1), second pushbutton switch (SWP2); Pin 47 ends of level transferring chip (U6) connect pin 13 ends of the MPU processor (2-3) in the DSP/MPU central control circuit (2), the pin 24 of level transferring chip (U6), pin 25, pin 48, pin 4, pin 10, pin 15, pin 21, pin 28, pin 34, pin 39, pin 45 ends are ground connection all, the pin 1 of level transferring chip (U6), pin 7, pin 18, pin 31, pin 42 ends all connect power supply (+VCC) end, pin 2 ends of level transferring chip (U6), pin 2 ends of the 3rd optocoupler (U7) connect pin 2 ends of the 4th optocoupler (U8), pin 1 end of the 3rd optocoupler (U7) connects an end of the 9th resistance (R9), the other end connection power supply of the 9th resistance (R9) (+VCC) hold, pin 3 ends of the 3rd optocoupler (U7), one end of the 3rd electric capacity (C3) connects an end and the ground connection of first pushbutton switch (SWP1), pin 4 ends of the 3rd optocoupler (U7), one end of the tenth resistance (R10), the other end of the 3rd electric capacity (C3) connects the other end of first pushbutton switch (SWP1) and connects pin 17 ends of DeviceNet control chip (U2), another termination power of the tenth resistance (R10) (+VDD) hold, pin 1 end of the 4th optocoupler (U8) connects an end of the 8th resistance (R8), the other end connection power supply of the 8th resistance (R8) (+VCC) hold, pin 3 ends of the 4th optocoupler (U8), one end of the 12 resistance (R12), one end of the 4th electric capacity (C4) connects an end of the 11 resistance (R11) and connects the reset signal input end of EtherNet communication interface circuit (7), the other end ground connection of the 12 resistance (R12), pin 4 ends of the 4th optocoupler (U8), the other end of the 4th electric capacity (C4) connect an end of second pushbutton switch (SWP2) and connect power supply (+VDD) end, the other end of second pushbutton switch (SWP2) connects the other end of the 11 resistance (R11).