CN2775973Y

CN2775973Y - Frame buffer structure for Mpeg-4 microblock

Info

Publication number: CN2775973Y
Application number: CNU2004201222631U
Authority: CN
Inventors: 白锋
Original assignee: Vimicro Corp
Current assignee: Vimicro Corp
Priority date: 2004-12-31
Filing date: 2004-12-31
Publication date: 2006-04-26
Anticipated expiration: 2014-12-31

Abstract

The utility model discloses a frame buffer structure for Mpeg-4 macro blocks. The utility model comprises a frame buffer controller and two groups of SRAMs, wherein one group of an SRAM is used for storing reference frames of Mpeg-4 coding and decoding requirements, the other group of an SRAM is used for storing current frames of Mpeg-4 coding and decoding requirements, and the two groups of SRAMs which are arranged in parallel carry out data exchange with the frame buffer controller respectively. Compared with the prior art, the utility model realizes accessing the current frames and the reference frames simultaneously and reduces accessing time, and consequently, the speed of coding and decoding video data is increased.

Description

A kind of frame buffer structure at the Mpeg-4 macro block

Technical field

The utility model relates to the frame buffer structure that adopts in a kind of video data processing, particularly a kind of frame buffer structure at the Mpeg-4 macro block.

Technical background

Frame buffer structure in the existing Mpeg-4 macro block is to use the physical support of SRAM (static random-access memory) as frame (image), deposit the view data that a frame or multiframe are handled or shown, because existing frame buffer structure has only been used one or one group of static random-access memory SRAM, promptly any one has only one constantly to the visit of SRAM, if therefore in the Mpeg-4 encoding and decoding, present frame and reference frame are handled simultaneously, existing structure must wait for that a visit finishes the visit of reprocessing another one, be that these 2 visits must be by serial process, and since during the mpeg-4 encoding and decoding standard-required simultaneously present frame and reference frame are read and write, this just shows that existing frame buffer structure will cause the longer access time, reduce the efficient of Mpeg4 encoding and decoding.

The utility model content

The purpose of this utility model is: at the deficiencies in the prior art, provide a kind of simple in structure, can read and write present frame and reference frame simultaneously, meet the Mpeg-4 standard, the frame buffer structure that access efficiency is high at the Mpeg-4 macro block.

In order to solve the problems of the technologies described above, technical solution adopted in the utility model is: a kind of frame buffer structure at the Mpeg-4 macro block, comprise frame buffer controller, also comprise two groups of SRAM, wherein one group of SRAM is used for storing the reference frame of mpeg-4 encoding and decoding requirement, another group SRAM is used for storing the present frame of mpeg-4 encoding and decoding requirement, and described two groups of SRAM are parallel to be provided with, and carries out data interaction with frame buffer controller respectively.

Described two groups of SRAM can be respectively carry out data interaction by reading the enable data line, write the enable data line separately, chip select line, ready line, write data line, read data line and frame buffer controller.

In technique scheme, the utility model adopts the SRAM of two concurrent designing, be used for storage of reference frames and present frame respectively, thereby can be according to the Mpeg-4 standard, realization is visited simultaneously to present frame and reference frame, reduce the access time greatly, raise the efficiency, thereby accelerated the speed of encoding and decoding in the image processing.

Description of drawings

Accompanying drawing 1 is the frame buffer structure of Mpeg-4 macro block in the prior art;

Accompanying drawing 2 is the frame buffer structure of Mpeg-4 macro block of the present utility model.

Embodiment

Below in conjunction with Figure of description and specific embodiment the utility model is described in further detail.

With reference to the accompanying drawings 2, a kind of frame buffer structure at the Mpeg-4 macro block, comprise frame buffer controller, also comprise two groups of SRAM, wherein SRAM1 is used for storing the reference frame of mpeg-4 encoding and decoding requirement, SRAM2 is used for storing the present frame of mpeg-4 encoding and decoding requirement, and described two groups of SRAM are parallel to be provided with, and carries out data interaction with frame buffer controller respectively.

Described two groups of SRAM carry out data interaction by reading the enable data line, write the enable data line separately, chip select line, ready line, write data line, read data line and frame buffer controller respectively.

When work, frame buffer controller can be visited two groups of SRAM simultaneously, thereby realizes the requirement of Mpeg-4 standard, has access to reference frame and present frame simultaneously, thereby quickens the speed of mpeg-4 encoding and decoding.

Claims

1, a kind of frame buffer structure at the Mpeg-4 macro block, comprise frame buffer controller, it is characterized in that: also comprise two groups of SRAM, wherein one group of SRAM is used for storing the reference frame of mpeg-4 encoding and decoding requirement, another group SRAM is used for storing the present frame of mpeg-4 encoding and decoding requirement, described two groups of SRAM are parallel to be provided with, and carries out data interaction with frame buffer controller respectively.

2, according to claim 1 at the frame buffer structure of Mpeg-4 macro block, it is characterized in that: described two groups of SRAM carry out data interaction by reading the enable data line, write the enable data line separately, chip select line, ready line, write data line, read data line and frame buffer controller respectively.