CN2763043Y - Pneumatic marking device - Google Patents

Pneumatic marking device Download PDF

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Publication number
CN2763043Y
CN2763043Y CN 200420057742 CN200420057742U CN2763043Y CN 2763043 Y CN2763043 Y CN 2763043Y CN 200420057742 CN200420057742 CN 200420057742 CN 200420057742 U CN200420057742 U CN 200420057742U CN 2763043 Y CN2763043 Y CN 2763043Y
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CN
China
Prior art keywords
microprocessor
pneumatic
input
control
pin
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Expired - Fee Related
Application number
CN 200420057742
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Chinese (zh)
Inventor
张爱萍
王曙文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WUHAN JIAMING LASER CO Ltd
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WUHAN JIAMING LASER CO Ltd
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Priority to CN 200420057742 priority Critical patent/CN2763043Y/en
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Abstract

The utility model relates to a pneumatic marking machine, particularly an integral digital control pneumatic marking machine, which is characterized in that the machine comprises a digital control system which uses a microprocessor as a kernel control chip, wherein the periphery of the microprocessor is provided with a real time clock, a memory, an input/output interface and a display in an extended way, and a marking control signal generated by the microprocessor is input into a motor and an air valve of the pneumatic marking machine head. The pneumatic marking machine of digital control marking integration provides various kinds of peripheral extended equipment, simplifies the hardware formation of the automation control of the pneumatic marking machine and has the advantages of small size and low cost.

Description

Pneumatic marker
Technical field
The utility model relates to a kind of pneumatic marker, especially integrated digital controlled pneumatic marker.
Background technology
In the prior art, need the additional configuration microsystem to finish to the automation of pneumatic marker control, promptly motor and the air valve by computer control pneumatic marker head carries out mark.Computer must have standardized central processing unit (CPU), memory and I/O (I/O) framework, the hardware cost height, and can not expand ancillary equipment neatly.The overall volume of pneumatic marker and microsystem also is unfavorable for motor-driven operation.Along with the progress of pneumatic labelling technique, pneumatic marker head volume reduces greatly in recent years, provides the incorporate pneumatic marker of numerical control mark to become current labelling technique field problem anxious to be solved.
The utility model content
The purpose of this utility model is at the problems referred to above, provides a kind of numerical control mark incorporate pneumatic marker.For achieving the above object, the technical scheme that the utility model provides is: a kind of pneumatic marker, have pneumatic marker head and support, comprise with the microprocessor being the digital control system of kernel control chip, the peripheral expansion of microprocessor is provided with real-time clock, memory, interface, display, and the marking of control signal that microprocessor produces is by the motor and the air valve of CPLD input pneumatic marker head.
The utility model is that core designs with the microprocessor, and multiple peripheral expansion equipment is provided, and the hardware of having simplified the automation control of pneumatic marker constitutes, thereby has reduced cost, has reduced equipment volume.And aspect software, compare with the desktop operating system that computer is huge, complicated, higher with the corresponding embedded OS reliability of the utility model hardware simplicity.The invention " the marking of control method of pneumatic marker " that use of the present utility model can be applied on the same day referring to the inventor.
Description of drawings
Fig. 1 is a schematic block circuit diagram of the present utility model;
Fig. 2 is a single chip part circuit diagram of the present utility model;
Fig. 3 is clock chip partial circuit figure of the present utility model;
Fig. 4 is RAM partial circuit figure of the present utility model;
Fig. 5 is a FLASH memory portion circuit diagram of the present utility model;
Fig. 6 is a CF of the present utility model interface section circuit diagram;
Fig. 7 is a usb segment circuit diagram of the present utility model.
The specific embodiment
Below in conjunction with drawings and Examples the utility model is further described.Referring to Fig. 1, the utility model comprises with the microprocessor being the digital control system of kernel control chip, the peripheral expansion of microprocessor is provided with real-time clock, memory, input and output (I/O) interface, display, and the marking of control signal that microprocessor produces is by the motor and the air valve of CPLD (CPLD) input pneumatic marker head.Adopt ripe at present electric design automation (EDA) technology, CPLD can realize finishing the high-speed synchronous D/A conversion of multi-channel analog input, therefore the marking of control signal of microprocessor generation is by CPLD (CPLD) effect, when the external PS2 keyboard of needs or other expansion I/Os, also can realize and being connected of microprocessor by CPLD, can select EPM7128STC100~10 chips for use during concrete enforcement of the new plough of this practicality, connect more specifically according to external and programming decision, can be referring to the explanation of chip data.Memory provides program running space and deposit data space.Interface is provided with according to the peripheral hardware situation, general double USB mouth and the serial ports established.Display selects the common LED device to get final product, and belongs to mature part in the prior art.The low-power consumption clock chip DS1302 that real-time clock of the present utility model adopts U.S. DALLAS company to release: traditional data record mode be every the time sampling or timing sampling, there is not concrete time interocclusal record, therefore can only record data and time that can't its appearance of accurate recording; If adopt the single-chip microcomputer timing, need on the one hand to adopt counter, take hardware resource, need to be provided with interruption, inquiry etc. on the other hand, expend the resource of single-chip microcomputer equally, and some TT﹠C system may not allow.In system, adopt DS1302 then can address this problem well.System needs during concrete enforcement power module and voltage monitoring, cpld interface socket etc. belong to prior art, do not do and give unnecessary details.
Microprocessor adopts reduced instruction set computer (RISC) processor.Mach and the control program work of risc processor by embedding, function singleness, operational efficiency height.
ARM (Advanced RISC Machines) is a tame esbablished corporation of microprocessor industry, has designed big quantity high performance, cheapness, the low risc processor of power consumption, has become the RISC standard.The utility model has been selected the AT91M40800 chip U1 of Atmel company based on the ARM7TDMI kernel for use.AT91M40800 has the very a chip of high performance-price ratio in the AT91 16/32 8-digit microcontroller series released of Atmel company.It is based on the ARM7TDMI kernel, include SRAM, external bus interface able to programme (EBI), 3 passages, 16 digit counters/timer, 32 programmable I/O mouths, interrupt control unit, 2 USART (wherein each respectively is with 2 special external recording controllers), programmable watchdog timer, master clock circuit and DRAM sequential control circuits on high performance 32 risc processors, 16 high integration instruction set, the 8KB sheet, and be furnished with senior energy-saving circuit; Simultaneously, can support the JTAG debugging, dominant frequency can reach 40MHz.The AT91M40800 chip supports JTAG (combined testing action group, a kind of international standard test protocol) boundary scan to test in application program system, and the JP among Fig. 2 is jtag interface.The serial data input SCLK of DS1302 chip U2 links to each other with the control pin P17 of U1, and serial data I/O end links to each other with the control pin P16 of microprocessor, and microprocessor is controlled its reset pin NRST by the P18 output signal.Also have external crystal-controlled oscillation GXO in addition, be used for producing accurate and stable clock signal.
Described memory comprises random-access memory (ram) and flash memory (FLASH), and RAM is connected in the two-way communication mode with microprocessor respectively with FLASH.RAM is main running space as program in system, store data and stack area, the RAM employing monolithic IS61LV25616 chip U3 of the utility model embodiment (256K * 16bit), for the ease of implementing, annexation can be more specifically: its data pin I/O0~I/O15 is by data/address bus (D0~D15) link to each other with data pin D0~D15 of U1, its address pin A0~A17 by address bus (A1~A18) link to each other with address pin A1~A18 of U1, its write operation enables input WE, read operation enables input OE, sheet selects input CE, low level control LB, high-order control UB respectively with the corresponding control pin NWRO/NEW of U1, NRD/NOE, NCS1, AO/NLB, NWRI/NUB links to each other.The FLASH memory has the characteristic that data were wiped and stored to low electricity, and word-base data required in tab file that the user edits and the mark can be saved in wherein.The FLASH memory of the utility model embodiment adopts AT49BV16147-90 chip U4, for the ease of implementing, annexation can be more specifically: its data pin I/O0~I/O15 is by data/address bus (D0~D15) link to each other with data pin D0~D15 of U1, its address pin AO~A19 is by address bus (A1~A19, P28/A20) with address pin A1~A19 of U1, P28/A20/CS25 links to each other, and its write operation enables input WE, read operation enables input OE, sheet selects input CE, reset pin RESET respectively with the corresponding control pin NWRO/NEW of U1, NRD/NOE, NCS0, NRST links to each other.
The I/O interface of the utility model embodiment setting comprises USB (USB) interface, serial ports, standard flash memory (CF) clamping mouth.USB interface, serial ports are to establish for font file and marker graphic that download user is edited on computers, CF clamping mouth is set after, also can dump in the marker system by the CF card.CF is the present big capacity movable storage device of minimum in the world, and the utility model is provided with the CF interface as main external memory interface, in order to avoid the CF card reader of extra purchase of user and usb compatible.A kind of CFSOCKET Plug pin patch bay U5 that the utility model adopts, its data pin D0~D15, address pin A1~A3 are used for and the CF card connection, its write operation Enable Pin IOWR, read operation Enable Pin IORD, reset pin RESET link to each other with corresponding control pin NWRO/NEW, NRD/NOE, the NRST of U1 respectively, by the microprocessor control that sets driver.
The utility model adopts MAX232 chip U6 to realize the serial ports of RS232 standard, the T1IN of MAX232 chip, T2IN, R1OUT, R2OUT is the pin that connects the TTL/CMOS level, TXDSA, TXDSB, R1IN, R2IN is the pin that connects the RS232A level, therefore for the ease of implementing, annexation can be more specifically: T1IN, T2IN meets the P14/TXD0 of U1 respectively, the P21/TXD1/NTR1 pin, R1OUT, R2OUT meets the P15/RXD0 of U1 respectively, the P22/RXD pin, TXDSA, TXDSB is used for connecing the receiving terminal of peripheral hardware, R1IN, R2IN is used for connecing the transmitting terminal of peripheral hardware.The utility model adopts PDIVSBD12 chip U7 to realize the USB mouth, for the ease of implementing, annexation can be more specifically: its data pin D0~D7 links to each other with data pin D0~D7 of U1 by data/address bus D0~D7, its address pin A0 links to each other with the address pin A2 of U1 by address bus A2, its read gate pin RD_N, write gate pin WR_N, interrupt pin INT_N, reset pin RESET_N link to each other with corresponding control pin NRD/NOE, NWRO/NEW, P11/IRO2, the NRST of U1 respectively, and usb data line D-, D+ are connected with the USB peripheral hardware in use.
The normal steady operation of whole system just depends on the mutual coordination of each part mentioned above.When the utility model uses, be provided with by the periphery and cooperate microprocessor operation program down, the mark of control pneumatic marker head can be adopted modular construction on the software level: comprise the main program module that real-time clock (RTC) read-write and FLASH operate; Comprise the human-computer interaction module that keyboard/the button input is read, LCD shows, comprise the file system module of tab file management, the operation of CF card; The communication module that comprises usb communication, serial communication; The marking of control module that comprises Electric Machine Control and Air Valve Control.The software configuration of modularization programming is clear, easy to maintenance, cooperates with the utility model more to help providing the stability of a system and reliability.

Claims (6)

1. pneumatic marker, have pneumatic marker head and support, it is characterized in that: comprise with the microprocessor being the digital control system of kernel control chip, the peripheral expansion of microprocessor is provided with real-time clock, memory, input/output interface, display, and the marking of control signal that microprocessor produces is by the motor and the air valve of CPLD input pneumatic marker head.
2. pneumatic marker as claimed in claim 1 is characterized in that: described microprocessor adopts reduced instruction set computer (RISC) processor.
3. pneumatic marker as claimed in claim 2 is characterized in that: described risc processor adopts the AT91M40800 of Atmel company.
4. as claim 1 or 2 or 3 described pneumatic markers, it is characterized in that: described memory comprises SRAM and FLASH, and SRAM is connected in the two-way communication mode with microprocessor respectively with FLASH.
5. as claim 1 or 2 or 3 described pneumatic markers, it is characterized in that: described input/output interface comprises USB interface, serial ports, CF clamping mouth, is connected in the two-way communication mode with microprocessor respectively.
6. pneumatic marker as claimed in claim 4 is characterized in that: described input/output interface comprises USB interface, serial ports, CF clamping mouth, is connected in the two-way communication mode with microprocessor respectively.
CN 200420057742 2004-12-14 2004-12-14 Pneumatic marking device Expired - Fee Related CN2763043Y (en)

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Application Number Priority Date Filing Date Title
CN 200420057742 CN2763043Y (en) 2004-12-14 2004-12-14 Pneumatic marking device

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Application Number Priority Date Filing Date Title
CN 200420057742 CN2763043Y (en) 2004-12-14 2004-12-14 Pneumatic marking device

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CN2763043Y true CN2763043Y (en) 2006-03-08

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231060A (en) * 2011-07-18 2011-11-02 北京航天福道高技术股份有限公司 General-purpose hardware platform device
CN101259791B (en) * 2007-03-09 2012-11-07 珠海天威技术开发有限公司 Multiple ink box chips parallel working low-power consumption treatment method
CN103192616A (en) * 2013-04-25 2013-07-10 桂林国际电线电缆有限责任公司 Code printing machine capable of using external storage information

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101259791B (en) * 2007-03-09 2012-11-07 珠海天威技术开发有限公司 Multiple ink box chips parallel working low-power consumption treatment method
CN102231060A (en) * 2011-07-18 2011-11-02 北京航天福道高技术股份有限公司 General-purpose hardware platform device
CN103192616A (en) * 2013-04-25 2013-07-10 桂林国际电线电缆有限责任公司 Code printing machine capable of using external storage information

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C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060308

Termination date: 20101214