CN2751446Y - Structure of multi-grid dielectric layer - Google Patents
Structure of multi-grid dielectric layer Download PDFInfo
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- CN2751446Y CN2751446Y CN 200420059202 CN200420059202U CN2751446Y CN 2751446 Y CN2751446 Y CN 2751446Y CN 200420059202 CN200420059202 CN 200420059202 CN 200420059202 U CN200420059202 U CN 200420059202U CN 2751446 Y CN2751446 Y CN 2751446Y
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Abstract
The utility model provides a structure of multiple-grid dielectric layer, wherein the structure of the multiple-grid dielectric layer is that the multiple-grid dielectric layer contains a high permittivity dielectric layer which deposits on a semiconductor basement with an original oxide layer, and the permittivity of the high permittivity dielectric layer is over 8. The high permittivity dielectric layer is not formed in a high-performance component region, and it is taken as a portion of a grid dielectric layer of a low leakage current component region.
Description
Technical field
The utility model relates to a kind of structure of multiple grid dielectric layer, and particularly relevant for a kind of structure that can be applicable to the bigrid dielectric layer of high-effect assembly and low-leakage current assembly.
Background technology
The integrated circuit of multi-functional is the trend of integrating at present, and it must possess at same chip (chip) goes up the transistor that manufacturing has different qualities.Particularly, for the grid oxic horizon of different-thickness is set on same chip, so that the transistor with different operating voltage to be provided.
Service speed for lifting subassembly, often with logical circuit (logic circuit) and main memory circuit (memory circuit) mixing manufacture on same chip, this kind mixes the assembly that is provided with and is called embedded semiconductor device (embedded semiconductor device).Usually, logical circuit needs thin grid oxic horizon, and can be in the work down of about about 1.8 to 2.5 volts operating voltage, to improve transistorized switch speed (switching speed); Memory cell areas and its periphery circuit region then need thicker grid oxic horizon, and can be in the work down of about about 3.0 to 5.0 volts operating voltage.
Tradition is made the method for two kinds of different thickness of grid oxide layer respectively two zoness of different; be prior to forming the ground floor grid oxic horizon on the silicon base; protect the grid oxic horizon of first area afterwards by photoresist layer, and utilize etching method to remove the grid oxic horizon of second area.After photoresist layer removed, carry out the processing procedure of secondary grid oxic horizon,, also can increase and be positioned at the first grid thickness of oxide layer of first area this moment to form grid oxic horizon with second thickness in second area.Therefore, the first area of silicon base has the first grid oxide layer of first thickness, and second area has the second grid oxide layer of second thickness.
In addition, United States Patent (USP) the 5th, 668, No. 035 people such as Fang discloses a kind of manufacture method of bigrid oxide layer, can avoid photoresistance directly to contact grid oxic horizon and make it contaminated, it is at first after forming the first grid oxide layer in the substrate, on the first grid oxide layer of memory cell areas, form first polysilicon layer, remove the first grid oxide layer that is exposed to logic circuit area afterwards, the substitute is the second grid oxide layer of thinner thickness, form one deck second polysilicon layer afterwards, and utilize lithography that second polysilicon layer is covered on the second grid oxide layer of logic circuit area, continue on first and second polysilicon layers and to form a layer insulating, and utilize micro image etching procedure to be defined itself and first and second polysilicon layers of below, with the formation gate electrode.United States Patent (USP) the 6th, 265, No. 325 people such as Cao more disclose a kind of method that improves the processing procedure of above-mentioned Fang case, and it is after forming second polysilicon layer, utilize chemical mechanical milling method to remove part second polysilicon layer, make first polysilicon layer have identical level with second polysilicon layer.But, basically, its method that forms the bigrid oxide layer is identical.
United States Patent (USP) the 6th, 383, No. 861 people such as Gonzalez disclose a kind of one deck silicon nitride layer that forms in substrate, remove the silicon nitride layer of memory cell areas afterwards, then growth one deck silicon oxide layer in whole substrate, the thickness of the silicon oxide layer that memory cell areas is grown up can be thicker than the thickness of the silicon oxide layer on the silicon nitride layer of logic circuit area.
United States Patent (USP) the 6th, 168, No. 958 people such as Gardner disclose a kind of manufacture method with dielectric layer with high dielectric constant of different-thickness, it is that deposition one layer thickness is about 100-500 dust dielectric constant and is about 20 dielectric layer in substrate, and on this dielectric layer, form the first grid conductive layer, then utilize micro image etching procedure to remove the first grid conductive layer of subregion, and the dielectric layer that exposes of this zone of etching, make its thickness be reduced to second thickness, on this regional dielectric layer, form the second grid conductive layer again.
Summary of the invention
Because the integrated circuit of multi-functional is to the transistorized demand of different qualities, the utility model provides a kind of structure of multiple grid dielectric layer.
The utility model provides a kind of structure of multiple grid dielectric layer.It comprises: the first grid dielectric layer that is arranged at high-effect assembly district; And the second grid dielectric layer that forms by dielectric layer with high dielectric constant and interface dielectric layer stack that is arranged at low-leakage current assembly district.Wherein, the interface dielectric layer is that the dielectric constant of dielectric layer with high dielectric constant is greater than 8 at semiconductor-based the end at dielectric layer with high dielectric constant with.
The structure of the utility model and a kind of multiple grid dielectric layer.It comprises: the first grid dielectric layer that is arranged at the first area; Be arranged at second area by second grid dielectric layer that native oxide constituted; And be arranged at one the 3rd gate dielectric that the 3rd district is formed by a dielectric layer with high dielectric constant and this native oxide storehouse.Wherein, the dielectric constant of first grid dielectric layer is different from the dielectric constant of second grid dielectric layer.Wherein, native oxide is that the dielectric constant of dielectric layer with high dielectric constant is greater than 8 at semiconductor-based the end at dielectric layer with high dielectric constant with.
The utility model also provides a kind of structure of multiple grid dielectric layer.It comprises: the first grid dielectric layer that is arranged at the first area; Be arranged at a second grid dielectric layer that is constituted by a sedimentary deposit of second area; Be arranged at one the 3rd gate dielectric that the 3rd zone is formed by a dielectric layer with high dielectric constant and this sedimentary deposit storehouse.Wherein, the material of first grid dielectric layer comprises an element at the semiconductor-based end.Wherein, the dielectric constant of first grid dielectric layer is different from the dielectric constant of second grid dielectric layer.Wherein, sedimentary deposit is that the dielectric constant of dielectric layer with high dielectric constant is greater than 8 at semiconductor-based the end at dielectric layer with high dielectric constant with.
In a second embodiment, wherein after forming dielectric layer with high dielectric constant, the suprabasil low-leakage current assembly of semiconductor district more comprises: the native oxide that removes high-effect assembly district; And form a dielectric layer in the semiconductor-based basal surface in high-effect assembly district.And the method for this dielectric layer comprises and carries out oxidation processes, or carries out oxidation processes and nitrogen treatment in regular turn.Wherein, the employed oxidizing gas of oxidation processes comprises steam (H
2O
(g)), oxygen (O
2), ozone (O
3), nitrogen monoxide (NO), nitrous oxide (N
2One of O) person or its combination.Therefore, the material of this dielectric layer comprises SiO
2, SiON, SiO
2One of/SiON is laminated person or its combination.
In the 3rd embodiment, wherein before forming dielectric layer with high dielectric constant, more comprise removing native oxide at semiconductor-based the end; And on the semiconductor-based end, form dielectric layer with high dielectric constant, and remove after the part that is positioned at high-effect assembly district, more be included between the semiconductor-based basal surface in the semiconductor-based basal surface in high-effect assembly district and low-leakage current assembly district and the dielectric layer with high dielectric constant and form an interface dielectric layer.Wherein, the method that removes native oxide is included in temperature and roughly is higher than and carries out the hydrogen baking under 700 ℃.Wherein, the method that forms the interface dielectric layer comprises carries out oxidation processes, perhaps carries out oxidation processes and nitrogen treatment in regular turn.Wherein, the employed oxidizing gas of oxidation processes comprises steam (H
2O
(g)), oxygen (O
2), ozone (O
3), nitrogen monoxide (NO), nitrous oxide (N
2One of O) person or its combination.Therefore, the material of interface dielectric layer comprises SiO
2, SiON, SiO
2One of/SiON is laminated person or its combination.
In the 4th embodiment, wherein before forming dielectric layer with high dielectric constant, more comprise removing native oxide at semiconductor-based the end; And on the semiconductor-based end, form dielectric layer with high dielectric constant, and remove after the part that is positioned at high-effect assembly district, more be included in semiconductor-based basal surface and form an interface dielectric layer; And on the dielectric layer of the interface in low-leakage current district, form dielectric layer with high dielectric constant.Wherein, the material of interface dielectric layer comprises SiO
2, SiON, SiO
2One of/SiON is laminated person or its combination.
In the 5th embodiment, wherein before forming dielectric layer with high dielectric constant, more comprise removing native oxide at semiconductor-based the end.And, on the semiconductor-based end, form dielectric layer with high dielectric constant, and remove after the part that is positioned at high-effect assembly district, more be included in this semiconductor-based basal surface and form an interface dielectric layer; On the dielectric layer of the interface in low-leakage current district, form dielectric layer with high dielectric constant; Remove the interface dielectric layer in high-effect assembly district; And form a dielectric layer in the semiconductor-based basal surface in high-effect assembly district.Wherein, the material of interface dielectric layer comprises SiO
2, SiON, SiO
2One of/SiON is laminated person or its combination.
Description of drawings
Figure 1A to Figure 1B is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model first embodiment forms gate dielectric;
Fig. 2 A to Fig. 2 D is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model second embodiment forms gate dielectric;
Fig. 3 A to Fig. 3 C is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model the 3rd embodiment forms gate dielectric;
Fig. 4 A to Fig. 4 B is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model the 4th embodiment forms gate dielectric;
Fig. 5 A to Fig. 5 D is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model the 5th embodiment forms gate dielectric;
Fig. 6 is the method flow diagram that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of expression the utility model first and second embodiment forms gate dielectric;
Fig. 7 is the method flow diagram that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of expression the utility model the 3rd embodiment forms gate dielectric;
Fig. 8 is the method flow diagram that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of expression the utility model the 4th and the 5th embodiment forms gate dielectric.
Symbol description:
High-effect assembly district: I
Low-leakage current assembly district: II
The semiconductor-based end: 10,20,30,40,50
Assembly isolation structure: 12,22,32,42,52
Native oxide: 13,23
The dielectric material layer of high-k: 15,25,35,45,55
Etch mask layer: 16;
Semiconductor-based basal surface dielectric layer becomes long-range order: 80
Dielectric layer: 26
Interface dielectric layer: 36,44,54
Processing procedure: A, B, C, D, E
Step 1: the semiconductor substrate is provided, and the surface has a native oxide;
Step 2: remove native oxide;
Step 3: deposit an interface dielectric layer;
Step 4: deposition and definition dielectric layer with high dielectric constant are in low-leakage current assembly district;
Step 5: the interface dielectric layer that removes high-effect assembly district;
Step 6: the native oxide that removes high-effect assembly district;
Step 7: carry out semiconductor-based basal surface dielectric layer and become long-range order;
Embodiment
The utility model is to utilize dielectric layer with high dielectric constant and other dielectric material to form the gate dielectric with differing dielectric constant, and wherein dielectric layer with high dielectric constant is generally used for requiring the transistor component that leakage current will be low.In addition, dielectric layer with high dielectric constant and have an interface directly contacts with the semiconductor-based end in order to avoid dielectric layer with high dielectric constant at semiconductor-based the end.Fast for requiring the switch switch speed, the transistorized gate dielectric that usefulness will be good, not high to the requirement of leakage current, then adopt the low relatively dielectric material of dielectric constant usually.Below be to describe the utility model in detail for several embodiment.
First embodiment:
Figure 1A to Figure 1B is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model first embodiment forms gate dielectric.
At first please refer to Figure 1A, semiconductor substrate 10 is provided, for example be the semiconductor-based end of occurring matrix type (bulk semiconductor substrate) (for example silicon base, silicon-Germanium base) or silicon-coated insulated type substrate (silicon-on-insulator substrate, SOI substrate).Formed assembly isolation structure 12 in the semiconductor-based end 10, for example field oxide (field oxidelayer) or groove isolation construction (trench isolation) are to be example with the latter in graphic.High-effect assembly district (high-performance deviceregion) I and low-leakage current assembly district (low-leakage device region) II can roughly be divided in this semiconductor-based end 10.
Usually, the semiconductor-based end 10, during one processing procedure, can generate layer of oxide layer in the surface under waiting for, be referred to as native oxide (native oxide) 13 usually, and its thickness is for number dust (), normally less than 5 dusts.Then, the dielectric material of deposition one deck high-k (highK) on native oxide 13, its deposition process for example is chemical vapour deposition technique (CVD), sputtering method (sputtering), reaction equation sputtering method (reactive sputtering).Then, the dielectric material layer 15 of definition high-k makes it be covered in low-leakage current assembly district II, and the part of high-effect assembly district I then removes by wet etching or dry ecthing.Its define method for example is prior to forming one deck etch mask layer 16 on the dielectric material layer 15 of high-k; for example be energy-sensitive dye layer (particularly for example being photoresist layer); and this etch mask floor has the pattern that covers low-leakage current assembly district II; then protect the dielectric material floor 15 of the high-k of low-leakage current assembly district II with this etch mask floor; remove the dielectric material floor 15 of the high-k that is exposed to high-effect assembly district I by etching step, end to the native oxide 13 that exposes high-effect assembly district I.Afterwards, this etch mask layer 16 is removed.
Wherein, the dielectric material at the high-k of this indication is meant that dielectric constant is greater than the material more than 8.The dielectric material of above-mentioned high-k for example is metal oxide (metallicoxides), metal oxynitride, metal nitride (metallic nitride), metal silicate (metallic silicate) and metal aluminate (metallic aluminates).Wherein, the metal oxide of high-k hafnium oxide (hafnium oxide, HfO for example
2), zirconia (zirconium oxide, ZrO
2), aluminium oxide (aluminum oxide, Al
2O
3), lanthana (lanthanum oxide, La
2O
3), titanium oxide (titanium oxide, TiO
2), yittrium oxide (yttrium oxide, Y
2O
3), tantalum oxide (tantalum oxide, Ta
2O
5) etc.; The metal oxynitride of high-k is nitrogen zirconia (ZrON), nitrogen hafnium oxide (HfON) etc. for example; The metal silicate of high-k is zirconium silicate (zirconium silicate, ZrSiO for example
4); The metal aluminate of high-k is zirconium aluminate (zirconium aluminate) for example.
Wherein, aspect the dielectric material layer 15 of definition high-k, for example, can utilize sulfuric acid (H
2SO
4) the etching material is zirconia (ZrO
2) the dielectric material layer.
Through above-mentioned A processing procedure corresponding to Fig. 6, after carrying out the processing procedure of step 1 and step 4 in regular turn, as gate dielectric, low-leakage current assembly district II is laminated as gate dielectric with native oxide 13 and high K dielectric material layers 15 with native oxide 13 for the high-effect assembly district I on surface, the semiconductor-based ends 10.
Second embodiment:
Fig. 2 A to Fig. 2 D is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model second embodiment forms gate dielectric.
At first please refer to Fig. 2 A, semiconductor substrate 20 is provided, for example is the semiconductor-based end of occurring matrix type or silicon-coated insulated type substrate.Formed assembly isolation structure 22 in the semiconductor-based end 20, for example field oxide or groove isolation construction are to be example with the latter in graphic.High-effect assembly district I and low-leakage current assembly district II can roughly be divided in this semiconductor-based end 20.
Usually, the semiconductor-based end 20, during one processing procedure, can generate layer of oxide layer in the surface under waiting for, be commonly referred to as native oxide 23, and its thickness is for the number dust, normally less than 5 dusts.
Please refer to Fig. 2 B, the then dielectric material of deposition one deck high-k on native oxide 23, its material and deposition process are as described in first embodiment, in this few superfluous words.Then, the dielectric material layer 25 of definition high-k makes it be covered in low-leakage current assembly district II, and the part of high-effect assembly district I then removes by wet etching or dry ecthing.
Then please refer to Fig. 2 C, remove the native oxide 23 that is exposed to high-effect assembly district I.
The method of above-mentioned dielectric material layer 25 that removes the part high-k and native oxide 23 for example is prior to forming one deck energy-sensitive dye layer (not illustrating) on the dielectric material layer 25 of high-k, it for example is photoresist layer, and this energy-sensitive dye layer has the pattern that covers low-leakage current assembly district II, be etch mask then with this energy-sensitive dye layer, remove the dielectric material floor 25 and the native oxide 23 of the high-k that is exposed to high-effect assembly district I in regular turn by etching step, afterwards this energy-sensitive dye layer is removed.
Then please refer to Fig. 2 D, carrying out semiconductor-based basal surface dielectric layer and become long-range order 80, for example be oxidation processes (oxidizing treatment), or oxidation processes adds nitrogen treatment, form one dielectric layer 26 with the surface in substrate 20, its material for example is SiO
2, SiON or SiO
2/ SiON is laminated.
Wherein, with the material be SiO
2Dielectric layer 26 be example, its thickness at high-effect assembly district I is about the 2-30 Izod right side, the formation method for example is to carry out the high-temperature oxydation processing procedure, employed oxidizing gas comprises steam (H
2O
(g)), oxygen (O
2), ozone (O
3), nitrogen monoxide (NO) or nitrous oxide (N
2O).Particularly, the high-temperature oxydation processing procedure for example is single-wafer type Rapid Thermal processing procedure (single-wafer rapid-thermal based process), be about 850 ℃ in temperature, pressure is about under 6 Bristols (torr), produces (in-situ steamgeneration with synchronous steam; ISSG) silica that generates of mode.Or the furnace oxidation processing procedure, be about 600-800 ℃ in temperature, be atmospheric pressure and contain oxygen (O at pressure
2) environment under, oxidation 1-30 minute.
Wherein, with the material be SiON or SiO
2The laminated dielectric layer 26 of/SiON is an example, its at the equivalent silicon oxide thickness of high-effect assembly district I approximately less than 10 dusts, its formation method for example is after carrying out the high-temperature oxydation processing procedure, carry out again long-range electricity slurry nitridation reaction (remote plasmanitridation, RPN).When carrying out long-range electricity slurry nitridation reaction, since the formed silica of high-temperature oxydation processing procedure can be exposed to highdensity long-range with helium base nitrogen fluid (high-density remote helium-based nitrogen discharge) under, to carry out nitrogen treatment.Nitrogen free radical in the electricity slurry can generate nitrogenous gate dielectric with the silica reaction.
Through above-mentioned B processing procedure corresponding to Fig. 6, after carrying out the processing procedure of step 1, step 4, step 6 and step 7 in regular turn, as gate dielectric, low-leakage current assembly district II is laminated as gate dielectric with native oxide 23 and high K dielectric material layers 25 with dielectric layer 26 for the high-effect assembly district I on surface, the semiconductor-based ends 20.
The 3rd embodiment:
Fig. 3 A to Fig. 3 C is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model the 3rd embodiment forms gate dielectric.
At first please refer to Fig. 3 A, semiconductor substrate 30 is provided, wherein formed assembly isolation structure 32, for example field oxide or fleet plough groove isolation structure are to be example with the latter in graphic.
Then, before surface deposition of the semiconductor-based ends 30, carry out the surface clean step, to remove the native oxide on surface, the semiconductor-based ends 30, it removes method for example is at high temperature to carry out hydrogen baking (hydrogen baking), temperature is approximately higher than 700 ℃ greatly, makes native oxide form the silicon monoxide (SiO of volatile
(g)) or aqueous vapor (H
2O
(g)) and remove.Other method that removes native oxide also is applicable to this.
Then please refer to Fig. 3 B, in the dielectric material of 30 surface deposition one deck high-ks (highK) of the semiconductor-based end, its material and deposition process are as described in first embodiment, in this few superfluous words.Then, the dielectric material layer 35 of definition high-k makes it be covered in low-leakage current assembly district II, and the part of high-effect assembly district I then removes by wet etching or dry ecthing.Its define method for example is prior to forming one deck energy-sensitive dye layer (not illustrating) on the dielectric material layer 35 of high-k, it for example is photoresist layer, and this energy-sensitive dye layer has the pattern that covers low-leakage current assembly district II, be etch mask then with this energy-sensitive dye layer, remove the dielectric material floor 35 of the high-k that is exposed to high-effect assembly district I by etching step, afterwards this energy-sensitive dye layer is removed.
Please refer to Fig. 3 C, then carry out semiconductor-based basal surface dielectric layer and become long-range order 80, for example be oxidation processes (oxidizing treatment), or oxidation processes adds nitrogen treatment, to form a very thin bed boundary dielectric layer 36 between the dielectric material layer 35 of the surface of substrate 30 and substrate 30 and high-k.The material of interface dielectric layer 36 for example is SiO
2, SiON or SiO
2/ SiON is laminated, and its formation method is seldom given unnecessary details at this as the formation of the described dielectric layer 26 of second embodiment.
Through above-mentioned C processing procedure corresponding to Fig. 7, carry out step 1, step 2, step 4 and step 7 in regular turn ' processing procedure after, as gate dielectric, low-leakage current assembly district II is laminated as gate dielectric with interface dielectric layer 36 and high K dielectric material layers 35 with interface dielectric layer 36 for the high-effect assembly district I on surface, the semiconductor-based ends 30.
The 4th embodiment:
Fig. 4 A to Fig. 4 B is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model the 4th embodiment forms gate dielectric.
At first please refer to Fig. 4 A, semiconductor substrate 40 is provided, wherein formed assembly isolation structure 42, for example field oxide or fleet plough groove isolation structure are to be example with the latter in graphic.
Then please refer to Fig. 4 B, in 40 surface depositions, one bed boundary dielectric layer 44 of the semiconductor-based end, its material for example is SiO
2, SiON, SiO
2/ SiON is laminated, one of metal silicate (for example zirconium silicate) or metal aluminate (for example zirconium aluminate) person or its combination.
Then, continue to form the dielectric material layer 45 of one deck high-k above interface dielectric layer 44, its material and deposition process are as described in first embodiment, in this few superfluous words.Then, carry out micro image etching procedure, the dielectric material layer 45 of definition high-k makes it be covered in low-leakage current assembly district II, and the part of high-effect assembly district I then removes by wet etching or dry ecthing.
Through above-mentioned D processing procedure corresponding to Fig. 8, after carrying out the processing procedure of step 1, step 2, step 3 and step 4 in regular turn, as gate dielectric, low-leakage current assembly district II is laminated as gate dielectric with interface dielectric layer 44 and high K dielectric material layers 45 with interface dielectric layer 44 for the high-effect assembly district I on surface, the semiconductor-based ends 40.
The 5th embodiment:
Fig. 5 A to Fig. 5 D is a profile, the method that high-effect assembly district and the low-leakage current assembly district respectively at the semiconductor-based end of its expression the utility model the 5th embodiment forms gate dielectric.
At first please refer to Fig. 5 A, semiconductor substrate 50 is provided, wherein formed assembly isolation structure 52, for example field oxide or fleet plough groove isolation structure are to be example with the latter in graphic.
Then please refer to Fig. 5 B, in 50 surface depositions, one bed boundary dielectric layer 54 of the semiconductor-based end, its material for example is SiO
2, SiON, SiO
2/ SiON is laminated, one of metal silicate (for example zirconium silicate) or metal aluminate (for example zirconium aluminate) person or its combination.
Then, continue to form the dielectric material layer 55 of one deck high-k above interface dielectric layer 54, its material is as described in first embodiment, in this few superfluous words.Then, carry out micro image etching procedure, the dielectric material layer 55 of definition high-k makes it be covered in low-leakage current assembly district II, and the part of high-effect assembly district I then removes by wet etching or dry ecthing.
Then please refer to Fig. 5 C, continue to remove the interface dielectric layer 54 that is exposed to high-effect assembly district I.
The method of above-mentioned dielectric material layer 55 that removes the part high-k and interface dielectric layer 54 for example is prior to forming one deck energy-sensitive dye layer (not illustrating) on the dielectric material layer 55 of high-k, it for example is photoresist layer, and this energy-sensitive dye layer has the pattern that covers low-leakage current assembly district II, be etch mask then with this energy-sensitive dye layer, remove the dielectric material floor 55 and the interface dielectric layer 54 of the high-k that is exposed to high-effect assembly district I in regular turn by etching step, afterwards this energy-sensitive dye layer is removed.
Then please refer to Fig. 5 D, then, carry out semiconductor-based basal surface dielectric layer and become long-range order 80, form very thin one dielectric layer 56 with surface in the semiconductor-based end 50 that exposes.The material of dielectric layer 56 for example is SiO
2, SiON, SiO
2/ SiON is laminated, and its formation method is seldom given unnecessary details at this as the formation of the described dielectric layer 26 of second embodiment.
Through behind the above-mentioned processing procedure, through above-mentioned E processing procedure corresponding to Fig. 8, after carrying out the processing procedure of step 1, step 2, step 3, step 4, step 5 and step 7 in regular turn, as gate dielectric, low-leakage current assembly district II is laminated as gate dielectric with high K dielectric material layers 55 and interface dielectric layer 54 with dielectric layer 56 for the high-effect assembly district I on surface, the semiconductor-based ends 50.
Heavy gate dielectric structure be to comprise semiconductor substrate 50, and this semiconductor-based end 50 was to be divided into a high-effect assembly district I and a low-leakage current assembly district II more than this preferred embodiment was described.This high-effect assembly district I has this dielectric layer 56, and this low-leakage current assembly district II has at laminated this semiconductor-based end 50 that is formed at that is made of this high K dielectric material layers 55 and this interface dielectric layer 54, and wherein to have a dielectric constant be greater than 8 to this high K dielectric material layers 55.
The 6th embodiment:
First above-mentioned embodiment and the processing procedure of second embodiment can also be integrated mutually, and prepare three kinds of different gate dielectrics.First kind is (for example to be SiO to carry out the dielectric layer that semiconductor-based basal surface dielectric layer becomes long-range order to be generated
2, SiON or SiO
2/ SiON is laminated) as gate dielectric; Second kind is as gate dielectric with native oxide; The third is laminated as gate dielectric with high K dielectric material layers and native oxide.
Below be with table one, and cooperate Fig. 6 to do explanation.At first provide the semiconductor substrate surface to have a native oxide as step 1; Then cover the whole semiconductor-based end as step 4 deposition dielectric layer with high dielectric constant, define dielectric layer with high dielectric constant afterwards, to remove the dielectric layer with high dielectric constant of area I and II, its define method for example is to form one deck etch mask layer on dielectric layer with high dielectric constant, stop as etching with this etch mask layer, utilize etch process to remove to be exposed to the dielectric layer with high dielectric constant of area I and II; Then as step 6 definition native oxide, to remove the native oxide of area I, its define method for example is to form one deck etch mask layer on dielectric layer with high dielectric constant and native oxide, stop as etching with this etch mask layer, utilize etch process to remove to be exposed to the native oxide of area I; Then carrying out semiconductor-based basal surface dielectric layer as step 7 becomes long-range order, with in the semiconductor-based basal surface growth one dielectric layer of area I.
The integration processing procedure of table one first and second embodiment
| The step of corresponding diagram 6 | Fabrication steps in regular turn | Area I | Area I I | Area |
| Step | ||||
| 4 | The deposition dielectric layer with high dielectric constant | Cover | Cover | Cover |
| The definition dielectric layer with high dielectric constant | Remove | | Keep | |
| Step | ||||
| 6 | The definition native oxide | Remove | Keep | Keep |
| Step 7 | Carry out semiconductor-based basal surface dielectric layer and become long-range order | Grow up | ||
| The structure of the gate dielectric of finishing | First kind | Second kind | The third | |
The 7th embodiment:
The 4th above-mentioned embodiment and the processing procedure of the 5th embodiment can also be integrated mutually, and prepare three kinds of different gate dielectrics.First kind is (for example to be SiO to carry out the dielectric layer that semiconductor-based basal surface dielectric layer becomes long-range order to be generated
2, SiON or SiO
2/ SiON is laminated) as gate dielectric; Second kind be with the deposition the interface dielectric layer as gate dielectric; The third is laminated as gate dielectric with the interface dielectric layer of high K dielectric material layers and deposition.
Below be with table two, and cooperate Fig. 8 to do explanation.At first provide the semiconductor substrate surface to have a native oxide as step 1; Then remove the native oxide of semiconductor-based basal surface as step 2; Then cover the whole semiconductor-based end as step 3 deposition one bed boundary dielectric layer; Then cover whole semiconductor basal region as step 4 deposition dielectric layer with high dielectric constant, define dielectric layer with high dielectric constant afterwards, to remove the dielectric layer with high dielectric constant of area I and II, its define method for example is to form one deck etch mask layer on dielectric layer with high dielectric constant, stop as etching with this etch mask layer, utilize etch process to remove to be exposed to the dielectric layer with high dielectric constant of area I and II; Then as step 5 definition interfaces dielectric layer, to remove the interface dielectric layer of area I, its define method for example is to form one deck etch mask layer on dielectric layer with high dielectric constant and interface dielectric layer, stop as etching with this etch mask layer, utilize etch process to remove to be exposed to the interface dielectric layer of area I; Then carrying out semiconductor-based basal surface dielectric layer as step 7 becomes long-range order, with in the semiconductor-based basal surface growth one dielectric layer of area I.
The integration processing procedure of table two the 4th and the 5th embodiment
| The step of corresponding diagram 8 | Fabrication steps in regular turn | Area I | Area I I | Area |
| Step | ||||
| 2 | Remove native oxide | Remove | Remove | Remove |
| Step 3 | Deposit an interface dielectric layer | Cover | | Cover |
| Step | ||||
| 4 | The deposition dielectric layer with high dielectric constant | Cover | Cover | Cover |
| The definition dielectric layer with high dielectric constant | Remove | Remove | Keep | |
| Step 5 | The definition interfaces dielectric layer | Remove | Keep | |
| Step 7 | Carrying out semiconductor-based basal surface is situated between | Grow up |
| The electricity layer becomes long-range order | ||||
| The structure of the gate dielectric of finishing | First kind | Second kind | The third | |
Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; anyly have the knack of this skill person; in not breaking away from spirit and scope of the present utility model; when doing a little change and retouching, therefore protection range of the present utility model is as the criterion when looking appended the claim scope person of defining.
Claims (16)
1. the structure of a multiple grid dielectric layer is characterized in that, comprising:
The semiconductor substrate, this semiconductor-based end, comprise a high-effect assembly district and a low-leakage current assembly district;
One first grid dielectric layer is arranged at this semiconductor-based basal surface in this high-effect assembly district;
A second grid dielectric layer that forms by a dielectric layer with high dielectric constant and an interface dielectric layer stack, be arranged at this semiconductor-based basal surface in this low-leakage current assembly district, this interface dielectric layer is that the dielectric constant of this dielectric layer with high dielectric constant is greater than 8 between this dielectric layer with high dielectric constant and this semiconductor-based end.
2. the structure of multiple grid dielectric layer according to claim 1 is characterized in that the material of this first grid dielectric layer comprises one of following material or its combination: a native oxide, SiO
2, SiON or SiO
2/ SiON is laminated.
3. the structure of multiple grid dielectric layer according to claim 1, the material that it is characterized in that this dielectric layer with high dielectric constant comprises one of following material or its combination: metal oxide, metal oxynitride, metal nitride, metal silicate or metal aluminate, and the material of this interface dielectric layer comprises SiO
2, SiON or SiO
2/ SiON is laminated.
4. the structure of multiple grid dielectric layer according to claim 3 is characterized in that:
This metal oxide comprises one of following material or its combination: hafnium oxide (HfO
2), zirconia (ZrO
2), aluminium oxide (Al
2O
3), lanthana (La
2O
3), titanium oxide (TiO
2), yittrium oxide (Y
2O
3) or tantalum oxide (Ta
2O
5);
This metal oxynitride comprises nitrogen zirconia (ZrON) or nitrogen hafnium oxide (HfON);
This metal silicate comprises zirconium silicate (ZrSiO
4);
This metal aluminate comprises zirconium aluminate.
5. the structure of multiple grid dielectric layer according to claim 1, the equivalent oxide thickness that it is characterized in that this first grid oxide layer is less than 10 dusts.
6. the structure of multiple grid dielectric layer according to claim 1, the thickness that it is characterized in that this dielectric layer with high dielectric constant in this second grid oxide layer is between 2 to 500 dusts.
7. the structure of multiple grid dielectric layer according to claim 1, the thickness that it is characterized in that this interface dielectric layer in this second grid oxide layer is between 2 to 30 dusts.
8. the structure of a multiple grid dielectric layer is characterized in that comprising:
The semiconductor substrate, this semiconductor-based end, comprise a first area, a second area and one the 3rd zone;
One first grid dielectric layer is arranged at this semiconductor-based basal surface of this first area;
By the second grid dielectric layer that an oxide layer is constituted, be arranged at this semiconductor-based basal surface of this second area, wherein the dielectric constant of this first grid dielectric layer is different from the dielectric constant of this second grid dielectric layer;
One the 3rd gate dielectric that forms by a dielectric layer with high dielectric constant and this oxide layer storehouse, be arranged at this semiconductor-based basal surface in the 3rd zone, this oxide layer is that the dielectric constant of this dielectric layer with high dielectric constant is greater than 8 between this dielectric layer with high dielectric constant and this semiconductor-based end.
9. the structure of multiple grid dielectric layer according to claim 8, the material that it is characterized in that this first grid dielectric layer are one of following material or its combination: SiO
2, SiON or SiO
2/ SiON is laminated.
10. the structure of multiple grid dielectric layer according to claim 8 is characterized in that the material of this dielectric layer with high dielectric constant comprises one of following material or its combination: metal oxide, metal oxynitride, metal nitride, metal silicate or metal aluminate.
11. the structure of multiple grid dielectric layer according to claim 10 is characterized in that:
This metal oxide comprises one of following material or its combination: hafnium oxide (HfO
2), zirconia (ZrO
2), aluminium oxide (Al
2O
3), lanthana (La
2O
3), titanium oxide (TiO
2), yittrium oxide (Y
2O
3) or tantalum oxide (Ta
2O
5);
This metal oxynitride comprises nitrogen zirconia (ZrON) or nitrogen hafnium oxide (HfON);
This metal silicate comprises zirconium silicate (ZrSiO
4);
This metal aluminate comprises zirconium aluminate.
12. the structure of a multiple grid dielectric layer is characterized in that comprising:
The semiconductor substrate, this semiconductor-based end, comprise a first area, a second area and one the 3rd zone;
One first grid dielectric layer is arranged at this semiconductor-based basal surface of this first area, and wherein the material of this first grid dielectric layer comprises an element at this semiconductor-based end;
By the second grid dielectric layer that a sedimentary deposit is constituted, be arranged at this semiconductor-based basal surface of this second area, wherein the dielectric constant of this first grid dielectric layer is different from the dielectric constant of this second grid dielectric layer;
One the 3rd gate dielectric that forms by a dielectric layer with high dielectric constant and this sedimentary deposit storehouse, be arranged at this semiconductor-based basal surface in the 3rd zone, this sedimentary deposit is that the dielectric constant of this dielectric layer with high dielectric constant is greater than 8 between this dielectric layer with high dielectric constant and this semiconductor-based end.
13. the structure of multiple grid dielectric layer according to claim 12 is characterized in that the material of this first grid dielectric layer is the dielectric material that contains the element silicon at this semiconductor-based end, comprises one of following material or its combination: SiO
2, SiON or SiO
2/ SiON is laminated.
14. the structure of multiple grid dielectric layer according to claim 12 is characterized in that the material of this sedimentary deposit comprises one of following material or its combination: SiO
2, SiON or SiO
2/ SiON is laminated.
15. the structure of multiple grid dielectric layer according to claim 12 is characterized in that the material of this dielectric layer with high dielectric constant comprises one of following material or its combination: metal oxide, metal oxynitride, metal nitride, metal silicate or metal aluminate.
16. the structure of multiple grid dielectric layer according to claim 15 is characterized in that:
This metal oxide comprises one of following material or its combination: hafnium oxide (HfO
2), zirconia (ZrO
2), aluminium oxide (Al
2O
3), lanthana (La
2O
3), titanium oxide (TiO
2), yittrium oxide (Y
2O
3) or tantalum oxide (Ta
2O
5);
This metal oxynitride comprises nitrogen zirconia (ZrON) or nitrogen hafnium oxide (HfON);
This metal silicate comprises zirconium silicate (ZrSiO
4);
This metal aluminate comprises zirconium aluminate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420059202 CN2751446Y (en) | 2004-05-25 | 2004-05-25 | Structure of multi-grid dielectric layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420059202 CN2751446Y (en) | 2004-05-25 | 2004-05-25 | Structure of multi-grid dielectric layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2751446Y true CN2751446Y (en) | 2006-01-11 |
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ID=35932612
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165437A (en) * | 2011-12-12 | 2013-06-19 | 无锡华润上华科技有限公司 | Gate-oxide etching method and multi-grid-electrode manufacturing method |
| CN103377934A (en) * | 2012-04-23 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device structure |
| CN105762179A (en) * | 2014-12-16 | 2016-07-13 | 北京有色金属研究总院 | Hafnium-based high-k gate dielectric stack structure and MOSFET device thereof |
| CN108695375A (en) * | 2017-04-10 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2004
- 2004-05-25 CN CN 200420059202 patent/CN2751446Y/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165437A (en) * | 2011-12-12 | 2013-06-19 | 无锡华润上华科技有限公司 | Gate-oxide etching method and multi-grid-electrode manufacturing method |
| CN103165437B (en) * | 2011-12-12 | 2016-06-29 | 无锡华润上华科技有限公司 | A kind of grid oxygen lithographic method and many grid making methods |
| CN103377934A (en) * | 2012-04-23 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device structure |
| CN103377934B (en) * | 2012-04-23 | 2016-08-24 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device structure |
| CN105762179A (en) * | 2014-12-16 | 2016-07-13 | 北京有色金属研究总院 | Hafnium-based high-k gate dielectric stack structure and MOSFET device thereof |
| CN108695375A (en) * | 2017-04-10 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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Expiration termination date: 20140525 Granted publication date: 20060111 |