CN105762179A - Hafnium-based high-k gate dielectric stack structure and MOSFET device thereof - Google Patents
Hafnium-based high-k gate dielectric stack structure and MOSFET device thereof Download PDFInfo
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- CN105762179A CN105762179A CN201410782187.5A CN201410782187A CN105762179A CN 105762179 A CN105762179 A CN 105762179A CN 201410782187 A CN201410782187 A CN 201410782187A CN 105762179 A CN105762179 A CN 105762179A
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Abstract
The present invention discloses a hafnium-based high-k gate dielectric stack structure and a MOSFET device thereof. The hafnium-based high-k gate dielectric stack structure comprises an interface transition layer, a hafnium-based high-k gate dielectric layer and a gate electrode which are orderly arranged on a silicon substrate and also comprises a back electrode arranged at the lower surface of the silicon substrate, wherein the hafnium-based high-k gate dielectric layer is a stack structure formed by doping hafnium oxide with a transition metal oxide. The semiconductor industrial standard process is employed, the hafnium oxide is doped by the transition metal oxide (M-O: TiO2, ZrO2), the gate dielectric film whose dielectric constant is higher than that of the hafnium oxide is obtained, lower EOT is realized in a same gate oxide thickness, and the hafnium-based gate dielectric stack structure with better comprehensive performance and MOSFET device thereof are prepared.
Description
Technical field
The present invention relates to the more excellent hafnio high k gate dielectric stack structure of a kind of combination property and MOSFET element thereof, belong to technical field of semiconductors.
Background technology
Follow " Moore's Law ", semi-conductor industry is just towards more high integration, low-power consumption development.Integrated level is more high, and the size of device is more little.Traditional gate dielectric material is dielectric constant is the SiO of 3.92, along with reducing of device size, SiO2The physical thickness of gate dielectric layer constantly reduces.At SiO2When physical thickness is less than 1nm, big leakage current, reducing further of restriction device size occur.From 45nm technology node, semicon industry adopts the dielectric constant high K thin film more than 3.9 to replace SiO2.The introducing of high-k gate dielectric, when identical EOT (equivalent oxide thickness), high-k gate dielectric physical thickness increases so that leakage current significantly reduces, and dimensions of semiconductor devices is reduced further.Wherein HfO2Thin film has high-k (16-20), good with Si integration, has been successfully applied to 45nm, 32nm, 22nm technology node.16/14nm technology node and technology node afterwards, it is desirable to gate dielectric membrane has the more combination property demand such as high-k, low-leakage current, reliability.Therefore, to HfO2Thin film carries out doping vario-property and improves the satisfied more advanced technology node requirement of performance, it has also become study hotspot.
Summary of the invention
It is an object of the invention to provide the more excellent hafnio high k gate dielectric stack structure of a kind of combination property and MOSFET element thereof.
For achieving the above object, the present invention is by the following technical solutions:
A kind of hafnio high k gate dielectric stack structure, including interface transition layer, hafnio high-k gate dielectric layer and gate electrode that surface on a silicon substrate sets gradually, and at the back electrode that silicon substrate lower surface is arranged, wherein hafnio high-k gate dielectric layer is the laminated construction formed by transition metal oxide doping hafnium oxide.
Wherein, described transition metal oxide is TiO2Or ZrO2.Transition metal oxide TiO2、ZrO2It is oxide of the same clan, wherein TiO with hafnium oxide2Dielectric constant up to 80, ZrO2There is higher dielectric constant 26 and the conduction band offset amount 1.4eV bigger with silicon energy level；A small amount of transition metal oxide TiO2Or ZrO2Mix the dielectric constant that can significantly improve thin film, under identical grid medium thickness reduce hafnio stack architecture EOT, improve reliability, for next-generation technology node provide high-k, stable hafnio high-k gate dielectric films.
Described hafnio high-k gate dielectric layer adopts prevailing technology ALD (technique for atomic layer deposition) deposition of quasiconductor film forming to form, for noncrystal membrane, stable performance.By regulating different cyclic deposition number of times and the order of transition metals Ti or zirconium source and hafnium source, carry out the adjustment of film doping concentration and membrane structure, prepare Hf-M-O gate dielectric membrane.Preferably, the doping of described transition metal oxide is 5%-20%, and the physical thickness of described hafnio high-k gate dielectric layer is 1-4nm.
Described interface transition layer is SiO2Layer, its thickness is not more than 1nm.Described back electrode is Ag or Al.Described silicon substrate is resistivity at the n-type silicon of 1-10 Ω cm or p-type silicon.Described gate electrode is one or more in TiN, TiAl, TaN, Pt, Ru and W.
The preparation method of described hafnio high k gate dielectric stack structure comprises the following steps:
(1) silicon substrate cleans, it is possible to adopt standard RCA technological process to be carried out；
(2) silicon substrate is prepared interface transition layer-SiO2Layer, it is possible to grow SiO by thermal oxide or its thin film deposition2Layer；
(3) ALD (technique for atomic layer deposition) is utilized to deposit the laminated construction of transition metal oxide and hafnium oxide；
(4) ALD or magnetron sputtering deposition gate electrode are utilized；
(5) utilizing ALD or magnetron sputtering to deposit coat of metal on gate electrode, thickness is 50-200nm；
(6) the hydrofluoric acid clean silicon substrate back side, magnetron sputtering back electrode are utilized.
Wherein, in step (1), silicon chip adopts standard RCA technological process to be carried out.After step (3), step (5), step (6), it is necessary to the annealing of different condition.
A kind of MOSFET element, including above-described hafnio high k gate dielectric stack structure, standard semiconductor 8 inches can being utilized to produce Wiring technology, prepare described hafnio high k gate dielectric stack structure and MOSFET source, drain electrode on SOI Substrate, the channel length of this MOSFET element is 20-50nm.
It is an advantage of the current invention that:
The present invention adopts semi-conductor industry standard technology, by transition metal oxide (M-O:TiO2、ZrO2) hafnium oxide is adulterated, obtain the dielectric constant gate dielectric membrane higher than hafnium oxide, under equal gate oxide thicknesses, realize less EOT, prepare the more excellent hafnio gate dielectric stack structure of combination property and its MOSFET element.
The hafnio high k gate dielectric stack structure dielectric constant of the present invention is bigger, and unfailing performance is better, simultaneously with the Hf-Ti-O device being gate medium and with same physical thickness HfO2MOSFET element performance for gate medium is similar, better performances.By transition metal oxide (TiO of the present invention2、ZrO2) to hafnium oxide base film doping vario-property, be expected to provide more excellent hafnio high-k gate dielectric films for generation semiconductor technology node.
Accompanying drawing explanation
Fig. 1 is the structure diagram of the hafnio high k gate dielectric stack structure of the present invention.
Fig. 2 is the preparation flow figure of the hafnio high k gate dielectric stack structure of the present invention.
Fig. 3 is the HfO of the embodiment of the present invention 1 preparation2High frequency voltage-electric capacity (C-V) curve chart of gate dielectric stack structure and QMCV matched curve figure.
Fig. 4 is high frequency voltage-electric capacity (C-V) curve chart and the QMCV matched curve figure of the Hf-Ti-O gate dielectric stack structure of the embodiment of the present invention 1 preparation.
Fig. 5 is the HfO of the embodiment of the present invention 1 preparation2, Hf-Ti-O gate dielectric stack structure breakdown voltage figure.
Fig. 6 is the HfO of the embodiment of the present invention 1 preparation2, Hf-Ti-O gate dielectric stack structure time breakdown figure.
Fig. 7 is the MOSFET structure sketch that the embodiment of the present invention 3 prepares the more excellent hafnio high-k gate dielectric of a kind of combination property.
Fig. 8 be the embodiment of the present invention 3 preparation respectively with HfO2, Hf-Ti-O be the PFET device Id-Vg curve chart of gate medium.
Detailed description of the invention
Below in conjunction with accompanying drawing, the present invention is further elaborated.
Fig. 1 is the structure diagram of hafnio high k gate dielectric stack structure of the present invention, including silicon substrate 104, interface transition layer 103 on silicon substrate 104, interface transition layer 103 hafnio high-k gate dielectric layer 102 deposited above, hafnio high-k gate dielectric layer 102 deposited above for gate electrode 101 and the back electrode 105 that deposits below substrate 104.
Such as the preparation flow figure of hafnio high k gate dielectric stack structure that Fig. 2 is the present invention, specifically include:
Step 201: the present invention uses resistivity at the n-type of 1-10 Ω cm or p-type silicon as substrate, adopts standard RAC technique to be carried out, substrate surface non-metallic ion after cleaning, organic impurities and silicon oxide.
Step 202: utilize O2、O3The SiO that the mode of thermal oxide generates at substrate silicon surface2Layer, as interface transition layer.
Step 203: utilize ALD deposition technology, at SiO2The high-k gate dielectric layer of interface transition layer deposition of titania doping hafnium oxide, depositing temperature is 300 DEG C.The concrete structure of hafnio high-k gate dielectric layer can be HfO2/M-O/HfO2Sandwich laminated construction, it is also possible to for HfO2, M-O multi-layer laminate structure.
Step 204: utilize ALD, magnetron sputtering to deposit top electrode on hafnio high-k gate dielectric layer.
Step 205: utilize the hydrofluoric acid clean substrate silicon back side, removes the SiO that substrate back produces in the above step2.Utilize ALD, magnetron sputtering technique, deposit back electrode at substrate back.
Standard is utilized partly to lead 8 inches of production technologies of industry, the MOSFET structure being gate medium with hafnio height K thin film.Fig. 7 is the MOSFET structure sketch of preparation on SOI Substrate, and the gate stack structures on Si is identical with Fig. 1's.SOI Substrate includes interface transition layer SiO2, hafnio high-k gate dielectric layer and gate electrode, simultaneously also active, drain electrode.
Embodiment 1
(1) preparing the gate dielectric stack structure that gate dielectric layer is Hf-Ti-O, idiographic flow is:
Step 201: the p-type silicon adopting standard RCA technique cleaning resistivity to be 8-12 Ω cm.
Step 202: dry foster thermal oxide SiO on substrate2Layer is as interface transition layer.
Step 203: depositing Hf-Ti-O interface transition layer surface A LD300 DEG C, its laminated construction is HfO2/TiO2/HfO2Sandwich structure, its TiO2Doping content is 10%.
Step 204: on Hf-Ti-O gate dielectric membrane, adopts ALD to grow W thick for TiN and 50nm thick for 3nm as top electrode, and wherein the area of top electrode is 100 μ m 100 μm.
Step 205: utilize the hydrofluoric acid clean substrate silicon back side, and adopt Al thick for magnetron sputtering deposition 700nm as back electrode.After having deposited, adopt 400 DEG C of N2And H2Annealing 20min makes back electrode alloying.
(2) preparing gate dielectric layer is HfO2Gate dielectric stack structure, the processing step according to above-mentioned (1), except the deposition HfO identical with Hf-Ti-O thickness in step 2032Gate dielectric layer, other process conditions are identical with (1).
Embodiment 2
The HfO obtained in testing example 1 respectively2The electric property of gate dielectric stack structure and Hf-Ti-O gate dielectric stack structure.
(1) utilize keithley4200 equipment, at probe station, probe is coupled with on back electrode and top electrode.Survey the TiO prepared by embodiment 12Doping content be 10% the C-V of Hf-Ti-O gate dielectric stack structure, I-V, breakdown voltage, breakdown time curve.Figure 30 1, Figure 40 1 respectively HfO2, Hf-Ti-O gate dielectric stack structure C-V curve.
(2) by using QMCV (matlab version) program matching, EOT and Δ Vfb data are extracted, such as Figure 30 2, Figure 40 2.HfO2Gate dielectric stack structure EOT=0.84nm, Δ Vfb=0.011V, Hf-Ti-O gate dielectric stack structure EOT=0.69nm, Δ Vfb=0.002V.
(3) Figure 50 1, Figure 50 2 respectively HfO2, Hf-Ti-O gate dielectric stack structure breakdown voltage figure.HfO2Stack architecture is when applying voltage V=-4V, and leakage current becomes big, and stack architecture lost efficacy；Hf-Ti-O stack architecture is when applying to suppress V≤-10V, and electric current is gradually increased, but stack architecture normal operation.
(4) Figure 60 1, Figure 60 2 respectively HfO2, Hf-Ti-O gate dielectric stack structure apply voltage be time breakdown figure during-2V.Hf-Ti-O stack architecture resistance to breakdown time is 3148.5s, hence it is evident that higher than HfO2The resistance to breakdown time 2369 of stack architectures。
As can be seen here, under equal gate oxide thicknesses, it is less that Hf-Ti-O gate dielectric stack structure has less EOT, C-V loop line width.Transition metal oxide TiO2Doping HfO2, successfully prepare the hafnio high k gate dielectric stack structure of a kind of lower EOT, more high-breakdown-voltage and resistance to breakdown time, its thin film is stable, and good combination property, providing for next-generation technology node can material selection.
Embodiment 3
Method according to embodiment 1, produces 8 cun of standards and prepares with HfO on line2, Hf-Ti-O be the PFET device of gate medium, its channel length Lg=25nm.Utilize keithley4200 device tester part performance, such as Fig. 8.With HfO2For the PFET device open-circuit current Ion=429uA/um of gate medium, pass electric current Ioff=3.2 × 1O-8A/um, on-off ratio Ion/Ioff=1.34 × 104, its saturation threshold voltage Vtsat=-0.17V, the reduction DIBL=56mV of the barrier height that drain terminal causes；With the Hf-Ti-O PFET device open-circuit current Ion=463uA/um being gate medium, close electric current Ioff=1.5 × 10-8A/um, on-off ratio Ion/Ioff=3.09 × 104, its saturation threshold voltage VtsAt=-0.16V, the reduction DIBL=53mV of the barrier height that drain terminal causes.
From test result it can be seen that TiO2The hafnio thin film of doping vario-property successfully reduces the EOT of stack architecture, and prepared device out have with HfO2For the performance that the device of gate medium is slightly excellent, there is good performance.Prove TiO of the present invention2Doping HfO2Thin film, hafnio film performance is optimized, and is expected to become the candidate materials of more excellent technology node.
Claims (10)
1. a hafnio high k gate dielectric stack structure, it is characterized in that, including interface transition layer, hafnio high-k gate dielectric layer and gate electrode that surface on a silicon substrate sets gradually, and at the back electrode that silicon substrate lower surface is arranged, wherein hafnio high-k gate dielectric layer is the laminated construction formed by transition metal oxide doping hafnium oxide.
2. hafnio high k gate dielectric stack structure according to claim 1, it is characterised in that described transition metal oxide is TiO2Or ZrO2。
3. hafnio high k gate dielectric stack structure according to claim 1 and 2, it is characterised in that described hafnio high-k gate dielectric layer adopts technique for atomic layer deposition deposition to form.
4. hafnio high k gate dielectric stack structure according to claim 1 and 2, it is characterised in that the doping of described transition metal oxide is 5%-20%.
5. hafnio high k gate dielectric stack structure according to claim 4, it is characterised in that the physical thickness of described hafnio high-k gate dielectric layer is 1-4nm.
6. hafnio high k gate dielectric stack structure according to claim 1 and 2, described interface transition layer is the SiO of thickness≤1nm2Layer.
7. hafnio high k gate dielectric stack structure according to claim 1, it is characterised in that described back electrode is Ag or Al.
8. hafnio high k gate dielectric stack structure according to claim 1, it is characterised in that described silicon substrate is resistivity at the n-type silicon of 1-10 Ω cm or p-type silicon.
9. hafnio high k gate dielectric stack structure according to claim 1, it is characterised in that described gate electrode is one or more in TiN, TiAl, TaN, Pt, Ru and W.
10. a MOSFET element, including the hafnio high k gate dielectric stack structure described in any one of claim 1-7.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2751446Y (en) * | 2004-05-25 | 2006-01-11 | 台湾积体电路制造股份有限公司 | Structure of multi-grid dielectric layer |
| CN1949532A (en) * | 2005-10-12 | 2007-04-18 | 财团法人工业技术研究院 | Semiconductor structure and mfg. method thereof |
| US20080029790A1 (en) * | 2006-08-03 | 2008-02-07 | Micron Technology, Inc. | ALD of silicon films on germanium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2751446Y (en) * | 2004-05-25 | 2006-01-11 | 台湾积体电路制造股份有限公司 | Structure of multi-grid dielectric layer |
| CN1949532A (en) * | 2005-10-12 | 2007-04-18 | 财团法人工业技术研究院 | Semiconductor structure and mfg. method thereof |
| US20080029790A1 (en) * | 2006-08-03 | 2008-02-07 | Micron Technology, Inc. | ALD of silicon films on germanium |
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