CN2746368Y

CN2746368Y - Intelligent collection monitoring device

Info

Publication number: CN2746368Y
Application number: CN 200420041974
Authority: CN
Inventors: 景敏卿; 周健; 高峰; 苏文军; 席晓鹏; 郭明杨; 侯成刚; 虞烈
Original assignee: Sichuan Vertical Instrument Co Ltd; Xian Jiaotong University
Current assignee: Sichuan Vertical Instrument Co Ltd; Xian Jiaotong University
Priority date: 2004-05-27
Filing date: 2004-05-27
Publication date: 2005-12-14
Anticipated expiration: 2014-05-27

Abstract

The utility model discloses a large-scale rotating machinery equipment which is an intelligent collection monitoring device. The device is formed by the connection of a signal gain adjustment and filtering module 1 and the input end of a signal null shift adjustment module 2, and the input end of an A/D converting module 5 is respectively connected with the output ends of a reference voltage module 3, a signal null shift adjustment module 2 and a control circuit 9. The output end of the control circuit 9 is respectively connected with the signal gain adjustment and filtering module 1, the signal null shift adjustment module 2, the A/D converting module 5 and the input end of a DSP handler 6, the output end of an extended memory of the DSP handler (10) is connected with the input end of the DSP handler 6, and the input end of a CPCI interface circuit 7 is connected with a CPCI bus. The output end of the CPCI interface circuit is connected with the DSP handler 6, a voltage module 4 is provided single current supply by the CPCI bus, and the output ends of the voltage module are connected with the input ends of power supplies corresponding to every functional module. The device can carry on real-time acquisition and disposal for monitor signals, thus meeting the requests of reliability, modularity, easy use and attention which are needed by the real-time environmental monitor for industries.

Description

A kind of intelligent acquisition monitoring device

Technical field

The utility model relates to the data acquisition and processing (DAP) field, relates in particular to a kind of intelligent acquisition monitoring device that is applied to the real-time working environment.

Background technology

On current data collection and process field and market, multiple monitoring device is arranged.Such as common monitoring device based on PCI (Peripheral Controller Interface, peripheral controller interface) bus commonly used etc., they can only satisfy civilian service condition.Some novel monitoring system has also adopted DSP (Digital Signal Processor, digital signal processor) processor in addition.Adopt common monitoring device based on pci bus mostly as: the real-time state monitoring of China's present stage large rotating machinery, this device is not only to using the field requirement height, and owing to there is not the real time signal processing ability, can not satisfy the real-time monitoring requirement of system.

The utility model content

The purpose of this utility model is to provide a kind of intelligent acquisition monitoring device that is applied to the real-time working environment.This device is applicable to signal collection in real time and processing based on CPCI (Compact Peripheral Controller Interface, compact periphery control unit interface) bus.As: to the rotating speed of large rotating machinery, vibration, the real-time intelligent monitoring of signals such as technology type.This device has guaranteed the static amount and the dynamic accuracy of measurement of acquired signal by signal is classified conditioning, amplification and anti-aliasing filtering.

The technical solution that realizes above-mentioned said intelligent acquisition monitoring device comprises signal gain adjusting and filtration module, signal drift adjustment module, reference voltage module, power module, analog/digital A/D modular converter, digital signal dsp processor, peripheral controllers CPCI interface circuit, control circuit, dsp processor extended memory, the signal input, wherein: signal gain adjusting and filtration module link to each other with the input end of signal drift adjustment module; Reference voltage module links to each other with the input end of signal drift adjustment module, and the input end of A/D modular converter links to each other with the output terminal of reference voltage, signal drift adjustment module, control circuit respectively; The output terminal of control circuit links to each other with the input end of signal gain adjusting and filtration module, signal drift adjustment module, A/D modular converter, dsp processor respectively, the output terminal of dsp processor extended memory links to each other with the input end of dsp processor, the input end of peripheral controllers CPCI interface circuit links to each other with cpci bus, and its output terminal links to each other with dsp processor; Signal input can be carried out 8 passages and imports synchronously, and every passage with respect to the differential input signal full range of 11 ranges is: ± 0.02V-± 20.0V, and its range can independently be provided with; , input signal frequency range is: 0HZ～50KHz.This device is by the single power supply of cpci bus, and carries out voltage transitions by power module 4, provides this to install the required various operating voltage of each functional module.

The realization of this device is based on the hardware device of cpci bus and dsp processor.The application of high-speed floating point type DSP makes this device can satisfy the real-time processing of image data; The application of cpci bus has been satisfied this device under industrial real time environment, necessary firm, reliable, modularization, intellectuality, easily uses and the requirement of easy care.

Description of drawings

Fig. 1 is that structure of the present utility model is formed block scheme;

Fig. 2 is theory of constitution figure of the present utility model;

Fig. 3 is the theory of constitution figure of signal drift adjustment module 2 of the present utility model;

Fig. 4 is the theory of constitution figure of reference voltage module 3 of the present utility model;

Fig. 5 is a profile of the present utility model mechanism front panel synoptic diagram;

Embodiment

The utility model is described in further detail below in conjunction with drawings and Examples.

Structure referring to Fig. 1 is formed block scheme, and consisting of of this device provides the signal input by signal input 11, and signal gain is regulated and filtration module 1 links to each other with the input end of signal drift adjustment module 2; Reference voltage module 3 links to each other with the input end of signal drift adjustment module 2, and the input end of A/D modular converter 5 links to each other with the output terminal of reference voltage module 3, signal drift adjustment module 2, control circuit 9 respectively; The output terminal of control circuit 9 regulates with signal gain respectively and the input end of filtration module 1, signal drift adjustment module 2, A/D modular converter 5, dsp processor 6 links to each other; The output terminal of dsp processor extended memory 10 links to each other with the input end of dsp processor 6; The input end of peripheral controllers CPCI interface circuit 7 links to each other with cpci bus, and its output terminal links to each other with dsp processor 6; Power module 4 by the single power supply of cpci bus (voltage is+12V), select for use linear power supply L1085, L7805, L7905, L7809, L7909 through voltage transitions, its output terminal links to each other with the corresponding power input of each functional module.

Fig. 2 is and the pairing circuit theory synoptic diagram of Fig. 1.

Signal gain is regulated and filtration module 1 is regulated by signal gain and low pass signal filtering constitutes, its input end links to each other with input signal Si gnal, present embodiment is selected for use programmable gain amplifier PGA205 and programmable gain amplifier PGA103 to carry out signal gain and is regulated, and is made of PGA205 and PGA103 cascade; The gain of PGA205 (* 1,2,4,8) is by its pin A0, and A1 determines, the gain of PGA103 (* 1,10,100) is by its pin A2, and A3 determines, signal gain is regulated and the pin A0 of filtration module 1, A1, A2, A3 and corresponding output terminal connection by the TPIC6B595 in the control circuit 9; Low pass signal filtering is made of 4 rank low-pass filter TLC14, and its cutoff frequency equals and the input clock signal frequency, and its input clock signal end connects with corresponding output terminal by the TPIC6B595 in the control circuit 9; The input end of TLC14 is connected with the output terminal of PGA205, and the input disconnection of its output terminal and signal drift adjustment module 2 connects.

Referring to Fig. 3, signal drift adjustment module 2 is mainly used in to be revised the drift of input signal, and it is mainly formed by follower circuit 14 and adder circuit 15 cascades that operational amplifier OP07C constitutes.The input end of follower circuit 14 regulates with signal gain and the output terminal of filtration module 1 links to each other, the input end of adder circuit 15 links to each other with the output terminal of follower circuit 14, the output terminal of TLC5628C in the control circuit 9 respectively, the output terminal of TLC5628C in the control circuit 9 provides error compensation by adder circuit 15 for the drift of signal, and the output terminal of signal drift adjustment module 2 links to each other with the signal input part of the ADS8322 of A/D modular converter 5.

With reference to the reference voltage module theory of constitution figure of Fig. 4, the input end of reference voltage module 3 and A/D conversion chip reference voltage (+2.5V) output terminal links to each other, with its transfer to reference voltage (+2.5V ,-2.5V) output, and provide enough output powers.The follower circuit 12 that reference voltage module 3 is made of operational amplifier OP07C provide reference voltage circuit (+2.5V), calculator circuit 13 by cascade provides reference voltage (2.5V) again, the input end of reference voltage module 3 links to each other with the reference voltage output terminal Refout of A/D modular converter 5, and its output terminal links to each other with the reference voltage input terminal Ref of signal gain and filtering adjustment module 1, A/D modular converter 5, control circuit 9 respectively.(it specifically implements circuit as shown in Figure 3).

According to shown in Figure 2, A/D modular converter 5 is made of A/D conversion chip ADS8322, its signal positive input terminal links to each other with the output terminal of signal drift adjustment module 2, the signal negative input end links to each other with ground, its control signal: CLK (clock signal), CVT (Convert Start, the conversion beginning), BYTE (data-bus width), CS (Chip Select, sheet choosing) input end respectively with control circuit 9 in CPLD (ComplexProgrammable Logic Device, CPLD) output terminal of chip EP20K100EQC240-3 correspondence links to each other, its data line D _0.7Link to each other with the data line of data buffer 74AHC574 in the control circuit 9.

Dsp processor 6 shown in Figure 2 is TMS320C6711BGFN, and it is signal analysis, the processing enter of this system.Dsp processor extended memory 10 is for it provides storage space, and dsp processor extended memory 10 provides program's memory space by FLAS storer MX29LV040QC, and HY57V28820HCT provides data space by the DRAM storer.The fpga chip EP20K100EQC240-3 of control circuit 9 also provides data space, is used to store the A/D translation data.The data line D of dsp processor 6 _0.15With address wire A _0.20Respectively be connected corresponding of data line of control circuit 9, dsp processor extended memory 10, CPCI interface circuit 7 with address wire, its control signal C/BE _0.3(Byte Enable, byte enable), CS (Chip Select, the sheet choosing), RD (Read, read), WR (Write, write), OE (OutputEnabled, output enable), RDY (Ready, ready) output terminal is connected with the input end of control circuit 9, dsp processor extended memory 10, compact periphery controller CPCI interface circuit 7 respectively.INT4 (the Interrupt of dsp processor 6, interruption), INT5, INT6 signal input part are connected with the output terminal of control circuit 9, for dsp processor provides look-at-me, RST (the Reset of dsp processor 6, resetting) signal input part is connected with the output terminal of control circuit 9, for dsp processor provides hardware reset signal.

According to shown in Figure 2, compact periphery controller CPCI interface circuit 7 is chip PCI2040PGE, and a CPCI interface is provided between cpci bus and digital sampling and processing.Its 32 position datawires link to each other with cpci bus, its control signal C/BE _0.3(Byte Enable, byte enable), PCLK (clock signal), PRST (reset signal) input end link to each other its data output end GPIO with the control signal output ends of CPCI _0.5Link to each other with the data input pin of control circuit 9.16 of CPCI interface circuit 7 is that data line links to each other with the data line of dsp processor 6.Control circuit 9 is by fpga chip EP20K100EQC240-3, serial D/A (Digital/Analog) chip TPIC6B595, TLC5628C, and data buffer 74AHC574 forms.The control signal OE of EP20K100EQC240-3 chip, CLK output terminal and data line are connected with the corresponding input end of 74AHC574, are used for the touring 8 passage A/D translation data that receive.Its serial ports output terminal links to each other with the serial ports input end of serial D/A chip TPIC6B595, TLC5628C.TPIC6B595 is used for the control of signal gain amplifier, and its output terminal is regulated with signal gain, the input end of filtering 1 links to each other; TLC5628C is used for the control that the signal drift is regulated, and it links to each other with input end in the signal drift adjustment module 2.The input end of control circuit 9 links to each other with external timing signal ExtClk with outer triggering signal ExtTrg.Its output terminal and power light Lamp1 gather run indicator Lamp2 and link to each other simultaneously, are used to control and show the duty of this device.Its GPIO _0.5The GPIO of (General-purpose Input/Output, general I/O port) input end and CPCI interface circuit 7 _0.5Output terminal is connected.

With reference to shown in Figure 5, power light, operation indication, signal incoming end are arranged on the front panel of this device, and external trigger, external clock incoming end.Each symbolic representation is as follows:

CH1, CH2, CH3, CH4, CH5, CH6, each channel signal input end of CH7, CH8 all add signal with the Q9 signal wire

EXT TRG external trigger input end; EXT CLK external clock input end.

The utility model intelligent monitoring device utilizes the high reliability of cpci bus and the high-speed cruising of dsp processor, by monitored signal is classified, the real-time high-efficiency buffer memory and the transmission of conditioning, amplification, anti-aliasing filtering, synchronous high-speed A/D conversion, data, for intelligent monitoring device provides at a high speed, hardware supported reliably.

Guarantee the static amount and the dynamic accuracy of measurement of acquired signal in the utility model by conditioning that signal is classified, amplification, anti-aliasing filtering.Monitoring device adopts the ADS8322 chip of 8 TI (Texas Instruments) company, each passage independent parallel is gathered, convert 8 channel analog signals to 8 channel digital signals synchronously, send into dsp processor and carry out real time data analysis and processing, the highest inversion frequency of every passage is 100KHz, has guaranteed the synchronous high-speed collection of each channel signal.Every passage differential input signal full range is ± 0.02V-± 20.0V that its range can independently be provided with; DAC (Digital/Analog Current, the digital-to-analog electric current) output of every channel signal all stackable 12Bit of input (position) with respect to 11 range DAC output areas be ± 0.01V-± 20.0V, and various places passage DAC can independently be provided with; The drift of every passage and gain are carried out coarse adjustment and fine tuning by two 8 D/A conversion chips respectively, and the precision of fine tuning is better than 0.01% of range ability,

Dsp processor has been selected the dsp chip TMS320C6711B of TI (Texas Instruments, Texas Instruments) company for use.It is a kind of high-speed floating point type DSP, and speed is applicable to data operation soon, and power consumption is extremely low, and cost performance is higher, and exploitation is convenient, and technical grade product is arranged.Work dominant frequency 150MHz, instruction cycle 900M Mps/S.There is the 64Kbyte high-speed SRAM TMS320C6711 inside, outside expansion 64Mbyte high speed SDRAM.

The scope of acquired signal :+20V in the utility model～-20V; 0HZ～50KHz.Can carry out 8 passage synchronous acquisition, monitoring to signals such as rotating speed, vibration, speed, technologies.

The utility model adopts high-speed dsp processor and cpci bus, and monitor signal is finished real-time collection and processing, has satisfied industrial real time environment and has used necessary firm, reliable, modularization, easily uses and the requirement of easy care.In the on-line condition monitoring and fault diagnosis of large rotating machinery equipment, realized the real-time collection and the processing of monitoring of equipment data, satisfied the monitoring requirement of industry spot.

Claims

1, a kind of intelligent acquisition monitoring device comprises signal gain adjusting and filtration module (1), signal drift adjustment module (2), and it is characterized in that: signal gain is regulated and filtration module (1) links to each other with the input end of signal drift adjustment module (2); Reference voltage module (3) links to each other with the input end of signal drift adjustment module (2), and the input end of A/D modular converter (5) links to each other with the output terminal of reference voltage (3), signal drift adjustment module (2), control circuit (9) respectively; The output terminal of control circuit (9) regulates with signal gain respectively and the input end of filtration module (1), signal drift adjustment module (2), A/D modular converter (5), dsp processor (6) links to each other, the output terminal of dsp processor extended memory (10) links to each other with the input end of dsp processor (6), the input end of peripheral controllers CPCI interface circuit (7) links to each other with cpci bus, and its output terminal links to each other with dsp processor (6).

2, intelligent acquisition monitoring device according to claim 1, it is characterized in that: described signal input (11) can be carried out 8 passages and import synchronously, every passage with respect to the differential input signal full range of 11 ranges is: ± 0.02V-± 20.0V, and its range can independently be provided with; , input signal frequency range is: 0HZ～50KHz.

3, intelligent acquisition monitoring device according to claim 1 is characterized in that: this device is by the single power supply of cpci bus, and carries out voltage transitions by power module (4), provides this to install the required various operating voltage of each functional module.