The utility model content
The purpose of this utility model is: at the deficiencies in the prior art, provide a kind of simple in structure, can reduce the data link data traffic, alleviate the intelligent multi-serial port bridge of the work load of the equipment on the link.
In order to solve the problems of the technologies described above, technical solution adopted in the utility model is: a kind of intelligent multi-serial port bridge, comprise the PORT COM expansion module that has the descending serial port of many groups, also comprise storage forwarding control module and route data table memory module, described storage is transmitted control module and is had up serial port, with with upper device talk, described storage transmit control module also link road by the data table stores module, with the data memory route, or in route data table memory module, read in the data route, realize and be connected to the point-to-point communication of the next equipment of descending serial port.
Described storage is transmitted control module can comprise single-chip microcomputer, address decoding circuitry, described single-chip microcomputer has 1 up serial port, and its port also forms the bus system of being made up of data/address bus, address bus and control bus respectively, thereby be connected with other module by described bus system, the input of described address decoding circuitry is from the address date of single-chip microcomputer address bus, and exports enable signal corresponding to other module respectively to control bus.
Described route data table memory module can adopt nonvolatile storage, the address end link address bus of described nonvolatile storage, and its data terminal connects data/address bus, and its control end connects control bus.
Described PORT COM expansion module can comprise universal asynchronous serialization controller and communication interface drive circuit, described universal asynchronous serialization controller has the descending serial port of many groups, and described descending serial port all is connected the next equipment or upper equipment by the communication interface drive circuit with the up serial port that storage is transmitted control module.
In technique scheme, the utility model transmits control module by storage and route data table memory module cooperates the PORT COM expansion module that has the descending serial port of many groups, thereby data memory route automatically, changing traditional broadcast type communication mode is point-to-point data communication pattern, effectively reduce the data traffic on the data link, solved the puzzlement of network blockage, made communication more smoothly, fast, reliably.In addition, because transmitting control module, storage has the serial port of uploading, the data of upper equipment are directly imported single-chip microcomputer, thereby make storage transmit control module and can directly carry out data parsing, thereby making other the next equipment can no longer make data resolves, reduced the work load of the next equipment, made in the data link Task Distribution of each equipment more reasonable, thereby also can improve data transmission bauds and efficient.
Embodiment
Below in conjunction with Figure of description and specific embodiment the utility model is described in further detail.
With reference to the accompanying drawings 3, a kind of intelligent multi-serial port bridge is transmitted control module and route data table memory modules constitute by the PORT COM expansion module that has the descending serial port of many groups, storage.Described storage is transmitted control module and is had up serial port, with with upper device talk, described storage transmit control module also link road by the data table stores module, with the data memory route, or in route data table memory module, read in the data route, realize and be connected to the point-to-point communication of the next equipment of descending serial port.
Accompanying drawing 4,5 provides the circuit block diagram and the circuit theory diagrams of a kind of preferred embodiment of the present utility model.
With reference to the accompanying drawings 4, described storage is transmitted control module and is comprised single-chip microcomputer, address decoding circuitry.
Described single-chip microcomputer has 1 up serial port, and its port also forms the bus system of being made up of data/address bus, address bus and control bus respectively, thereby is connected with other module by described bus system.Wherein, what data/address bus transmitted is data-signal, and data can be provided or be provided by external equipment by single-chip microcomputer, specifically is to be realized by control bus control by single-chip microcomputer; Address bus provides the external device address that receives or send data; Control bus provides these data and is provided by single-chip microcomputer or provided by external equipment, data type, information such as this signal is when effective, and other various controlled function.In this design, mainly used the bus-type external equipment, model commonly used has 89C52, DS80C320 etc.
The input of described address decoding circuitry is used for the multiplexing address/data-signal of CPU output from the address date of single-chip microcomputer address bus, and independent separate is come out, and exports enable signal corresponding to other module respectively to control bus.Model commonly used is that chips such as 74LS138,74LS139,16V8,20V8 constitute.
Described storage is transmitted control module and is also comprised the program storage that is used to store the random asccess memory of ephemeral data and is used for the storage running program, their data terminal is connected data/address bus and address bus respectively with the address end, and their reading and writing control end is respectively by control bus input reading and writing signal.Wherein program storage is used to store compiled working procedure, can not online modification.Random asccess memory is used for the ephemeral data of memory device run duration, and work such as common data operation, processing are all finished in this chip.
Described route data table memory module adopts nonvolatile storage, the address end link address bus of described nonvolatile storage, and its data terminal connects data/address bus, and its control end connects control bus.Because nonvolatile storage is during equipment work, data can write, data keep not losing (no matter normal shutdown or abnormal power-down) after device powers down, at work, CPU transfers to the data that needs are preserved in the nonvolatile storage from random asccess memory at any time, so, various data record, data etc. are set, all are kept in the nonvolatile storage.
When bridge when up serial port is received the data that upper level equipment sends, carry out data analysis, judge at first whether these data are the valid data of native system.If non-native system data are directly lost; If the valid data of native system, then check whether be instruction or the data that monitoring host computer sends, or the data sent of other collecting devices.If instruction that monitoring host computer sends or data, check the routing table that is stored in the route data table memory, check that whether Already in this data address in the routing table, if this data address is arranged in the routing table, port by this place, address sends immediately, realizes point-to-point sending mode; If this data address not in the routing table, send to whole port broadcast types immediately, when return from a certain port contain the address device data after, automatically the routing iinformation of this address is charged in the nonvolatile storage, send later the data of this address again, no longer broadcast type sends, but point-to-point transmission; If broadcast type sends more than the several times, do not return and contain the address device data, then suspend the data that send this address, wait for the some time after, again this address is tested again.So the routing table in the route data table memory is the data that dynamically update, upgrade at any time and write in the nonvolatile storage, normally close bridge, or because abnormal cause closing device (having a power failure as accident), these data are not still lost.
Comparison diagram 2 and Fig. 3 can very clearly find out, the utility model can significantly reduce the data traffic on the data link, thereby can overcome in the prior art defective such as network data is stopped up, transfer of data is lost easily or make mistakes, the next equipment task is heavy, transmission speed slow, system works efficient is low.
Described PORT COM expansion module comprises universal asynchronous serialization controller and communication interface drive circuit, described universal asynchronous serialization controller is used for the parallel bus signal of CPU is converted into the general serial signal, as RS232 mode etc., realize bridge function for single-chip microcomputer expanding universal COM port, it has the descending serial port of many groups.Described communication interface drive circuit is used for Transistor-Transistor Logic level is changed into the RS232 level, can improve antijamming capability like this, is fit to be transferred to place (being generally 15 meters) far away a little.Described descending serial port all is connected the next equipment or upper equipment by the communication interface drive circuit with the up serial port that storage is transmitted control module.
The concrete circuit theory diagrams of accompanying drawing 5 present embodiments.Wherein, the model of described single-chip microcomputer D1 is DS80C320, and the model of described nonvolatile storage D10 is AT28C256, and the model of the universal asynchronous serialization controller D8 of described four-way is TL16C554.
Data/address bus D0~D7 that the P0 interruption-forming of described single-chip microcomputer D1 is 8, its P2 mouth is that the data latches D2 of 74LS373 forms address bus A0~A15 of 16 with model, the most-significant byte of P2 mouth OPADD bus wherein, the input of data latches D2 connects the P0 mouth, the least-significant byte of its output OPADD bus, the RD of described single-chip microcomputer D1, WR end is exported the reading and writing signal respectively to control bus, its RXD, TXD end is one group of up serial port, and its P12, P13 end forms one group of descending serial port.
Described address decoding circuitry is that GAL20V8 address decoder D5 and peripheral component thereof constitute by model, the input of described address decoder D5 is respectively by address bus Input Address signal A8~A15, and by control bus input reading and writing signal, from the ale signal and the PSEN signal of single-chip microcomputer, its output is exported universal asynchronous serialization controller control signal CSA~CSD, random asccess memory gating signal CS62 and nonvolatile storage gating signal CS28 respectively.
It is the universal asynchronous serialization controller D8 of four-way of TL16C554 that described universal asynchronous serialization controller adopts model, data terminal D0~D7 of the universal asynchronous serialization controller D8 of described four-way connects data/address bus, A0~A1 on its address end A0~A1 link address bus, its control end CSA~CSD input is from the universal asynchronous serialization controller control signal CSA~CSD of address decoding circuitry, its IOW end is by control bus input write signal WR, its IOR end is by control bus input read signal RD, and its RXA, TXA~RXD, TXD end are respectively four groups of descending serial ports.
It is the serial ports level translator D3 of MAX232 that described communication interface drive circuit adopts model, D6, D9 and peripheral component thereof constitute, their (R1 IN), (R2 IN0 end receives the data from upper equipment and the next equipment respectively, their (R1 OUT), the then corresponding output received signal of (R2 OUT) end is to signal receiving end and the descending serial port of single-chip microcomputer D1 and the signal receiving end of up serial port of the four tunnel descending serial ports of the universal asynchronous serialization controller D8 of four-way, their (T1 IN), (T2 IN) end connects described each the descending serial port of the universal asynchronous serialization controller D8 of four-way and the signal sending end of up serial port, their (T1OUT) respectively, the corresponding dateout of (T2 OUT) end difference is to the next equipment and upper equipment.