CN2711906Y - Multi-chip IC package structure - Google Patents
Multi-chip IC package structure Download PDFInfo
- Publication number
- CN2711906Y CN2711906Y CNU2004200196998U CN200420019699U CN2711906Y CN 2711906 Y CN2711906 Y CN 2711906Y CN U2004200196998 U CNU2004200196998 U CN U2004200196998U CN 200420019699 U CN200420019699 U CN 200420019699U CN 2711906 Y CN2711906 Y CN 2711906Y
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- silicon chip
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a multi-chip integrated circuit packaging structure, which comprises a plurality of chips, a base plate and a metal pin frame, wherein, the base plate adopts a silicon chip base plate which is provided with wirings, the chips of which are connected with each other, and the silicon chip base plate is arranged in the metal pin frame. A plurality of chips are arranged on the silicon chip base plate, the chips are connected with each other by a gold thread, the chips are connected with the silicon chip base plate by the gold thread, and the silicon chip base plate is also connected with the metal pin frame by the gold thread. The chips, the silicon chip base plate and the metal pin frame are integrated by the packaging of plastic packaging materials. The multi-chip integrated circuit packaging structure breaks through the present status that a plurality of chips only can adopt a ball grid array packaging form in system packaging, so that the multi-chip integrated circuit packaging structure realizes the metal pin packaging form. Meanwhile, the utility model reduces the packaging cost and the requirement of the manufacturing technology of the base plate, and also smartly widens the function of the multi-chip integrated circuit after packaging.
Description
Technical field
The utility model relates to the encapsulation of integrated circuit (IC) chip, more specifically refers to a kind of multichip IC encapsulating structure.
Background technology
At present, in to the integrated circuit (IC) chip encapsulation, a plurality of bare chips are interconnected as system, and " system in package (the SIP) " scheme that is assembled in the single encapsulation comes into one's own day by day.Though " SOC (system on a chip) (SOC) " scheme can and be manufactured on the single nude film a plurality of chip functions designs, have " system in package (SIP) " too in the advantage that provides aspect circuit board packing density and the reliability, but compare with " system in package (SIP) ", " SOC (system on a chip) (SOC) " scheme exists the design cycle long, research and development expense height, be difficult to circuit integrated limitations of entering such as high frequency, high pressure, therefore " system in package (SIP) " must not develop rapidly owing to there is not above shortcoming.
" system in package " be integrated with mostly CPU, ' a plurality of functions such as RAM, ROM, I/O, the complicated interconnection in the system between the multicore sheet must realize by substrate, the printed circuit board (PCB) of the effect of substrate and common installation electronic devices and components is identical.
In chip-packaging structure, the substrate of " system in package " all adopts glass epoxy printed board so far, and just littler, thinner than common printed substrate, it is meticulousr to connect up.In existing tens of kinds of encapsulation technologies commonly used, be broadly divided into two classes:
The first kind is to adopt the structure of metal (copper, nickel) nead frame, as DIP, TSOP, QFP, PLCC etc., this class formation, with the metal pins framework as chip carrier, chip 1 links by gold thread 2 and metal pins framework 3 and outwards draws (see figure 1), and capsulation material 4 is with its sealing.
Second class is to adopt the structure of nonmetal pin, as ball grid array (BGA), as chip carrier, chip 1 links to each other with printed substrate 5 by gold thread 2 this class formation with miniature printed wiring board, and draw (see figure 2) by the soldered ball 6 of bottom, and with capsulation material 4 with its sealing.Its advantage is to draw soldered ball to be distributed on the floor space, can only draw on side with frame pin and compare, and has the density height, size is little, can arrange a large amount of pins.
In the encapsulation of multicore sheet,, can only place silicon chip on the metal framework, and not allow to place miniature printed wiring board for the restriction of temperature coefficient match.Therefore " system in package " is interconnect substrates owing to adopting miniature printed wiring board so far, and (1 is chip among Fig. 4, and 2 is the gold thread that connects just to have only employing ball grid array (BGA) packing forms, 5 is printed substrate, 6 is soldered ball, and 4 is capsulation material), and do not allow to adopt the metal pins packing forms.This has just limited to the range of application of " system in package " chip, and its limitation is that the complete system plant that much can assemble the metal pins chip does not have equipment and the ability that the chip that adopts BGA Package is installed; Simultaneously a large amount of low side electronic products does not wish to adopt the chip of BGA Package for the consideration that reduces packing density, chip cost and manufacturing technique requirent yet.How to solve the problems referred to above that exist in the encapsulation of multicore sheet, perplexing the people in the industry always.
Summary of the invention
The purpose of this utility model be at multicore sheet encapsulation exist above-mentioned all to adopt miniature printed wiring board be substrate, can only realize the problem of BGA Package, a kind of multichip IC encapsulating structure is proposed, so that the integrated circuit scope of application after the encapsulation of multicore sheet is more wide.
To achieve these goals, the utility model adopts following technical scheme:
This multichip IC encapsulating structure comprises a plurality of chips, substrate, metal pins framework, and described substrate adopts the silicon chip substrate and at the silicon chip substrate wiring of chip interconnect is set, and the silicon chip substrate places in the metal pins framework; Described a plurality of chip places on the silicon chip substrate, between chip and the chip, be connected by gold thread between chip and the silicon chip substrate; Also be connected between silicon chip substrate and the metal pins framework by gold thread; A plurality of chips, silicon chip substrate, metal pins framework encapsulate one-body molded by capsulation material.
In technique scheme of the present utility model, this multichip IC encapsulating structure comprises a plurality of chips, substrate, metal pins framework, described substrate adopts the silicon chip substrate and at the silicon chip substrate wiring of chip interconnect is set, and the silicon chip substrate places in the metal pins framework; Described a plurality of chip places on the silicon chip substrate, between chip and the chip, be connected by gold thread between chip and the silicon chip substrate; Also be connected between silicon chip substrate and the metal pins framework by gold thread; A plurality of chips, silicon chip substrate, metal pins framework encapsulate one-body molded by capsulation material.This multichip IC encapsulating structure adopts ball grid array package structure to compare with tradition, has the following advantages:
1, broken through the multicore sheet and can only adopt the present situation of BGA Package form, realized the packing forms of metal pins in system in package.
2, also greatly reduce manufacturing technique requirent to substrate.
3, adopt silicon chip to make substrate and can realize the unapproachable more complicated system interconnection of printed substrate.
4, adopt silicon chip will use printed substrate as the substrate cost far below routine as the cost of substrate.
5, widened the function of the multichip IC after the encapsulation neatly by increasing the mask number of plies.
Description of drawings
Fig. 1 a and Fig. 1 b are respectively conventional metals nead frame single-chip package structure and analyse and observe and elevational schematic view.
The ball grid array single-chip package structure that Fig. 2 a and Fig. 2 b are respectively traditional is analysed and observe and elevational schematic view.
Fig. 3 is traditional ball grid array multichip packaging structure cross-sectional schematic.
Fig. 4 is the encapsulating structure cross-sectional schematic of multicore sheet of the present utility model.
Embodiment
Multichip IC encapsulating structure of the present utility model sees also shown in Figure 5, in this structure, comprise a plurality of chips 1, metal pins framework 3, capsulation material 4, substrate 7, described substrate 7 adopts the silicon chip substrate and the wiring of chip interconnect is set on silicon chip substrate 7, and silicon chip substrate 7 places in the metal pins framework 3; Described a plurality of chip 1 places on the silicon chip substrate 7, is connected by gold thread 2 between chip 1 and the silicon chip substrate 7; Also be connected between silicon chip substrate 7 and the metal pins framework 3 by gold thread 2; A plurality of chips 1, silicon chip substrate 7, metal pins framework 3 encapsulate one-body molded by capsulation material 4.
Described a plurality of chip 1 is one deck or which floor is stacked and placed on the silicon chip substrate 7.
When a plurality of chips stacked on the silicon chip substrate 7 are one deck, interconnect by gold thread with the chip 1 of one deck, or chip 1 is connected on the silicon chip substrate 7 by gold thread 2;
When a plurality of chips 1 stacked on the silicon chip substrate 7 stack to which floor, last layer chip 1 adopt gold thread 2 to be connected on the silicon chip substrate 7 or the chip 1 of lower floor on.
The advantage of the utility model said structure is described below:
Adopt the substrate of silicon chip, thereby make " system in package " break through the present situation that can only adopt the BGA Package form, realized the packing forms of metal pins as " system in package ".
Adopt silicon chip as substrate, not only make " system in package " to realize the metal pins packing forms, also greatly reduce manufacturing technique requirent substrate.In fact the miniature printed wiring board that substrate adopts at present belongs to identical technology and technology with the circuit board of common installation electronic devices and components, live width that its common process can be accomplished and line-spacing are 4 Mills (100um), and substrate is below 3 Mills (75um) to the requirement of live width and line-spacing, the technological limits that has surpassed printed substrate, therefore its cost and technology difficulty have all increased greatly, and its cost will account for the 40%-50% of BGA Package total cost usually.And live width that the silicon chip common process can be accomplished and line-spacing are that 0.6urn (6 cun wafers) is to 1.2um (4 cun wafers), even the silicon wafer-based printed line is wide and the density of line-spacing has improved 50 demultiplications to 1.5um than printed substrate, great technology affluence degree is also arranged, so can guarantee high qualification rate easily.Because the wiring density of silicon chip improves more than 50 times than printed substrate, therefore adopt silicon chip to make substrate and can realize the unapproachable more complicated system interconnection of printed substrate simultaneously.
Aspect the substrate cost; to be higher than printed substrate though it is generally acknowledged silicon chip unit are cost; but in fact; the substrate that Chip Packaging is used; miniature printed wiring board cost will be far above conventional printed substrate; adopting silicon chip to do the cost of substrate simultaneously will be far below custom integrated circuit; chip cost is to increase progressively according to the number of plies that adds the mask in man-hour; for the substrate silicon chip; only need two-layer wiring; comprise that interlayer metal via hole and protective layer only need 4 layers of mask to get final product, the silicon chip that therefore is used for substrate is cheaply more over half than miniature printed wiring board reality.When this external substrate cost allows, can increase functional substrate neatly by increasing the mask number of plies, as adding resistance, simple logic or high voltage conversion etc.
In order to be illustrated more clearly in both difference, also can consult following table, to carry out the performance comparison after substrate adopts miniature printed wiring board respectively and adopts silicon chip:
| Substrate | The metal pins encapsulation | Common process | The requirement of substrate actual process | Technology difficulty | Wiring density | Cost | Increase function |
| Printed substrate | NO | 100um | 75um | Difficult | Low | High | NO |
| Silicon chip | YES | 0.6um | 1.5um | Easily | High | Low | YES |
In concrete encapsulating structure, known to aforementioned, the annexation that stacks altogether on the silicon chip substrate between what layer chip, each layer how much chip of placement and the chip is decided on the concrete integrated circuit of required making.In embodiment illustrated in Figure 5, stacked two layers of chip on the silicon chip substrate altogether, the last layer chip has three, and one deck adjacent with substrate has two, and one deck chip adjacent with the silicon chip substrate all has gold thread to be connected on the silicon chip substrate separately.Interconnect earlier between three chip blocks of last layer, and then be connected on the substrate with gold thread.Can understand at an easy rate, the encapsulating structure of different integrated circuits should comprise the chip of different function and quantity, and chip is stacked in the number of plies on the silicon chip substrate and the annexation between each chip.
The main core of the utility model is to adopt silicon chip to carry various chips as substrate and encapsulate.When concrete encapsulation, can adopt following encapsulation step:
A adopts the carrier of metal pins framework as the encapsulation of multicore sheet;
B, adopt silicon chip as substrate forming the silicon chip substrate, and the wiring of chip interconnect is set on the silicon chip substrate;
C puts the silicon chip substrate on the metal pins framework;
D stacks a plurality of chips that will encapsulate on the silicon chip substrate;
E adopts the gold threads interconnection with a plurality of chips that will encapsulate or is connected on the silicon chip substrate;
F is connected the silicon chip substrate with gold thread again with the metal pins framework;
G, with chip, silicon chip substrate, metal pins framework plastic packaging in one.
In the described steps d, when on the silicon chip substrate, stacking a plurality of chip, a plurality of chips can be stacked one deck or which floor.
When a plurality of chips that stack on the silicon chip substrate stack to one deck, will interconnect with gold thread with the chip of one deck, or chip is being connected on the silicon chip substrate with gold thread;
When a plurality of chips that stack on the silicon chip substrate stacked to which floor, the last layer chip all adopted gold thread to be connected on the silicon chip substrate or on the chip of lower floor.
The annexation that stacks altogether on the silicon chip substrate between what layer chip, each layer how much chip of placement and the chip is decided on the concrete integrated circuit of required making.Chip all will be received on the silicon chip substrate after connecting, and then by gold thread silicon chip substrate and metal pins framework is coupled together but in general.
Those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the utility model, and be not to be used as qualification of the present utility model, as long as in connotation scope of the present utility model, all will drop in the scope of the utility model claims variation, the modification of the above embodiment.
Claims (3)
1, a kind of multichip IC encapsulating structure, this encapsulating structure comprises a plurality of chips, substrate, metal pins framework, it is characterized in that:
Described substrate adopts the silicon chip substrate and at the silicon chip substrate wiring of chip interconnect is set, and the silicon chip substrate places in the metal pins framework; Described a plurality of chip places on the silicon chip substrate, between chip and the chip, be connected by gold thread between chip and the silicon chip substrate; Also be connected between silicon chip substrate and the metal pins framework by gold thread; Described a plurality of chip, silicon chip substrate, metal pins framework encapsulate one-body molded by capsulation material.
2, multichip IC encapsulating structure as claimed in claim 2 is characterized in that: described a plurality of chips are one deck or which floor is stacked and placed on the silicon chip substrate.
3, multichip IC encapsulating structure as claimed in claim 1 or 2 is characterized in that:
When a plurality of chips stacked on the silicon chip substrate are one deck, interconnect by gold thread with the chip of one deck, or chip is connected on the silicon chip substrate by gold thread;
When a plurality of chips stacked on the silicon chip substrate stacked to which floor, the last layer chip all adopted gold thread to be connected on the silicon chip substrate or on the chip of lower floor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2004200196998U CN2711906Y (en) | 2004-01-19 | 2004-01-19 | Multi-chip IC package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2004200196998U CN2711906Y (en) | 2004-01-19 | 2004-01-19 | Multi-chip IC package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2711906Y true CN2711906Y (en) | 2005-07-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2004200196998U Expired - Lifetime CN2711906Y (en) | 2004-01-19 | 2004-01-19 | Multi-chip IC package structure |
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| Country | Link |
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| CN (1) | CN2711906Y (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074541A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof |
| CN101677092B (en) * | 2008-09-18 | 2011-12-14 | 乾坤科技股份有限公司 | Chip packaging structure |
| WO2012068762A1 (en) * | 2010-11-26 | 2012-05-31 | 天水华天科技股份有限公司 | Ic chip package of sip system integration level and manufacturing method thereof |
| US8247891B2 (en) | 2008-09-10 | 2012-08-21 | Cyntec Co., Ltd. | Chip package structure including heat dissipation device and an insulation sheet |
| CN102938398A (en) * | 2011-08-16 | 2013-02-20 | 北京天中磊智能科技有限公司 | Packaging structure for kernel module of intelligent electricity meter |
| CN102944709A (en) * | 2011-08-16 | 2013-02-27 | 北京天中磊智能科技有限公司 | Electric meter module structure realized by adopting multi-chip system-level packaging technology and packaging method thereof |
| CN111681569A (en) * | 2020-07-24 | 2020-09-18 | 江西联创南分科技有限公司 | Miniature intelligent control digital tube assembly and electronic equipment lens |
-
2004
- 2004-01-19 CN CNU2004200196998U patent/CN2711906Y/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8247891B2 (en) | 2008-09-10 | 2012-08-21 | Cyntec Co., Ltd. | Chip package structure including heat dissipation device and an insulation sheet |
| CN101677092B (en) * | 2008-09-18 | 2011-12-14 | 乾坤科技股份有限公司 | Chip packaging structure |
| CN102074541A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof |
| WO2012068763A1 (en) * | 2010-11-26 | 2012-05-31 | 天水华天科技股份有限公司 | Gird-array ic chip package without carrier and manufacturing method thereof |
| WO2012068762A1 (en) * | 2010-11-26 | 2012-05-31 | 天水华天科技股份有限公司 | Ic chip package of sip system integration level and manufacturing method thereof |
| US9136231B2 (en) | 2010-11-26 | 2015-09-15 | Tianshui Huatian Technology Co., Ltd. | Carrier-free land grid array IC chip package and preparation method thereof |
| US9349615B2 (en) | 2010-11-26 | 2016-05-24 | Tianshui Huatian Technology Co., Ltd. | SiP system-integration IC chip package and manufacturing method thereof |
| CN102938398A (en) * | 2011-08-16 | 2013-02-20 | 北京天中磊智能科技有限公司 | Packaging structure for kernel module of intelligent electricity meter |
| CN102944709A (en) * | 2011-08-16 | 2013-02-27 | 北京天中磊智能科技有限公司 | Electric meter module structure realized by adopting multi-chip system-level packaging technology and packaging method thereof |
| CN111681569A (en) * | 2020-07-24 | 2020-09-18 | 江西联创南分科技有限公司 | Miniature intelligent control digital tube assembly and electronic equipment lens |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI MICROELECTRONICS DESIGN CO., LTD. Free format text: FORMER OWNER: JITONG DIGITAL CODE TECH CO LTD, SHANGHAI Effective date: 20080829 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20080829 Address after: Room 709, C District, 668 Beijing East Road science and technology capital, Shanghai, China: 200001 Patentee after: Shanghai Microelectronic Design Co., Ltd. Address before: Shanghai Guo Shou Jing Road, Zhangjiang High Tech Park of Pudong No. 351 Building No. 2 room 649-12, zip code: 200063 Patentee before: Jitong Digital Science and Technology Co., Ltd., Shanghai |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20140119 Granted publication date: 20050720 |