CN2699333Y - High-pressure withstanding mixed type spacing wall construction - Google Patents
High-pressure withstanding mixed type spacing wall construction Download PDFInfo
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- CN2699333Y CN2699333Y CN 200420059329 CN200420059329U CN2699333Y CN 2699333 Y CN2699333 Y CN 2699333Y CN 200420059329 CN200420059329 CN 200420059329 CN 200420059329 U CN200420059329 U CN 200420059329U CN 2699333 Y CN2699333 Y CN 2699333Y
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- spaced walls
- base plate
- mixed type
- high resistance
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Abstract
The utility model provides a high-pressure withstanding mixed type spacing wall construction of liquid crystal display. The liquid crystal display comprises two opposite filtering sheet base plates in parallel and a thin film transistor base plate; the high-pressure withstanding mixed type spacing wall construction comprises a plurality of pixel areas defined by a plurality of vertically crossed scanning lines and data lines, at least one main spacing wall is arranged in a first area between one pixel area and an adjacent pixel area thereof, and at least one subsidiary spacing wall is arranged in a second area between a pixel area and an adjacent pixel area thereof; wherein, the clearance height of the filtering sheet base plate and the thin film transistor base plate in the first area and the clearance height of the filtering sheet base plate and the thin film transistor base plate in the second area are different.
Description
Technical field
The utility model relates generally to a kind of high resistance to compression mixed type spaced walls (hybridspacer) structure of LCD.
Background technology
LCD has that external form is frivolous, power consumption is few and advantage such as radiationless pollution, therefore be widely used on the electronic product miscellaneous, for example display screens such as portable communications such as notebook computer, personal digital assistant product and large automatic equipment.Traditional liquid crystal display device structure is by a filter sheet base plate, a thin film transistor base plate, and the gap that liquid crystal is filled between filter sheet base plate and thin film transistor base plate constitutes.Traditional liquid crystal filling mode is earlier filter sheet base plate to be binded to the thin film transistor base plate surface, two substrates is placed in the cavity afterwards again, makes liquid crystal utilize the principle of capillarity to inject between filter sheet base plate and the thin film transistor base plate.Because traditional liquid crystal injection mode not only expends time in, and along with the development of large scale liquid crystal display, more make filling liquid crystal technology be easy to generate degradation problem under homogeneity and the yield, therefore present a kind of (one drop filling under the vacuum liquid crystal drop that is called, ODF) technology is high level of development, effectively addressing the above problem, and make LCD be applied to the volume production in large scale TV market.
The ODF technology is to utilize the principle of injection tube or ink-jet, with air pressure, servo motor or other similar modes with liquid crystal drop in the thin film transistor base plate surface, then thin film transistor base plate is delivered in the cavity together with filter sheet base plate, to provide suitable mechanical pressure and atmospheric pressure to make two substrate pressings, the thin film transistor base plate surface is located in utilization simultaneously or but the spaced walls on filter sheet base plate surface stays the gap that the brilliant molecule of feed flow exists between two substrates, and liquid crystal molecule is uniformly distributed in this gap.Hold liquid crystal in order to keep suitable gap, usually on thin film transistor base plate, insert plasticity pearl (plastic bead), beaded glass or glass fibre to spill cloth (spray) mode arbitrarily, yet the plasticity pearl that these are inserted etc. may be positioned at the light penetrating region, or present uneven distribution, cause the situation of gathering to take place, and then cause light to suffer scatterings such as plasticity pearl, the light that reduces LCD is to specific strength, perhaps also may produce white point (white point) defective, have a strong impact on display quality and product yield.
The above-mentioned variety of problems that may cause for fear of plasticity pearl spaced walls, utilize the formed photoresistance spaced walls of photoetching process (photo spacer) owing to have size, the position of accurate control spacer, and can keep suitable advantages such as gap length, therefore replace plasticity pearl spaced walls at present gradually, be used for keeping the filter sheet base plate of LCD, the gap between thin film transistor base plate, promote picture quality.
Please refer to Fig. 1, Fig. 1 is the synoptic diagram that is provided with of an existing photoresistance spaced walls.As shown in Figure 1, a thin film transistor base plate 10 surfaces include many sweep traces that intersect vertically 12 and data line 14, and by these sweep traces 12, a plurality of pixel region 18a, 18b, 18c etc. that data line 14 defined.In addition, thin film transistor base plate 10 more includes many common electrodes that are parallel to sweep trace 12 and is across pixel region, for instance, be across pixel region 18a, 18b, 18c with electrode 16 altogether, form storage capacitors with a pixel electrode (not being shown among the figure) with pixel region 18a, 18b, 18c surface.Existing photoresistance spaced walls 20 is utilized photoetching process to come define pattern and is arranged at a filter sheet base plate surface and (is shown in Fig. 2, numbering 30), for fear of the aperture opening ratio that influences LCD, each pixel region, with pixel region 18b is example, only comprises the zone that monospace wall 20 piles up mutually corresponding to common electrode 16 and data line 14 at the most.
Please refer to Fig. 2, Fig. 2 is the diagrammatic cross-section of an existing LCD.As shown in Figure 2, LCD includes two parallel relative thin film transistor base plates 10, filter sheet base plate 30, and liquid crystal 28 is filled between thin film transistor base plate 10 and the filter sheet base plate 30.Thin film transistor base plate 10 surfaces include metal levels such as common electrode 16, data line 14, and a protective seam 24 is covered in data line 14 surfaces, and a both alignment layers 26 is covered in thin film transistor base plate 10 surfaces.Filter sheet base plate 30 surfaces include a black matrix" 32, an optical filter 34, and a spaced walls 20 is arranged at the top, zone that common electrode 16, data line 14 pile up mutually.It is corresponding with both alignment layers 26 that filter sheet base plate 30 surfaces include a both alignment layers 36 in addition.
In existing spaced walls structure, each pixel region only can be provided with single spaced walls at the most above common electrode and zone that data line piles up mutually, so that 30 of thin film transistor base plate 10 and filter sheet base plates can be kept suitable clearance height, be used for filling liquid crystal.Generally speaking, single spaced walls is comparatively not enough on crushing resistance, and therefore the area that must increase spaced walls to be to improve its crushing resistance, avoids spaced walls to produce in use mechanical pressure and atmospheric pressure make the process of two substrate pressings and breaks, and influences product quality.Along with the area ratio of spaced walls increases, utilize the ODF technology also can and then reduce in the drip space of liquid crystal of thin film transistor base plate, therefore cause process window (process window) deficiency of liquid crystal easily, and reduce the product yield.In addition, another problem that may bring of the crushing resistance of utilizing the area ratio increase of spaced walls to improve spaced walls is the influence of display aperture ratio.As previously mentioned, spaced walls is arranged at the top across the common electrode of pixel region, therefore the permissible range of bit errors can increase along with the area ratio of spaced walls and be sacrificed unavoidablely between two substrates, even spaced walls is covered to the pixel region of part, reduce the aperture opening ratio of display.
The utility model content
Therefore, the purpose of this utility model is promptly providing a kind of high resistance to compression mixed type spaced walls structure (design), good pressure resistance can be provided and support gap between two substrates of LCD.
Another purpose of the present utility model can increase the process window that liquid crystal injects in that a kind of high resistance to compression mixed type spaced walls structure is provided.
According to the purpose of this utility model, high resistance to compression mixed type spaced walls structure includes a plurality of pixel regions that sweep trace and data line defined that intersect vertically by many, at least one master space wall is arranged at the wherein first area between pixel region pixel region adjacent thereto, and at least one secondary spaced walls is arranged at the wherein second area between pixel region pixel region adjacent thereto, and the filter sheet base plate of LCD and thin film transistor base plate are inequality in the clearance height of second area in the clearance height of first area and filter sheet base plate and thin film transistor base plate.
Because the utility model supports clearance height between filter sheet base plate and thin film transistor base plate except utilizing the master space wall, supplemental support when further utilizing secondary spaced walls to provide filter sheet base plate to be pressure bonded to thin film transistor base plate, therefore the secondary spaced walls of can be under the prerequisite that does not influence the LCD aperture opening ratio suitable increase of the area ratio of secondary spaced walls or configuration proper number is to improve crushing resistance, avoid master space wall, secondary spaced walls to break, influence product quality in using mechanical pressure and atmospheric pressure to make and producing in the process of two substrate pressings.On the other hand, the reduction that the area ratio of master space wall can also be suitable is to improve problems such as liquid crystal process window deficiency and the reduction of LCD aperture opening ratio.
Description of drawings
Fig. 1 is the synoptic diagram that is provided with of an existing spaced walls;
Fig. 2 is the diagrammatic cross-section of an existing LCD;
Fig. 3 is the synoptic diagram that is provided with of the utility model one mixed type spaced walls;
Fig. 4 is the diagrammatic cross-section of the utility model one LCD.
Description of reference numerals
10,40 thin film transistor base plates
12,42 sweep traces
14,44 data lines
16,46 common electrodes
18a, 18b, 18c, 48a, 48b, 48c, 50a, 50b, 50c pixel region
20,52,54 spaced walls
24,58 protective seams
26,36,60,76 both alignment layers
28,62 liquid crystal
30,70 filter sheet base plates
32,72 black matrix"s
34,74 optical filters
Embodiment
Please refer to Fig. 3, Fig. 3 is the synoptic diagram that is provided with of the utility model one photoresistance spaced walls.As shown in Figure 3, a thin film transistor base plate 40 surfaces include many sweep traces that intersect vertically 42 and data line 44, and by these sweep traces 42, a plurality of pixel region 48a that data line 44 defined, 48b, 48c, 50a, 50b, 50c etc.In preferred embodiment of the present utility model, pixel region 48a, 48b, 48c, 50a, 50b, 50c etc. may be defined as red time pixel, green time pixel or blue sub-pixels.In addition, thin film transistor base plate 40 more includes many common electrodes that are parallel to sweep trace 42 and is across pixel region, for instance, be across pixel region 48a, 48b, 48c with electrode 46 altogether, form storage capacitors with a pixel electrode (not being shown among the figure) with pixel region 48a, 48b, 48c surface.In preferred embodiment of the present utility model, common electrode 46 is to utilize same technology to make with sweep trace 42, that is is formed by same metal level.
Photoresistance spaced walls of the present utility model setting is to utilize photoetching process (to be shown in Fig. 4 in a filter sheet base plate surface, numbering 70) defines master space wall 52 and secondary spaced walls 54 patterns such as grade, for fear of the aperture opening ratio that influences LCD, master space wall 52 and secondary spaced walls 54 all are arranged at the adjacent zone (i.e. the zone that indicates with dotted line) between each pixel region pixel region adjacent thereto.For instance, master space wall 52 can be arranged on the top, zone that common electrode 46 and data line 44 between pixel region 48a and pixel region 48b pile up mutually, can be arranged on sweep trace 42 tops between pixel region 48a and pixel region 50a as for secondary spaced walls 54.Because thin film transistor base plate 40 is higher than the surface (only comprise sweep trace 42 metal levels) of thin film transistor base plate 40 corresponding to secondary spaced walls 52 corresponding to the surface (comprising two metal levels such as common electrode 46, data line 44 at least) of master space wall 52, so filter sheet base plate and thin film transistor base plate 40 are inequality in the clearance height in two zones that master space wall 52, secondary spaced walls 54 are set.Be to utilize the height fall of thin film transistor base plate 40 surperficial zoness of different to come nature to form 40 of filter sheet base plate 70 and thin film transistor base plates to have different clearance heights in preferred embodiment of the present utility model in master space wall 52 places and in secondary spaced walls 54 places.Yet the utility model is not limited thereto, can also further change the height of master space wall 52, secondary spaced walls 54 in other embodiments, or utilize the height fall of filter sheet base plate 70 surperficial zoness of different to come nature to form 40 of filter sheet base plate 70 and thin film transistor base plates to have different clearance heights in master space wall 52 places and in secondary spaced walls 54 places.In other words, master space wall 52 can have identical height or different height with secondary spaced walls 54, thin film transistor base plate 40 can trim in thin film transistor base plate 40 in the surface elevation that corresponds to secondary spaced walls 54 in the surface elevation that corresponds to master space wall 52, perhaps thin film transistor base plate 40 can also be inequality in the surface elevation that corresponds to secondary spaced walls 54 with thin film transistor base plate 40 in the surface elevation that corresponds to master space wall 52, in addition, filter sheet base plate 70 can also be for identical or inequality in surface elevation that master space wall 52 places are set and the surface elevation that secondary spaced walls 54 places are set.More precisely, the utility model does not limit the position that is provided with of master space wall 52 and secondary spaced walls 54, so long as adjacent zone (light tight zone) all can be used to be provided with master space wall 52 of the present utility model and secondary spaced walls 54 between different pixels, make filter sheet base plate 70 and thin film transistor base plate 40 inequality in the clearance height in two zones that master space wall 52, secondary spaced walls 54 are set.
Please refer to Fig. 4, Fig. 4 is the diagrammatic cross-section of the utility model one LCD.As shown in Figure 4, LCD includes two parallel relative thin film transistor base plates 40, filter sheet base plate 70, and liquid crystal 62 is filled between thin film transistor base plate 40 and the filter sheet base plate 70.Thin film transistor base plate 40 surfaces include common electrode 46, the sweep trace 42 that is formed by the first metal layer; the data line 44 that is formed by second metal level is stacked in common electrode 46 tops, and a protective seam 58, a both alignment layers 60 are covered in thin film transistor base plate 40 surfaces respectively.Can comprise structures (not being shown among the figure) such as insulation course and semiconductor layer in addition at the first metal layer that forms common electrode 46 and second metal interlevel that forms data line 44, decide on product configurations.Filter sheet base plate 70 surfaces include a black matrix" 72, an optical filter 74, one master space walls 52 and are arranged at the top, zone that common electrode 46, data line 44 pile up mutually, and a secondary spaced walls 54 is arranged at sweep trace 42 tops.It is corresponding with both alignment layers 60 that filter sheet base plate 70 surfaces include a both alignment layers 76 in addition.In preferred embodiment of the present utility model, thin film transistor base plate 40 and filter sheet base plate 70 are in the thickness that master space wall 52 places and the clearance height drop that secondary spaced walls 54 places are set comprise data line 44 and semi-conductor layer at least is set, this gap height fall is rough between 0.5-0.6 micron (μ m), and the density ratio that is provided with of master space wall and secondary spaced walls is about 1: 20.
Compared to existing photoresistance spaced walls structure, the utility model supports the clearance height of 40 of filter sheet base plate 70 and thin film transistor base plates except utilizing master space wall 52, supplemental support when further utilizing secondary spaced walls 54 to provide filter sheet base plate 70 to be pressure bonded to thin film transistor base plate 40, therefore the secondary spaced walls 54 of can be under the prerequisite that does not influence the LCD aperture opening ratio suitable increase of the area ratio of secondary spaced walls 54 or configuration proper number is to improve crushing resistance, avoid the master space wall, secondary spaced walls is broken in using mechanical pressure and atmospheric pressure to make and producing in the process of two substrate pressings, influences product quality.On the other hand, the reduction that the area ratio of master space wall 52 can also be suitable is to improve problems such as liquid crystal process window deficiency and the reduction of LCD aperture opening ratio.
The above only is a preferred embodiment of the present utility model, and all equalizations of being done according to the utility model claim change and modify, and all should belong to the covering scope of the utility model patent.
Claims (20)
1. the high resistance to compression mixed type spaced walls structure of a LCD is characterized in that this LCD includes two parallel relative filter sheet base plate and thin film transistor base plates, and this high resistance to compression mixed type spaced walls structure includes:
By many a plurality of pixel regions that sweep trace and data line defined that intersect vertically;
At least one master space wall is arranged at the wherein first area between pixel region pixel region adjacent thereto; And
At least one secondary spaced walls is arranged at the wherein second area between pixel region pixel region adjacent thereto, and this filter sheet base plate and this thin film transistor base plate are inequality in the clearance height of this second area in the clearance height of this first area and this filter sheet base plate and this thin film transistor base plate.
2. high resistance to compression mixed type spaced walls structure as claimed in claim 1 is characterized in that this master space wall and should the pair spaced walls be arranged on this filter sheet base plate.
3. high resistance to compression mixed type spaced walls structure as claimed in claim 2 is characterized in that this master space wall has identical height with this pair spaced walls.
4. high resistance to compression mixed type spaced walls structure as claimed in claim 2 is characterized in that this master space wall has different height with this pair spaced walls.
5. high resistance to compression mixed type spaced walls structure as claimed in claim 1 is characterized in that this thin film transistor base plate trims the surface in this thin film transistor base plate in this second area in the surface of this first area.
6. high resistance to compression mixed type spaced walls structure as claimed in claim 1 is characterized in that this thin film transistor base plate is higher than the surface of this thin film transistor base plate in this second area in the surface of this first area.
7. high resistance to compression mixed type spaced walls structure as claimed in claim 1 is characterized in that this filter sheet base plate trims the surface in this filter sheet base plate in this second area in the surface of this first area.
8. high resistance to compression mixed type spaced walls structure as claimed in claim 1 is characterized in that this filter sheet base plate has differing heights in surface and this filter sheet base plate of this first area in the surface of this second area.
9. high resistance to compression mixed type spaced walls structure as claimed in claim 1 it is characterized in that this thin film transistor base plate comprises at least two metal levels in this first area, and this thin film transistor base plate comprises at least one metal level in this second area.
10. high resistance to compression mixed type spaced walls structure as claimed in claim 1 is characterized in that it comprises many in addition and is parallel to respectively that the common electrode of this sweep trace is across respectively this pixel region.
11., it is characterized in that this first area comprises the zone that this data line respectively and this common electrode respectively pile up mutually as the high resistance to compression mixed type spaced walls structure of claim 10.
12. high resistance to compression mixed type spaced walls structure as claimed in claim 1 is characterized in that this second area comprises the respectively setting area of this sweep trace.
13. the high resistance to compression mixed type spaced walls structure of a LCD, it is characterized in that this LCD includes two parallel relative first substrate and second substrates, this high resistance to compression mixed type spaced walls structure includes at least one master space wall and a secondary spaced walls is arranged at first substrate surface, and the surface that this second substrate corresponds to this master space wall has different height with the surface that this second substrate corresponds to this pair spaced walls.
14. the high resistance to compression mixed type spaced walls structure as claim 13 is characterized in that this master space wall and this pair spaced walls are arranged at the adjacent zone between pixel region pixel region adjacent thereto.
15. the high resistance to compression mixed type spaced walls structure as claim 13 it is characterized in that this second substrate is a thin film transistor base plate, and the surface that this second substrate corresponds to this master space wall includes at least two metal levels.
16. the high resistance to compression mixed type spaced walls structure as claim 13 it is characterized in that this second substrate is a thin film transistor base plate, and the surface that this second substrate corresponds to this pair spaced walls includes at least one metal level.
17., it is characterized in that this master space wall is corresponding to a data line and the zone of piling up mutually with electrode altogether as the high resistance to compression mixed type spaced walls structure of claim 13.
18. the high resistance to compression mixed type spaced walls structure as claim 13 is characterized in that the setting area of this pair spaced walls corresponding to the one scan line.
19. the high resistance to compression mixed type spaced walls structure as claim 13 is characterized in that this master space wall surface trims in this pair spaced walls surface.
20. the high resistance to compression mixed type spaced walls structure as claim 13 is characterized in that this master space wall surface and this pair spaced walls surface have differing heights.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420059329 CN2699333Y (en) | 2004-05-10 | 2004-05-10 | High-pressure withstanding mixed type spacing wall construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420059329 CN2699333Y (en) | 2004-05-10 | 2004-05-10 | High-pressure withstanding mixed type spacing wall construction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2699333Y true CN2699333Y (en) | 2005-05-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420059329 Expired - Lifetime CN2699333Y (en) | 2004-05-10 | 2004-05-10 | High-pressure withstanding mixed type spacing wall construction |
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| CN (1) | CN2699333Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7920244B2 (en) | 2006-05-10 | 2011-04-05 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| CN103744216A (en) * | 2014-01-02 | 2014-04-23 | 北京京东方光电科技有限公司 | Liquid crystal display panel and manufacturing method thereof |
-
2004
- 2004-05-10 CN CN 200420059329 patent/CN2699333Y/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7920244B2 (en) | 2006-05-10 | 2011-04-05 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US8325314B2 (en) | 2006-05-10 | 2012-12-04 | Lg Display Co., Ltd. | Liquid crystal display device and method for fabricating the same |
| CN103744216A (en) * | 2014-01-02 | 2014-04-23 | 北京京东方光电科技有限公司 | Liquid crystal display panel and manufacturing method thereof |
| WO2015100970A1 (en) * | 2014-01-02 | 2015-07-09 | 京东方科技集团股份有限公司 | Liquid crystal display panel and manufacturing method therefor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20140510 Granted publication date: 20050511 |