CN2669484Y - Apparatus for realizing LVTTL level to LVPECL level conversion - Google Patents
Apparatus for realizing LVTTL level to LVPECL level conversion Download PDFInfo
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- CN2669484Y CN2669484Y CNU032095503U CN03209550U CN2669484Y CN 2669484 Y CN2669484 Y CN 2669484Y CN U032095503 U CNU032095503 U CN U032095503U CN 03209550 U CN03209550 U CN 03209550U CN 2669484 Y CN2669484 Y CN 2669484Y
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Abstract
The utility model provides an apparatus for realizing LVTTL level to LVPECL level conversion, comprising a LVTTL level interface unit, a LVPECL level interface unit, a coupling capacitance C1 and a divider circuit. The coupling capacitance C1 is used for coupling and exporting the LVTTL level signal with 3.3V pendulum deflection exported by the LVTTL level interface unit. The divider circuit is used for dividing the voltage of the AC signal coupled and exported by the coupling capacitance C1; the AC signal with about 0.8V pendulum deflection conforming to the LVPECL requirement is generated, inputting the LVPECL level interface unit. Adopting the technical project of the utility model, the LVTTL level interface unit and the LVPECL level interface unit are connected with a seam, without using the interface transform chip.
Description
Technical field:
The utility model belongs to the circuit design technique field, is specifically related to realize the device of LVTTL (Low VoltageTTL-low voltage transistor-transistor logic) level to LVPECL (emitter-coupled logic of the low positive pressure of Low Voltage Positive ECL--) level conversion.
Background technology:
At present, in the complicated circuit design, the signal coexistence that often has the multiple interfaces level is in circuit, and the signal of different interface levels is used for the different local of circuit.Mainly contained LVTTL level signal and CMOS (CMOS (Complementary Metal Oxide Semiconductor)) level signal in the past, but along with the increase in demand of people to high speed circuit, original interface level signal no longer is suitable for high speed circuit.For solving high-speed line transmission rate height, anti-interference, reach problems such as long transmission distance, some new interface level signals have been carried, and are widely applied in the circuit design.SSTL (Stub Series Terminated Logic-tap series terminal logic) level signal is wherein arranged, LVPECL level signal, LVDS (Low Voltage Differential Signaling--Low Voltage Differential Signal) level signal etc.This two classes signal of LVPECL level signal and LVDS level signal adopts differential pair to be used to transmit high speed signal usually.
Current for high-speed line, adopt LVPECL, LVDS level signal of difference etc. usually.Some high speed devices are only supported these interface level signals, and the device that docks with these high speed devices makes that owing to some reason of producer self etc. does not provide the same-interface level signal two devices can not seamless link.
The utility model content:
LVTTL is a kind of application interface level very widely, adopts the 3.3V power supply, has the amplitude of oscillation of 3.3V.LVPECL adopts the 3.3V power supply, single-ended input amplitude of oscillation 250mV-1200mV, the bias voltage of band 2.0V.The purpose of this invention is to provide a kind of passive device network (resistance capacitance) that utilizes and realize the device of LVTTL level signal, and need not use special purpose interface conversion of signals chip (as shown in Figure 1) to the conversion of LVPECL level signal.
The technical solution of the utility model is as follows:
A kind of device of realizing the LVTTL level to the LVPECL level conversion comprises LVTTL electric level interface device and LVPECL electric level interface device, also comprises:
A coupling capacitance C1 is used for the 3.3V amplitude of oscillation LVTTL level signal coupling output with described LVTTL electric level interface device output;
A bleeder circuit is used for producing the AC signal of the about 0.8V amplitude of oscillation that meets the LVPECL requirement with carrying out dividing potential drop through the AC signal of described coupling capacitance C1 coupling output, is input to described LVPECL interface level device.A concrete bleeder circuit is as shown in Figure 2: allow AC (interchange) signal code through C1 coupling back output pass through divider resistance R1 and R2 successively, again by arriving ground (GND) every straight coupling capacitance C2, form a loop like this, formation is to the electric resistance partial pressure of this AC signal, thereby obtains the AC signal of the 0.8V amplitude of oscillation between R1 and R2.Simple computation is as follows:
Electric current I ac=3.3V/ (R1+R2)
Voltage Vout=Iac*R2=0.8V
Said apparatus, level conversion do not provide bias voltage, are applicable to that self provides bias voltage, require the device of AC signal coupling input.
If require level converter not only AC (interchange) signal to be provided but also bias voltage is provided, when requiring the device of bias voltage is provided to be applicable to, so in said apparatus, the AC signal of the 0.8V amplitude of oscillation that meets the LVPECL requirement that produces after the process bleeder circuit dividing potential drop is exported every straight coupling capacitance C3 by one earlier, utilize bias circuit that the bias voltage of 2.0V is provided again, the AC signal of the 0.8V amplitude of oscillation is imported LVPECL interface level device with bias voltage more then.
As shown in Figure 3:
The LVTTL level signal through C1 coupling output, obtains AC (interchange) signal, and a loop that constitutes by R1, R2 and C2 utilizes R1, R2 dividing potential drop (R1, R2 adopt aforementioned manner) again, obtains the AC signal of the 0.8V amplitude of oscillation between R1 and R2; Be the influence of the bias circuit that prevents the back to R1, R2 effect, use C3 every straight coupling capacitance, the AC signal of the 0.8V amplitude of oscillation is outputed to bias circuit----3.3V DC (direct current) power supply successively by loop of ground connection formation behind bias resistance R3, the R4, by the dividing potential drop of R3, R4, between R3, R4, obtain the bias voltage of about 2.0V; Simple computation is as follows:
Vdc＝3.3V*(R4)/(R3+R4)＝2.0V
The resistance of bias resistance R3, R4 is selected, and requires as long as divide pressure energy to obtain the bias voltage of 2.0V between R3, R4; But the resistance of R3, R4 that is noted that selection is improper, can produce big influence to the AC signal amplitude of oscillation of coupling input, because the loop that R3, R4 constitute also is a loop for AC signal.
Adopt the technical solution of the utility model, during conversion, at first, and with the LVTTL level signal of the 3.3V amplitude of oscillation, coupling output; Utilize bleeder circuit again, produce the AC signal of about 0.8V amplitude of oscillation, the bias voltage of 2.0V; 2.0V bias voltage as not needing, can not add.
Advantage of the present utility model and good effect:
Adopt the technical solution of the utility model, can be so that LVTTL interface level device has to stitch with LVPECL interface level device to be connected, and need not use the interface conversion chip.
Description of drawings:
Fig. 1 is LVTTL level of the present utility model and LVPECL level converter schematic block diagram;
Fig. 2 is LVTTL level and LVPECL level converter structure chart (not being with bias voltage), is applicable to the LVPECL interface device that requires AC coupling input;
Fig. 3 is LVTTL level and LVPECL level converter structure chart (band bias voltage), is applicable to the LVPECL interface device that requires to provide bias voltage.Need 100 ohm differential resistor for the LVPECL of differential pair.
Among the figure:
R1, R2-divider resistance R3, R4-bias resistance R5-differential resistor
C1-coupling capacitance C3, C2-are every straight coupling capacitance
Embodiment:
Embodiment 1:
As shown in Figure 2, be the device of a kind of LVTTL of realization level of the present utility model to the LVPECL level conversion.Level converter does not provide bias voltage, is applicable to the device that bias voltage is provided self.Comprise LVTTL electric level interface device and LVPECL electric level interface device, also comprise with lower member:
A coupling capacitance C1 (0.1uf) is used for the 3.3V amplitude of oscillation LVTTL level signal coupling output with the output of LVTTL electric level interface device;
A bleeder circuit is used for producing the AC signal of the about 0.8V amplitude of oscillation that meets the LVPECL requirement with carrying out dividing potential drop through the AC signal of coupling capacitance C1 coupling output, is input to LVPECL interface level device.Bleeder circuit comprises divider resistance R1 and R2, and AC (interchange) signal code of coupling capacitance C1 coupling back output passes through to arrive ground every straight coupling capacitance C2 again, thereby obtain the AC signal of the 0.8V amplitude of oscillation between R1 and R2 successively by R1 and R2.0.8V the AC signal of the amplitude of oscillation is directly imported the LVPECL electric level interface device that requirement only provides AC signal, thereby finishes the conversion of interface level.
Be calculated as follows:
Suppose R1=158 ' Ω (ohm); R2=50 ' Ω (ohm); C2=0.1uf;
Iac=3.3V/ (R1+R2)=3.3V/ (158 ' Ω+50 ' Ω)=＞be about 0.016A;
Vout＝Iac*R2＝0.016A*50′Ω＝0.8V；
Device is placed:
C1 and R1 resistance are placed near sending device;
R2 as far as possible near the corresponding pin of receiving device, can be played the effect of terminal coupling; Simultaneously C2 is placed near R2, make electric current arrive ground (GND) nearby.
Embodiment 2:
As shown in Figure 3, be the device of a kind of LVTTL of realization level to the LVPECL level conversion, the AC signal not only is provided, bias voltage also is provided, be applicable to the device that requires to provide bias voltage.On the basis of embodiment 1, increased bias voltage.Comprise LVTTL electric level interface device and LVPECL electric level interface device, also comprise:
1. a coupling capacitance C1 (0.1uf) is used for the 3.3V amplitude of oscillation LVTTL level signal coupling output with the output of LVTTL electric level interface device;
2. a bleeder circuit is used for producing the AC signal of the about 0.8V amplitude of oscillation that meets the LVPECL requirement with carrying out dividing potential drop through the AC signal of coupling capacitance C1 coupling output, is input to LVPECL interface level device.Bleeder circuit comprises divider resistance R1 and R2, and AC (interchange) signal code of coupling capacitance C1 coupling back output passes through to arrive ground every straight coupling capacitance C2 again, thereby obtain the AC signal of the 0.8V amplitude of oscillation between R1 and R2 successively by R1 and R2.
Be calculated as follows:
Suppose R1=158 ' Ω (ohm); R2=50 ' Ω (ohm); C2=0.1uf
Iac=3.3V (R1+R2)=3.3V/ (158 ' Ω+50 ' Ω)=＞be about 0.016A;
Vout＝Iac*R2＝0.016A*50′Ω＝0.8V；
Device is placed:
C1 and R1 resistance are placed near sending device;
R2 as far as possible near receiving device, can be played the effect of terminal coupling; Simultaneously C2 is placed near R2, make electric current arrive ground (GND) nearby.
3. every straight coupling capacitance C3:
With the AC signal output that meets the 0.8V amplitude of oscillation that LVPECL requires that produces;
4. bias circuit: utilize electric resistance partial pressure that the bias voltage of 2.0V is provided
3.3V DC (direct current) power supply forms a loop by ground connection behind bias resistance R3, the R4 successively, by the dividing potential drop of R3, R4, obtains the bias voltage of about 2.0V between R3, R4; Be calculated as follows:
Suppose R3=3K Ω; R4=4.7K Ω
Vdc=3.3V* (R4)/(R3+R4)=3.3V*R4/ (3K Ω+4.7K Ω)=＞about 2.0V places C3, R3, R4 near receiving device.
0.8V the AC signal of the amplitude of oscillation and bias voltage are input to LVPECL interface level device;
In addition, for the LVPECL signal of difference, also need between two paths of signals, to add one 100 ohm differential resistor R5.The resistance of existing 100 Ω of some device inside oneself, that just no longer needs R5.
Claims (6)
1. a device of realizing the LVTTL level to the LVPECL level conversion comprises LVTTL electric level interface device and LVPECL electric level interface device, it is characterized in that also comprising with lower member:
A coupling capacitance C1 is used for the 3.3V amplitude of oscillation LVTTL level signal coupling output with described LVTTL electric level interface device output;
A bleeder circuit is used for producing the AC signal of the about 0.8V amplitude of oscillation that meets the LVPECL requirement with carrying out dividing potential drop through the AC signal of described coupling capacitance C1 coupling output, is input to described LVPECL interface level device.
2. a kind of device of realizing the LVTTL level to the LVPECL level conversion as claimed in claim 1 is characterized in that, also comprises as lower member:
One every straight coupling capacitance C3, and the described AC signal that meets the 0.8V amplitude of oscillation that LVPECL requires is exported every straight coupling capacitance C3 by described earlier;
A bias circuit, be used for providing the bias voltage of 2.0V to described every the AC signal that meets the 0.8V amplitude of oscillation that LVPECL requires of straight coupling capacitance output, the AC signal of the 0.8V amplitude of oscillation that the described LVPECL of meeting requires is imported LVPECL interface level device with bias voltage again.
3. a kind of device of realizing the LVTTL level to the LVPECL level conversion as claimed in claim 1, it is characterized in that, described bleeder circuit comprises divider resistance R1 and R2, the AC AC signal current of described coupling capacitance C1 coupling back output is successively by R1 and R2, pass through again to arrive ground, thereby between R1 and R2, obtain the AC signal of the 0.8V amplitude of oscillation every straight coupling capacitance C2.
4. a kind of device of realizing the LVTTL level to the LVPECL level conversion as claimed in claim 2, it is characterized in that, described bias circuit is: the DC power supply of 3.3V forms a loop by ground connection behind bias resistance R3, the R4 successively, by the dividing potential drop of R3, R4, between R3, R4, obtain the bias voltage of about 2.0V.
5. a kind of device of realizing the LVTTL level to the LVPECL level conversion as claimed in claim 3, it is characterized in that, described coupling capacitance C1 and divider resistance R1 are geographically near described LVTTL electric level interface device, described divider resistance R2 is geographically near described LVPECL electric level interface device, and is described every the geographically close described divider resistance R2 of straight coupling capacitance C2.
6. a kind of device of realizing the LVTTL level to the LVPECL level conversion as claimed in claim 4 is characterized in that, and is described every the geographically close described LVPECL electric level interface device of straight coupling capacitance C3, bias resistance R3, bias resistance R4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU032095503U CN2669484Y (en) | 2003-09-15 | 2003-09-15 | Apparatus for realizing LVTTL level to LVPECL level conversion |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU032095503U CN2669484Y (en) | 2003-09-15 | 2003-09-15 | Apparatus for realizing LVTTL level to LVPECL level conversion |
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| CN2669484Y true CN2669484Y (en) | 2005-01-05 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102857210A (en) * | 2012-09-28 | 2013-01-02 | 无锡江南计算技术研究所 | Different voltage standard label virtual circuit metal oxide semiconductor (LVCMOS) signal direct interconnection method |
| CN103066960A (en) * | 2013-01-17 | 2013-04-24 | 中国科学技术大学 | Generating device and method of large-amplitude ultra-high speed synchronization pulse |
| CN103716051A (en) * | 2013-12-16 | 2014-04-09 | 广东正业科技股份有限公司 | High-precision analog-to-digital conversion circuit system |
| CN106936422A (en) * | 2015-12-30 | 2017-07-07 | 格科微电子（上海）有限公司 | Level shifting circuit |
-
2003
- 2003-09-15 CN CNU032095503U patent/CN2669484Y/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102857210A (en) * | 2012-09-28 | 2013-01-02 | 无锡江南计算技术研究所 | Different voltage standard label virtual circuit metal oxide semiconductor (LVCMOS) signal direct interconnection method |
| CN103066960A (en) * | 2013-01-17 | 2013-04-24 | 中国科学技术大学 | Generating device and method of large-amplitude ultra-high speed synchronization pulse |
| CN103066960B (en) * | 2013-01-17 | 2015-04-22 | 中国科学技术大学 | Generating device and method of large-amplitude ultra-high speed synchronization pulse |
| CN103716051A (en) * | 2013-12-16 | 2014-04-09 | 广东正业科技股份有限公司 | High-precision analog-to-digital conversion circuit system |
| CN106936422A (en) * | 2015-12-30 | 2017-07-07 | 格科微电子（上海）有限公司 | Level shifting circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: HUAWEI TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: GANGWAN NETWORK CO., LTD. Effective date: 20061020 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20061020 Address after: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee after: Huawei Technologies Co., Ltd. Address before: 100089, No. 21 West Third Ring Road, Beijing, Haidian District, Long Ling Building, 13 floor Patentee before: Harbour Networks Holdings Limited |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050105 Termination date: 20110915 |