CN2662316Y - System mainboard for embedded computer system - Google Patents
System mainboard for embedded computer system Download PDFInfo
- Publication number
- CN2662316Y CN2662316Y CN 200320122195 CN200320122195U CN2662316Y CN 2662316 Y CN2662316 Y CN 2662316Y CN 200320122195 CN200320122195 CN 200320122195 CN 200320122195 U CN200320122195 U CN 200320122195U CN 2662316 Y CN2662316 Y CN 2662316Y
- Authority
- CN
- China
- Prior art keywords
- chip
- bus
- system board
- port
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The utility model relates to a system mainframe used by an embedded computer system, comprising a CPU chip, a synchronous dynamic random memory chip, an enable chip, a flash memory chip and an on-the-spot programmable gate array chip and other members. The chips carry out communication with each other through the data bus and the address bus. An X port and an X port bus are defined on the system mainframe. The X port buses are separately connected with a dual-serial-port and a backup enable chip outside the system mainframe and the connection of the system mainframe with the embedded computer system are based on the COMPACT PCI bus and the X port bus structure. The utility model provides a high-performance computer mainframe with strong function and handling capacity, small volume and moderate power consumption, and can be applied to the aerospace area and especially applied to the projects demanding high handling capacity.
Description
Technical field
The utility model relates to a kind of computer system motherboard, relates in particular to the system board of the embedded computer system of the high-performance that is applied in the Aeronautics and Astronautics field, high reliability.
Background technology
Compact PCI technology is a kind of small and exquisite and firm high performance bus technology based on the standard pci bus.1994 PICMG (PCI Computer Manufacturer ' s Group, PCI industrial computer GPMA) Compact PCI technology has been proposed, it has defined more robust PCI version.Aspect electric, logic and software, it and PCI standard are compatible fully.
Compact PCI plate has following characteristics:
The PCI local bus
The Eurocard size of standard (according to IEEE 1101.1 machinery standards)
HD (high density) 2mm pin and socket connector (the IEC approval, Bellcore)
One, PCI local bus
PCI is the interconnected meaning of peripherals, becomes commercial PC bus standard very soon by the Intel issue in 1992.PCI is a kind of data bus that is independent of processor, not only functional but also low price.Two kinds of data widths of PCI local bus general idea: 32 and 64, bus speed can reach 66MHZ, the gross data processing power: 32 is 264MB/S, and 64 is 528MB/S.Most computers and operating system are all supported PCI.Because the product of a large amount of support PCI is arranged, make the PCI product not only cheaply but also easily buy.Have these advantages, pci bus is highly suitable in supercomputing and the high-speed data communications field and uses.
Two, European plug-in card physical construction
European plug-in card physical construction is a kind of technical grade packaging standard of being promoted by VMEbus.Two kinds of European plug-in card specifications are arranged: 3U and 6U.3U Compact pci card is of a size of 160mm * 100mm, and the 6U card is 160mm * 233.35mm, and its concrete shape as shown in Figure 1.The front panel of Compact pci card meets IEEE 1101.1 and IEEE 1101.10 standards, and can comprise optional EMC O-ring seal to reduce electromagnetic interference (EMI).Front panel comprises the I/O interface in typical case, LED light and switch.Compact PCI also supports the rear panel I/O of IEEE 1101.11.Because its characteristic that is easy to safeguard, it is very general that rear panel I/O uses on telecommunication apparatus.Because all lines all are connected on the card extender of rear portion, therefore the Compact PCI plug-in card of front can need not line again without any line when changing integrated circuit board.
Three, pin hole connector
Compact PCI uses and meets IEC-1076 international standard high density air hermetic pin hole connector, the metal stitch of its 2mm has low induction reactance and impedance, thereby reduced the signal reflex that the high-speed PCI bus causes, make the Compact pci system can reach 8 grooves in the unibus section, Compact PCI has defined 5 kinds of interface: J1 to J5, and standard has only defined the signal wire pin of J1 and J2.3U Compact PCI integrated circuit board has only J1 and two interfaces of J2, and 6U plate J1 comprises to J5.J1 and J2 are the same at 3U with definition on the 6U Compact PCI integrated circuit board, so 3U and 6U Compact PCI integrated circuit board can exchange on electric.
The Compact pci system is made up of one or more Compact PCI section, and each section comprises 1 block system plate (System Slot) and 7 peripheral boards (Peripheral Slot), and the spacing at plate and plate center is 20.32mm.System board provides arbitration, clock distribution and reset function for the plate in all these sections.System board is responsible for the initialization of executive system, manages the idsel signal on each this floor.Physically, system board can be inserted in any position on the backboard.For the simplification problem, the leftmost groove of regulation and stipulation position is the slot (from the backboard front) of system board, and concrete position as shown in Figure 2.Card is installed for vertical in the system, to guarantee suitable heat radiation.Air-flow is even, and thermal diffusivity is good.
The Compact pci bus has the favorable mechanical characteristic.It has strengthened maintainability and the reliability of pci system in the industrial environment of telecommunications or other inclement conditions.Compact PCI plate is deferred to Eurocard encapsulation standard, thereby has increased other Reliability ﹠ Maintainability of technical grade for the PCI environment.The Eurocard characteristic comprises a great selection of integrated circuit board characteristic (4096 combinations can be arranged), as the front console block, reduce the EMC protection feature of electromagnetic interference (EMI) etc.Compact PCI circuit board adopts the 2mm contact pin connectors of IEC specification, and its slot circuit board can insert from the cabinet front, and the I/O plate can insert from the cabinet front and also can insert from the back side.The connector of Compact PCI itself is different pin and a slot type connector of height.These needle tray connectors can provide velocity of propagation faster, reduce the reflection on bus/attachment unit interface, reduce noise, matched impedance better, and improved Mechanical Reliability.These needle tray connectors, block mechanism etc. combine, and for being connected between each piece plate and system provides better support and permanance, maintenance, repairing and upgrading etc. are also all significantly simplified.
The Compact pci bus is to be the industrial bus of high-performance of standard with the PCI electrical code.The Compact pci bus is easy to expansion, can support nearly 256 Standard PC I bus apparatus simultaneously.It can support 8 slots in each subsystem, add bridging chip after, Compact PCI can expand at an easy rate and support 32 slots.
Based on the advantage of above Compact pci bus technology, these bus structure replace original bus structure just gradually, are widely used in the computer system in fields such as Industry Control.APCI5000 series built-in industrial controller has adopted Compact pci bus technology at present, base plate has only system's groove, single CPU board, its performance has obtained improving greatly, but the field of all having relatively high expectations for system reliability and computing power, Aeronautics and Astronautics field for example, its reliability and performance all have much room for improvement.
Simultaneously, the high speed development of modern Space Science and Technology need the data-handling capacity of aerospace computer to increase substantially, and the aerospace computer of present domestic use can't reach such high request, for this reason, the research and development based on the computer motherboard of high-performance CPU just seem particularly necessary.An astrionic system is a typical hierarchical structure, more to the upper strata, high more, also high more to the requirement of reliability simultaneously to the requirement of the processing power of computing machine, different functional blocks is inequality to the processing power requirement of computing machine, and the amount of data information exchange is also different.At present, the astrionic system of China is existing than the proven technique deposit aspect middle reduction process ability computing machine and middle low-rate data networking transmission, and aspect high-performance computer and the high speed data transfer and international most advanced level also have tangible gap.
In addition, satellite or Airship system generally offer the 27V power supply and give load, and the voltage that most integrated circuit (IC) chip adopts is 5V, 3.3V, 2.5V etc.; Simultaneously,, make it be the aerospace engineering service more effectively, advanced steering logic rationally that must adopt and effective monitoring means in order to control the working method with the monitoring computer system.The structure of existing computer system and the design of integrated circuit board all need further improvement.
The utility model content
Technical problem to be solved in the utility model provides the system board that a kind of embedded computer system is used, improve system performance, processing power and the reliability of system board, and the characteristics of matching embedded type computing machine dual system, further increase described performance of computer systems, system reliability and stability.
In order to solve the problems of the technologies described above, the system board that the embedded computer system that the utility model provides is used, comprise a central processing unit chip and synchronous dynamic random storage chip, comprise that also one starts chip, one flash memory chip and a field programmable gate array chip, carry out communication by data bus and address bus between the said chip, also definition has X port and X port bus on described system board, the X port is connected respectively to the outer two serial port chip of system board and backup starts chip, and system board is connected with X port bus structure based on the COMPACT pci bus with embedded computer system.
In such scheme, the read-only storage space of the central processing unit chip of described system board is divided into RCS0 address space and RCS1 address space two parts, wherein the part of RSC0 address space is as the address space that starts chip, and a part is used as input/output end port, is called the X port; The RCS1 space is configured to the flash address space, is partitioned organization, as depositing user program.
In such scheme, by the decoding logic of field programmable gate array chip, the segment space of X port is used as resetting, feed dog, interrupting reading in and interrupt auxiliary logic such as isolated controlling of X port sheet choosing, the choosing of two serial ports sheet, PCI equipment.
In such scheme, the SYSEN# signal is introduced in the central processing unit chip, the MAA1 signal of control central processing unit chip, when MAA1 is high, the central processing unit chip operation is under holotype, and corresponding system board also is operated under the holotype, when MAA1 is low, the central processing unit chip operation is under pattern, and corresponding system board also is operated under pattern; The SYSEN# signal is introduced in the field programmable gate array chip in the system board simultaneously, the control backup starts address, the data bus of chip, when system board is operated in the holotype plate, address, data bus that backup starts chip are logical, when system board was operated in from pattern, address, data bus that backup starts chip were high-impedance state.
In such scheme, described field programmable gate array chip is finished auxiliary logic, comprises the driving to described flash memory chip, startup chip, X port address, control bus; Simultaneously described startup chip and X port be+the 5V chip, described system board utilize the LVTTL level of 5V Tolerance characteristic realization+3.3V of field programmable gate array chip same+conversion of the HCMOS level of 5V; And on the integrated circuit board of startup boot outside system board of described system board redundancy backup is arranged, active and standby part of boot takies identical physical space, field programmable gate array chip is according to steering logic, the system board that guarantees only to be operated under the holotype uses the X port function, and the system board that also only is under the holotype can use the backup boot.
In such scheme, the BOOTSEL signal is introduced in the field programmable gate array chip, by the logic switch in the described field programmable gate array chip, the mode that control starts, when the BOOTSEL signal when low, address, the data bus of described startup chip are unlocked, and described backup starts address, the data bus of chip and isolated; Same address, data bus that backup starts chip are unlocked when BOOTSEL signal when being high, and address, the data bus of startup chip are isolated.
In such scheme, when input SYSEN# signal was low, input BOOTSEL signal was low, and system is from being positioned at the startup chip enable on the system board that is operated under the holotype, the BOOTSEL signal is high, and system starts chip enable from the backup that is positioned on the external interface; When input SYSEN# signal when being high, system can only be from being positioned at the startup chip enable on the system board that is operated under the holotype.
In such scheme, effective when hanging down when the SYSEN# signal except that the described signal of dog of feeding, when the SYSEN# signal is isolated when being high, thereby assurance is operated in system board under the holotype to the control of system resource.
In such scheme, the storage space at random of described central processing unit chip is the 64M address space, data width is 64+8 ECC verifications, the data bus of central processing unit chip directly is connected with the data bus of synchronous DRAM chip, address bus must can be selected the frequency of operation of SDRAM through being connected with the address bus of synchronous DRAM (SDRAM) behind the 10 Ω resistor chains by configuration pin.
In such scheme, a 1553B Bus Interface Chip is arranged on the described CPU board, this interface chip is to pass through pci bus with being connected of described central processing unit chip, be integrated with the PCI bridge at chip internal, pci signal is converted to local signal, then by the 1553B bus, mainboard and external system just can be carried out communication, as long as power supply is provided, described system board carries out communication by 1553B bus and external unit, becomes a single board computer.
In such scheme, described system board has adopted MPC8240 series CPU as the central processing unit chip.
In such scheme, described system board satisfies COMPACT PCI 3U standard or COMPACT PCI 6U standard.
In sum, the system board that the embedded computer system that the utility model provides is used, be according to the design of the characteristics of embedded computer system dual system, double startup, by X port bus and pci bus and whole computer system communication, and is connected backup startup chip on power supply/control panel in the computer system with the X port bus by the X port, height by the SYSEN# signal introduced, control principal and subordinate's mode of operation of described system board, and introduce the BOOTSEL signal, thereby realize the double startup of described system.Thus, the high-performance computer system mainboard that the utility model provides, powerful, processing power is strong, and volume is less, and power consumption is moderate, and the reliability height.Be applicable to fields such as Aero-Space, be particularly suitable for the project that processing power is had relatively high expectations.
Description of drawings
Fig. 1 is the system board schematic diagram of the utility model embodiment;
Fig. 2 is a field programmable gate array chip control double startup logical diagram in the system board of the utility model embodiment;
Fig. 3 is X port address allocation of space figure in the system board of the utility model embodiment;
The drawing explanation:
System board---30; Cpu chip---31;
Synchronous dynamic random storage chip (SDRAM)---32;
Start chip (BOOTROM chip)---33;
Flash memory chip (FLASHDISK)---34;
Field programmable gate array chip (fpga chip)---35;
The PCI-1553B interface chip---36;
Reset and watchdog circuit---37; 10 Ohmages---38.
Embodiment
Describe the technical solution of the utility model in detail below in conjunction with the drawings and specific embodiments.
As shown in Figure 1, system board (CPU board) 30 is followed Compact PCI 3U standard, is of a size of 160mm * 100mm, has J1 and J2 two card i/fs.This system board 30 comprises cpu chip 31, synchronous dynamic random storage chip (SDRAM) 32, startup chip (BOOTROM chip) 33, flash memory chip (FLASHDISK) 34, field programmable gate array chip (fpga chip) 35, PCI-1553B interface chip 36, resets and watchdog circuit 37,10 Ohmages 38, X port (PORTX) (not shown), data bus, address bus, pci bus and X port bus (PORTX bus) etc.Being connected of system board and whole computer system be based on the Compact pci bus and PORTX bus-structured.
The ROM space of cpu chip 31 is divided into two parts, RCS0 address space and RCS1 address space, the RCS0 space is configured to 8 bit data width, 1M address space in design, BOOTROM as system start-up, the RCS1 space is configured to 64 bit data width, 8M address space, as depositing user program, its structure is configured to the partitioned organization of similar electronic hard disc, is called FLASHDISK in native system.
Wherein, the RCS0 address space of cpu chip 31 not only can be the memory device use but also can be the nonstorage device use, promptly can use as general purpose I/O port, be called X port (PORTX) 39, in the design,, the part address of RCS0 address space is used as PORTX uses by FPGA, two serial ports and backup BOOTROM all are connected on the PORTX bus, and simultaneously the segment space of PORTX is used as resetting, feed dog, interrupting reading in, interrupting auxiliary logic such as isolated controlling of PCI equipment.
As shown in Figure 3, in fpga chip 35, by decoding logic, the RCS0 address space is repartitioned, except that high 1M space is boot (BOOTROM) district, remaining 1M space is divided into: standby of PORTX selects 1,2, interrupt isolated controlling, the control of PCI device reset, two serial ports sheet choosings, external interrupt is read in, and feeds dog etc.Except that feeding dog, remaining signal is effective when SYSEN is low level, is isolated when SYSEN is high level.So just can guarantee as the control of the CPU board of main equipment system resource.
The FLASHDISK that is articulated to the RCS1 address space is configured to the partitions of file system of similar hard disk, and a plurality of user programs can be stored in wherein, can activate certain application program by order, thereby carry out corresponding task.
The ram space of cpu chip 31 is the 64M address space, data width is 64+8 ECC verifications, used and closed 1 synchronous DRAM (SDRAM) for 15, the data bus of CPU directly is connected with the data bus of synchronous DRAM (SDRAM) chip 32, and address bus must be through being connected with the address bus of synchronous DRAM (SDRAM) behind the 10 Ω resistor chains.Can select the frequency of operation of synchronous DRAM (SDRAM) chip 32 by configuration pin, in the design, synchronous DRAM (SDRAM) can be operated under the 100MHZ frequency, and this moment, cpu chip 31 frequency of operation were 200MHZ.
As shown in Figure 1,1553B interface chip 36 on CPU board and cpu chip 31 are connected by pci bus, be integrated with the PCI bridge in 1553B interface chip 36 inside, pci signal is converted to the LOCAL signal, the 1553B bus is made up of 1553B bus A and 1553B bus B, just can carry out communication with external system by 1553B bus interface CPU board.
As long as power supply is provided for above-mentioned CPU board 30, this high performance motherboard just can carry out communication by 1553B bus and external unit, becomes a single board computer.
In sum, described FPGA finishes auxiliary logic, comprises the driving to FLASHDISK, BOOTROM chip, PORTX address, control bus, finishes the driving to BOOTROM chip and PORTX data bus.
Simultaneously since BOOTROM chip and PORTX be+the 5V chip, native system utilize the LVTTL level of 5V Tolerance characteristic realizations+3.3V of FPGA same+conversion of the HCMOS level of 5V.
In addition, because the BOOTROM of native system has redundancy backup on power panel, active and standby part of BOOTROM takies identical physical space, FPGA is according to the steering logic on the power panel, guarantee that the CPU board only be in main part state just can use the PORTX interface function, the CPU board that also only is in main part state just can be used backup BOOTROM.
As shown in Figure 2, the SYSEN# signal imports CPU board into by base plate, the MAA1 signal of SYSEN# control CPU, and when the MAA1 signal be a height, CPU is operated in holotype (HOST), and when the MAA1 signal is low, CPU is operated in from pattern (AGENT).Same SYSEN# signal is introduced into FPGA, the control backup starts the address data bus of chip (BOOTROMBAK chip), when equipment is HOST, BOOTROMBAK chip address data bus is logical, the BOOTROMBAK address data bus is a high-impedance state when equipment is AGENT, promptly when equipment is HOST, both can adopt the boot (BOOTROM) on the BOOTROM chip to start, and also can adopt the backup boot (BOOTROMBAK) on the BOOTROMBAK chip to start; When equipment is AGENT, can only adopt the BOOTROM on the BOOTROM chip to start.
As shown in Figure 2, the BOOTSEL signal is introduced among the FPGA, by the logic switch among the FPGA, the mode that control starts, when the BOOTSEL signal when low, address, the data bus of BOOTROM chip are unlocked, the address of BOOTROMBAK chip, data bus are isolated; Equally when BOOTSEL signal when being high, address, the data bus of BOOTROMBAK chip are unlocked, and the address of BOOTROM chip, data bus are isolated.
As from the foregoing, the realization of double startup is to control and finish by being positioned at fpga chip 35 on the CPU board in the said system, when external control order SYSEN# signal when low (at this moment, this CPU board is a main equipment), external control order BOOTSEL signal is low, system starts from the BOOTROM that is positioned on this CPU board, the BOOTSEL signal is high, system starts chip (BOOTROMBAK chip) startup by PORTX from the backup that is positioned on the external interface, and the BOOTROMBAK chip comes from power supply/control interface board; When external control order SYSEN# signal when being high (at this moment, this CPU board is a slave unit), system can only start from the BOOTROM that is positioned on this CPU board.Below be the process that starts:
1, in the system board insertion system slot, the SYSEN# signal of input is low
1) external control order BOOTSEL signal is low, and this system board is main equipment (HOST), and starts from starting chip (BOOTROM chip); Startup is finished, and prints in hyper terminal: " system starts chip (BOOTROM chip) and starts from this locality, HOST is this system board ";
2) external control order BOOTSEL signal is high, this system board is main equipment (HOST), and starting chip (BOOTROMBAK chip) from backup starts, startup is finished, print in hyper terminal: " system starts chip (BOOTROMBAK chip) from backup and starts, and HOST is this system board ".
When 2, the SYSEN# signal of said system host slot input is high
System board can only be from the BOOTROM chip enable, and can not use the two serial ports on the PORTX, and hyper terminal does not have type information.
In addition, the technical solution of the utility model can be applicable under the Compact PCI 6U standard equally, and just the size of integrated circuit board changes.
Claims (9)
1, the system board that a kind of embedded computer system is used, comprise a central processing unit chip and synchronous dynamic random storage chip, it is characterized in that: comprise that also one starts chip, one flash memory chip and a field programmable gate array chip, carry out communication by data bus and address bus between the said chip, also definition has X port and X port bus on described system board, the X port is connected respectively to the outer two serial port chip of system board and backup starts chip, and system board is connected with X port bus structure based on the COMPACT pci bus with embedded computer system.
2, the system board used of embedded computer system as claimed in claim 1, the read-only storage space that it is characterized in that the central processing unit chip of described system board is divided into RCSO address space and RCS1 address space two parts, wherein the part of RSCO address space is as the address space that starts chip, a part is used as input/output end port, is called the X port; The RCS1 space is configured to the flash address space, is partitioned organization, as depositing user program.
3, the system board used of embedded computer system as claimed in claim 2, it is characterized in that the decoding logic by field programmable gate array chip, the segment space of X port is used as resetting, feed dog, interrupting reading in and interrupt auxiliary logic such as isolated controlling of X port sheet choosing, the choosing of two serial ports sheet, PCI equipment.
4, the system board used of embedded computer system as claimed in claim 1, it is characterized in that, comprise that also a SYSEN# signal is introduced in the central processing unit chip, the MAA1 signal of control central processing unit chip, when MAA1 be a height, the central processing unit chip operation is under holotype, corresponding system board also is operated under the holotype, when MAA1 is low, the central processing unit chip operation is under pattern, and corresponding system board also is operated under pattern; The SYSEN# signal is introduced in the field programmable gate array chip in the system board simultaneously, the control backup starts address, the data bus of chip, when system board is operated in the holotype plate, address, data bus that backup starts chip are logical, when system board was operated in from pattern, address, data bus that backup starts chip were high-impedance state.
5, the system board of using as claim 1,4 described embedded computer systems, it is characterized in that described field programmable gate array chip finishes auxiliary logic, comprise described flash memory chip, start the driving of chip, X port address, control bus; Simultaneously described startup chip and X port be+the 5V chip, described system board utilize the LVTTL level of 5V Tolerance characteristic realization+3.3V of field programmable gate array chip same+conversion of the HCMOS level of 5V; And on the integrated circuit board of startup boot outside system board of described system board redundancy backup is arranged, active and standby part of boot takies identical physical space, field programmable gate array chip is according to steering logic, the system board that guarantees only to be operated under the holotype uses the X port function, and the system board that also only is under the holotype can use the backup boot.
6, the system board used of embedded computer system as claimed in claim 1, it is characterized in that, the storage space at random of described central processing unit chip is the 64M address space, data width is 64+8 ECC verifications, the data bus of central processing unit chip directly is connected with the data bus of synchronous DRAM chip, address bus must can be selected the frequency of operation of SDRAM through being connected with the address bus of synchronous DRAM (SDRAM) behind the 10 Ω resistor chains by configuration pin.
7, the system board used of embedded computer system as claimed in claim 1, it is characterized in that, a 1553B Bus Interface Chip is arranged on the described CPU board, this interface chip is to pass through pci bus with being connected of described central processing unit chip, be integrated with the PCI bridge at chip internal, pci signal is converted to local signal, then by the 1553B bus, mainboard and external system just can be carried out communication, as long as power supply is provided, described system board carries out communication by 1553B bus and external unit, becomes a single board computer.
8, the system board used of embedded computer system as claimed in claim 1 is characterized in that described system board has adopted MPC8240 series CPU as the central processing unit chip.
9, the system board used of embedded computer system as claimed in claim 1 is characterized in that described system board satisfies COMPACT PCI 3U standard or COMPACT PCI 6U standard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200320122195 CN2662316Y (en) | 2003-11-28 | 2003-11-28 | System mainboard for embedded computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200320122195 CN2662316Y (en) | 2003-11-28 | 2003-11-28 | System mainboard for embedded computer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2662316Y true CN2662316Y (en) | 2004-12-08 |
Family
ID=34348559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200320122195 Expired - Lifetime CN2662316Y (en) | 2003-11-28 | 2003-11-28 | System mainboard for embedded computer system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2662316Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107832010A (en) * | 2009-04-08 | 2018-03-23 | 谷歌有限责任公司 | Data storage device |
-
2003
- 2003-11-28 CN CN 200320122195 patent/CN2662316Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107832010A (en) * | 2009-04-08 | 2018-03-23 | 谷歌有限责任公司 | Data storage device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN201171129Y (en) | Switching device | |
| CN102236381B (en) | Reinforced computer based on Loongson 3A processor | |
| CN108491039B (en) | Multiplexing type hard disk backboard and server | |
| CN1908885A (en) | Static memorizer interface device and data transmitting method thereof | |
| CN101571743B (en) | Power management method for main board and display card thereof | |
| CN1284060C (en) | System mainboard for embedded computer systems | |
| CN1321381C (en) | Ebedded computer system | |
| CN101042672A (en) | High speed emulator used for digital signal processor and operation method thereof | |
| CN101046780A (en) | Computer system and input/output plate | |
| CN201518112U (en) | Major-minor interface type mainboard | |
| CN203812171U (en) | CDN server under ARM architecture | |
| CN2662316Y (en) | System mainboard for embedded computer system | |
| CN102521200A (en) | System for configuring multi-processor in single Flash in embedded manner | |
| CN200983160Y (en) | Wireless adapter multi-purpose interface circuit based on PCI bus | |
| CN113485960A (en) | General platform and computer based on FT-2000-4 | |
| CN1284061C (en) | Power supply / control panel for embedded computer systems | |
| CN205318376U (en) | Hot wall mainboard is prevented to giga based on explain 411 majestic treaters | |
| CN212433755U (en) | Modular small-size and multi-type data interface processing device | |
| CN2672734Y (en) | Power/control panel for embedded computer system | |
| CN204189089U (en) | A kind of server | |
| CN2694339Y (en) | Embedded computer system adapted for aerospaceplane | |
| CN107145213A (en) | A kind of device and method being multiplexed for PCH MEdebug and USB port | |
| CN1152315C (en) | Double-bus industrial control computer and its control method | |
| CN200983161Y (en) | Multi-function circuit based on PCI bus | |
| CN213934866U (en) | Adapter card with solid state disk interface and server |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20031128 |
|
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20031128 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |