CN2655520Y - Delay circuit for controlling IPM dead zone time of air conditioner - Google Patents
Delay circuit for controlling IPM dead zone time of air conditioner Download PDFInfo
- Publication number
- CN2655520Y CN2655520Y CN 03268534 CN03268534U CN2655520Y CN 2655520 Y CN2655520 Y CN 2655520Y CN 03268534 CN03268534 CN 03268534 CN 03268534 U CN03268534 U CN 03268534U CN 2655520 Y CN2655520 Y CN 2655520Y
- Authority
- CN
- China
- Prior art keywords
- circuit
- ipm
- input
- capacitor
- air conditioner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The utility model provides a time delaying circuit for controlling the dead zone time of an air conditioner IPM, characterized in that the circuit comprises an integral logic OR-gate circuit, and a charging and discharging circuit formed by a resistance R and a capacitor C which are connected in serial, wherein an input end A of the OR-gate circuit is connected with a control signal of a CPU output and is connected with one end of the resistance R, the other end of the resistance R is connected with the input end B of the OR-gate circuit and is connected to one end of the capacitor C, and the other end of the capacitor C is connected with a work power field. The output end of the OR-gate is used to connect the IPM control signal input end. The choice of different resistances and capacitor values can get different delaying time, namely the IPM dead zone time to meet the different demands of IPM. The circuit is simple, the adjustment is convenient and easy to perform, and the cost is low.
Description
Technical field
The utility model is a kind of delay circuit, specifically, is a kind of delay circuit of controlling air conditioner IPM Dead Time, relates to the improvement of air conditioner circuit, belongs to air conditioner and makes the field.
Background technology
Used power model IPM is a kind of multichannel integrated device in the air conditioner, there is the dead band in its response time, also promptly: do the time spent simultaneously when a plurality of control signals of sending into IPM and can burn out IPM, therefore, each control signal need be delayed time, and guarantees that the delay time that IPM does not damage is called Dead Time.The time-delay of control signal is realized by software usually before the utility model is made, the software engineer just will consider the IPM Dead Time and it is write into Control Software when software design, but owing to different IPM is not quite similar to the requirement of Dead Time length, a plurality of versions will appear in software like this, be not easy to management, and influence MASK (mask) work of CPU.For the uniformity of Control Software, the software engineer who has is put into Dead Time among the E2 of the outer expansion of chip, to the IPM of different company, only need change the data among the E2, coupling that can the simple realization Dead Time.The shortcoming of this method is to have increased production cost, is subjected to certain limitation when practical application.
Summary of the invention
The purpose of this utility model is exactly to provide a kind of delay circuit of controlling air conditioner IPM Dead Time at the deficiency that prior art exists, and adopts simple hardware circuit to realize Dead Time, and delay time is convenient adjustable, easily implements, cost is low.
The purpose of this utility model is achieved through the following technical solutions:
A kind of delay circuit of controlling air conditioner IPM Dead Time, it is characterized in that: circuit is made of integrated logic sum gate circuit and charge-discharge circuit, an input A of integrated logic sum gate circuit connects the control signal of CPU output, and be connected with the input of charge-discharge circuit, another input B of integrated logic sum gate circuit is connected with the output of charge-discharge circuit, and the output of integrated logic sum gate circuit is used to connect IPM signal input end mouth.
Described charge-discharge circuit is made of resistance R and capacitor C series connection, one end of resistance R connects the input A of integrated logic sum gate circuit, the other end of resistance R connects the input B of integrated logic sum gate circuit, also is connected to an end of capacitor C, and the other end of capacitor C connects working power ground.
The input port of described integrated logic sum gate circuit is 2 when above, and no port connects working power ground.
Advantage of the present utility model and good effect be, the circuit that adopts the simple appliances part to form has been realized the control and the adjusting of air conditioner IPM Dead Time, has guaranteed the complete sum unanimity of air conditioner Control Software, and delay time is easy to adjust, easily implements, cost is low.
Description of drawings
Accompanying drawing 1 is the line map of an embodiment of the utility model;
Accompanying drawing 2 is working timing figures of an embodiment of the utility model.
Embodiment
Referring to Fig. 1, a kind of delay circuit of controlling air conditioner IPM Dead Time, it is characterized in that: circuit by integrated logic sum gate circuit 1 (hereinafter to be referred as: OR circuit 1) and by the charge-discharge circuit 2 that the series connection of resistance R and capacitor C constitutes form, an input A of OR circuit 1 connects the control signal of CPU output, and be connected with an end of resistance R, the other end of resistance R connects the input B of OR circuit 1, also is connected to an end of capacitor C, and the other end of capacitor C connects working power ground.The output of OR circuit 1 is used to connect IPM signal input end mouth.
In accompanying drawing 1, OR circuit 1 has 2 input A and B, and agreement IPM control signal low level is effective.The control signal of CPU output at ordinary times is in high level, and the A end of OR circuit 1 is high level, and output C end is high level, and IPM imports locking.When the CPU output low level, electric capacity is by conductive discharge, and the input pin B of OR circuit 1 still keeps high level, and OR circuit 1 output C end still is a high level, still locking of IPM input.When capacitor discharge finishes, when the input pin B of OR circuit 1 became low level, output C end just be a low level, and IPM control input is effective, and therefore, capacitor discharge time is exactly that CPU exports control signal and effectively arrives the effective delay time of IPM input control signal.When the control signal of CPU output became high level again, although electric capacity is in charged state and make OR circuit 1 input pin B be in low level, output C still became high level immediately, locking IPM input.
Suitably select the value of resistance, electric capacity, just can make delay time equal the IPM Dead Time, delay time designs more biggerly than IPM Dead Time in actual use, to improve the reliability of system.
Foregoing circuit is wherein one tunnel of six road IPM control input, and other five the tunnel do same processing, by adjusting the parameter of R, C, just can obtain different delay times to satisfy the needs of different IP M.
The input port of described integrated logic sum gate circuit 1 is 2 when above, and no port connects working power ground.
Claims (3)
1, a kind of delay circuit of controlling air conditioner IPM Dead Time, it is characterized in that: circuit is made of integrated logic sum gate circuit (1) and charge-discharge circuit (2), an input A of integrated logic sum gate circuit (1) connects the control signal of CPU output, and be connected with the input of charge-discharge circuit (2), another input B of integrated logic sum gate circuit (1) is connected with the output of charge-discharge circuit 2, and the output of integrated logic sum gate circuit (1) is used to connect IPM signal input end mouth.
2, the delay circuit of control air conditioner IPM Dead Time according to claim 1, it is characterized in that: described charge-discharge circuit (2) is made of resistance R and capacitor C series connection, one end of resistance R connects the input A of integrated logic sum gate circuit (1), the other end of resistance R connects the input B of integrated logic sum gate circuit (1), also be connected to an end of capacitor C, the other end of capacitor C connects working power ground.
3, the delay circuit of control air conditioner IPM Dead Time according to claim 1 and 2 is characterized in that: the input port of described integrated logic sum gate circuit (1) is 2 when above, and no port connects working power ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03268534 CN2655520Y (en) | 2003-06-26 | 2003-06-26 | Delay circuit for controlling IPM dead zone time of air conditioner |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03268534 CN2655520Y (en) | 2003-06-26 | 2003-06-26 | Delay circuit for controlling IPM dead zone time of air conditioner |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2655520Y true CN2655520Y (en) | 2004-11-10 |
Family
ID=34330129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03268534 Expired - Fee Related CN2655520Y (en) | 2003-06-26 | 2003-06-26 | Delay circuit for controlling IPM dead zone time of air conditioner |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2655520Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103872884A (en) * | 2014-03-24 | 2014-06-18 | 美的集团股份有限公司 | Intelligent power module |
| CN110138194A (en) * | 2019-06-25 | 2019-08-16 | 北京机械设备研究所 | A kind of anti-short-circuit dead-zone circuit of bridge drive circuit control direction commutation |
-
2003
- 2003-06-26 CN CN 03268534 patent/CN2655520Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103872884A (en) * | 2014-03-24 | 2014-06-18 | 美的集团股份有限公司 | Intelligent power module |
| CN103872884B (en) * | 2014-03-24 | 2016-07-20 | 美的集团股份有限公司 | Spm |
| CN110138194A (en) * | 2019-06-25 | 2019-08-16 | 北京机械设备研究所 | A kind of anti-short-circuit dead-zone circuit of bridge drive circuit control direction commutation |
| CN110138194B (en) * | 2019-06-25 | 2020-07-17 | 北京机械设备研究所 | Short circuit dead zone circuit is prevented in bridge type drive circuit control direction switching-over |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106535412B (en) | The digital simulation light adjusting circuit that a kind of port shares | |
| CN102739490A (en) | Multi-channel synchronous Ethernet expansion system based on peripheral component interface express (PCIe) bus | |
| CN2655520Y (en) | Delay circuit for controlling IPM dead zone time of air conditioner | |
| CN103716031A (en) | Non-polarity RS485 interface circuit conversion rate enhancement method and circuit | |
| WO2023108958A1 (en) | Power amplification circuit based on envelope tracking technology and doherty architecture, and design method therefor | |
| CN206620101U (en) | Microwave power amplifier pulse control circuit | |
| CN201149654Y (en) | Single-chip I/O mouth time-sharing multiplexing control circuit | |
| CN201118434Y (en) | Dual PWM mixed cutting wave control circuit | |
| CN204794929U (en) | Intelligence power module high reliability border pulse -generating circuit | |
| CN107437894B (en) | Overvoltage protection | |
| CN205195730U (en) | Real -time ethernet etherCAT slave station system | |
| CN210402328U (en) | Serial port extension circuit based on USB interface | |
| CN107104580A (en) | A kind of parallel system Balance route departure obtains circuit | |
| CN208461727U (en) | A kind of current-limiting control circuit applied to motor | |
| CN209844932U (en) | Digital circuit for filtering signal burrs | |
| CN207560022U (en) | A kind of embedded server Digital reference service applied to network optimization transmission | |
| CN206331375U (en) | A kind of energy-saving control circuit suitable for computer | |
| CN202033741U (en) | Program download device for STC single-chip microcomputer | |
| CN201789511U (en) | RS485 distributor | |
| CN109617541A (en) | One kind being used for mass spectrographic pulse delay width modulation circuit | |
| CN200953558Y (en) | Electric source wire chopping communication transmitting-receiving circuit | |
| CN204302718U (en) | A kind of enhancement mode communication control interface module | |
| CN213069800U (en) | Multichannel serial port expansion module based on FPGA (field programmable Gate array) parallel bus | |
| CN103049418A (en) | Symmetric non-flip-flop K-RS232 converter | |
| CN209233804U (en) | A kind of DC-6GHz temperature control attenuator circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: HISENSE( SHANDONG ) AIR CONDITIONING CO., LTD. Free format text: FORMER OWNER: QINGDAO HISENSE AIR CONDITIONING CO. Effective date: 20080425 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20080425 Address after: Seven floor, Hisense building, 17 East Sea Road, Shandong, Qingdao: 266071 Patentee after: Hisense (Shandong) Air-Conditioning Co., Ltd. Address before: Seven floor, Hisense building, 17 East Sea Road, Shandong, Qingdao: 266071 Patentee before: Haisense Air Conditioner Co., Ltd., Qingdao |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20041110 Termination date: 20120626 |