CN2651841Y

CN2651841Y - Protector of CPU external bus

Info

Publication number: CN2651841Y
Application number: CN 200320102609
Authority: CN
Inventors: 暴亮
Original assignee: Harbour Networks Holdings Ltd
Current assignee: Harbour Networks Holdings Ltd
Priority date: 2003-10-31
Filing date: 2003-10-31
Publication date: 2004-10-27
Anticipated expiration: 2013-10-31

Abstract

The utility model discloses a protector of a CPU external bus, which comprises a control monoboard connected with a CPU, wherein a control chip is arranged in the control monoboard comprises and is connected with the CPU through the CPU external bus. A counter is arranged on a CPU interface of the control chip, the initial values of the counter are set by the CPU, and the time counted from the initial values to overflow is more than the corresponding read-write time of the control chip. When the control chip receives read-write commands of the CPU, the counter starts to count, and an output electrical level turns over simultaneously. A chip selector OE of the control chip is turned on, and the control chip performs the read-write commands. When the counter overflows, the output electrical level turns over again, and the chip selector OE of the control chip is turned off. The internal data of the control monoboard connected with the CPU through the bus is effectively protected by the utility model, and the safety of systems is greatly improved.

Description

The protective device of CPU external bus

Technical field:

The utility model relates to a kind of protective device of CPU external bus.

Background technology:

CPU (central processing unit) adopts the mode of memory bus interface to carry out to the control of peripheral hardware veneer basically, or PCI local bus interface such as (peripheral controller interfaces).But PCI (peripheral controller interface) implements the comparison difficulty with respect to memory interface, and complexity increases greatly, and performance is limited again simultaneously.Therefore in the veneer control mode system of embedded system, still based on memory interface, the application of PCI is more limited.

As shown in Figure 1, the external address control bus not only comprises address bus, also comprise the chip selection signal line that is used for gating external unit veneer, when the major function of veneer is CPU (central processing unit) when finishing, so whole veneer also resets together if CPU (central processing unit) crashes.But the major function of veneer is not that CPU (central processing unit) finishes sometimes, CPU (central processing unit) is just auxiliary to be calculated, and the execution configuration effort, CPU (central processing unit) crashes so should not influence the operate as normal of the main ASIC of this plate (special IC) controller when resetting.Such situation is such as the cross board of SDH (formatted data processing), cross matrix information in CPU (central processing unit) inner preservation of cross chips when resetting also keeps, CPU (central processing unit) also keeps the state machine information before crashing in NVRAM, therefore CPU (central processing unit) can't influence its interleaving function after resetting, only influence cross-over configuration during this period of time.But CPU (central processing unit) might send chaotic sequential on bus when deadlock resets, distribute data arbituarily, this just might influence the safety of outside important ASIC (special IC) controller internal data, therefore be necessary to be provided with a kind of security mechanism, when bus writes without basis data, influence the data of outside important ASIC (special IC) controller inside when preventing the CPU program fleet.

At the problems referred to above, general a kind of way is now, utilize an important sheet of trigger control to translate the output of sign indicating number selectively, when need be before important ASIC (special IC) controller reads and writes data, at first write the control trigger, order control trigger is turned to the state of ON, passes through with regard to the chip selection signal that allows this ASIC (special IC) controller like this.When the reading and writing data of ASIC (special IC) controller is finished, write the control trigger again, make its state that is turned into OFF, the sheet choosing output of this ASIC (special IC) controller is turn-offed.Such control mode has improved the security of ASIC (special IC) controller internal data greatly, has prevented data tampering unintentionally.But it also has a tangible leak, after CPU (central processing unit) has opened the control trigger, if the data to ASIC (special IC) controller do not have to have read and write under the situation about just crashing the state that the control trigger will be held open always.The no sequential signal that occurs on the bus when resetting as CPU (central processing unit) just might cause fatal infringement to the internal data of ASIC (special IC) controller like this, thereby has also reduced the reliability of total system.

The utility model content:

At the existing problem and shortage of protective device of above-mentioned CPU (central processing unit) external bus, the purpose of this utility model provides the protective device of a kind of more effective CPU (central processing unit) external bus.

The utility model is achieved in that the protective device of a kind of CPU (central processing unit) external bus, include the control veneer that is connected with CPU (central processing unit), comprise control chip in this control veneer, this control chip is connected with CPU (central processing unit) by CPU (central processing unit) external bus, and the CPU of described control chip (central processing unit) interface is provided with counter; The initial value of counter is set by CPU (central processing unit), count down to time of overflowing corresponding access time greater than control chip from initial value; When control chip was received the read write command of CPU (central processing unit), counter began counting, output level upset simultaneously, and the sheet of control chip selects OE (output starts) to open, and control chip is carried out read write command; After counter overflowed, output level overturn once more, and the sheet of control chip selects OE (output starts) to keep closing.

Further, described counter is up counter or down counter.

Further, the CPU of described control chip (central processing unit) interface is provided with counter and specifically is connected with the OE (output startup) of the sheet choosing of described control chip for the output of described counter.

The utility model is by being provided with counter on CPU (central processing unit) interface of the control chip of controlling veneer, at CPU (central processing unit) when control chip sends read write command, judge the length that this desires to read and write data simultaneously, and calculate CPU (central processing unit) and normally read and write the time that these data need spend, and counter set corresponding initial value, this initial value specifically is to set like this: counter begins slightly to be longer than CPU (central processing unit) to the time of overflowing from counting and has has normally read and write the time that these data need spend; Counter begins counting after being set initial value, and output level is turned to ON simultaneously, and selects OE (output starts) to open the sheet of control chip, and CPU (central processing unit) sends read write command simultaneously, and control chip is carried out this read write command; Counter overflows the back output level and is turned to OFF, selects OE (output starts) to close the sheet of described control chip; Whether CPU (central processing unit) judgment data is read and write and is finished, if do not finish, reset the initial value of described counter, make this initial value to the time of overflowing greater than overflowing the time last time, counter restarts counting, and CPU (central processing unit) reads and writes these data again.Like this, can protect the internal data of the control veneer that is connected by bus with CPU (central processing unit) effectively, even on bus, send chaotic sequential when resetting or distribute data arbituarily in CPU (central processing unit) deadlock suddenly, because counting after CPU (central processing unit) handles the read write command of controlling veneer, counter overflows, and the sheet that will control the control chip of veneer selects OE (output starts) to close, chaotic sequential and the data of distributing arbituarily can not have influence on the data with existing in the control chip, control chip is by existing data fill order, like this, whole one-tenth system is just more stable; Even CPU (central processing unit) is not is not reading and writing just deadlock of data, because the initial value that counter is composed is less relatively to overflow value, overflow at the cpu reset hour counter, and the sheet of control chip has been selected OE (output starts) to close, do not affect the internal data of control chip equally; The utility model has promoted the security of system greatly.

Description of drawings:

Below in conjunction with accompanying drawing, the utility model is made detailed description.

Fig. 1 is the CPU control structure synoptic diagram of prior art;

Fig. 2 structure principle chart of the present utility model;

The counting principle figure of Fig. 3 the utility model counter.

Embodiment:

As shown in Figure 2, the utility model comprises the control veneer that is connected with CPU, comprises control chip ASIC in this control veneer, and control chip ASIC is connected with CPU by the CPU external bus, and the sheet of control chip ASIC selects and is connected with counter on the OE.As shown in Figure 3, counter is in counting process, and the level of its output is low, but not under the count status, its output level is high, at counter in counting process, because its output is low level, the sheet that promptly is equivalent to asic chip selects OE to open, and CPU can carry out read-write operation to asic chip, if under the non-count status, what counter was exported is high level, and the sheet of asic chip selects OE to close, and CPU just can't operate it, certainly, invalid data just can not disturb asic chip.Even CPU crashes suddenly in the rolling counters forward process, but when CPU was restarted, counter was counted already and is finished, and promptly the sheet of asic chip selects OE to close already, also can not have influence on asic chip.Particularly important asic chip is a comparison safety with this structure protects.

Principle of work of the present utility model is such: CPU judges the size of desiring to read and write data, and judge in view of the above controlling the corresponding access time of asic chip of veneer, and the corresponding initial value that counter is set, counter from counting begin to the time of overflowing greater than the access time of CPU to asic chip; Counter begins counting, and output level overturns simultaneously, and selects OE to open the sheet of asic chip; CPU sends read write command to asic chip, and asic chip is carried out this read write command; Rolling counters forward finishes, and output level upset selects OE to close the sheet of asic chip.When the maximum count time of setting was not enough, when promptly not finishing the business configuration to asic chip, CPU can prolong the read-write permission time by the counting initial value of resetting, and finishes up to configuration.

Consider that the configuration amount to asic chip might be bigger, the maximum count time of therefore setting counter is 2 milliseconds.Here, counter is up counter or down counter.

Claims

1. the protective device of a CPU external bus, include the control veneer that is connected with CPU, comprise control chip in this control veneer, this control chip is connected with CPU by the CPU external bus, it is characterized in that the cpu i/f of described control chip is provided with counter; The initial value of counter is set by CPU, count down to time of overflowing corresponding access time greater than control chip from initial value; When control chip was received the read write command of CPU, counter began counting, output level upset simultaneously, and the sheet of control chip selects OE to open, and control chip is carried out read write command; After counter overflowed, output level overturn once more, and the sheet of control chip selects OE to keep closing; Whether the CPU judgment data is read and write finishes, if do not finish, resets the initial value of described counter, this initial value to the time of overflowing greater than overflowing the time last time.

2. the protective device of CPU external bus as claimed in claim 1 is characterized in that, described counter is up counter or down counter.

3. the protective device of CPU external bus as claimed in claim 1 is characterized in that, the cpu i/f of described control chip is provided with counter and specifically is connected with the OE of the sheet choosing of described control chip for the output of described counter.