CN2648599Y - Radiating fin for semiconductor packaged element - Google Patents
Radiating fin for semiconductor packaged element Download PDFInfo
- Publication number
- CN2648599Y CN2648599Y CN 03207199 CN03207199U CN2648599Y CN 2648599 Y CN2648599 Y CN 2648599Y CN 03207199 CN03207199 CN 03207199 CN 03207199 U CN03207199 U CN 03207199U CN 2648599 Y CN2648599 Y CN 2648599Y
- Authority
- CN
- China
- Prior art keywords
- fin
- metal plate
- lug boss
- support arm
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The utility model relates to a fin of a semiconductor packing part, in particular to a metal plate with a salient in the centre. A plurality of openings is arranged in circle in the side wall of the central salient of the metal plate. A supporting arm is positioned in every opening and stretches downward from the superface of the salient of the metal plate. The supporting arm can stretch and be connected with the metal plate or stretch to the same flat of the underside of the metal plate and the supporting arm is connected with the metal plate into an integral forming. The utility model has the function of enhancing the holding power of the fin, thereby preventing the deformation of the fin caused by the pressure of the mold flow and pressing when in the process of die and improving the disadvantages of the loss of radiating effect caused by the mold flow overflowing into the pressing surface of the die cavity and no beautiful appearance.
Description
Technical field
The utility model relates to a kind of fin of semiconductor package part, particularly a kind of fin that strengthens support force by support arm.
Background technology
Evolution along with the manufacture of semiconductor technology, the density of integrated circuit constantly increases, from the early stage one chip less than ten transistors, to today one chip promptly have up to ten million transistors, so high transistor density will certainly cause problems such as heat radiation is difficult for, the fractal key so relevant heat dissipation design heals.
In the encapsulation procedure of integrated circuit, for example plastic ball grid array (Plastic Ball Grid Array) encapsulation, often have and add metal fin to strengthen the design of heat dissipation, as shown in Figures 1 and 2, be respectively a known fin and known semiconductor package part with heat sink design, this fin is the metallic plate 10 of a center projections, the bottom surface of this metallic plate 10 is arranged on the base plate for packaging 16, center projections portion 12 then with chip 18 and go between 20 be placed in, and outside the end face of these metallic plate 10 center projections portions 12 is revealed in, when carrying out the pressing mold processing procedure, utilize a patrix die cavity to press the end face of being located at this center projections portion 12, to prevent that mould stream thing 22 from overflowing between die cavity and the fin, makes center projections portion 12 end faces expose, with the radiating effect that increases by this.
Yet in the encapsulation procedure of known tool built-in type fin, for alleviating wire sweep (wire sweep) effect that is caused when the pressing mold, can around metallic plate 10 center projections portions 12, offer a plurality of guided mode stream openings 14 by sidewall, as shown in Figures 1 and 2, yet this design can cause the fin support force to weaken, make mould stream thing 22 clamp-on the stitching surface of die cavity and fin by stamping pressure, the surface attachment that causes fin to expose has the mould stream thing 22 that overflows into, thereby radiating effect and outward appearance impacted, shown in Fig. 2 and Fig. 2 A.
Summary of the invention
Main purpose of the present utility model provides a kind of fin of tool support arm, uses the support force that increases fin, and prevents that mould stream thing from overflowing between die cavity and the fin, and causes defectives such as heat dissipation loss and external form are not attractive in appearance.
The purpose of this utility model is achieved in that a kind of fin of semiconductor package part, it is characterized in that having the metallic plate of center projections portion, sidewall is equipped with plurality of openings around the described lug boss, one support arm is located in each described opening, and is extended downwards by the end face of described lug boss.
Wherein each described support arm is extended downwards by the end face of described lug boss and is linked to described metallic plate.The end face and the root edge of wherein said support arm and described lug boss are one-body molded.Wherein each described support arm extends downward bottom surface copline with described metallic plate by the end face of described lug boss.
When carrying out the pressing mold processing procedure, support arm can provide extra support force, make fin not yielding and with the die cavity fluid-tight engagement, overflow into the stitching surface of fin and die cavity and influence fin heat dissipation and outward appearance so can prevent mould stream thing mat stamping pressure.
Description of drawings
Fig. 1 is known fin schematic diagram with guided mode stream opening;
Fig. 2 is known semiconductor package part schematic diagram with heat sink design;
Fig. 2 A is the partial enlarged drawing of Fig. 2;
Fig. 3 is a stereogram of the present utility model;
Fig. 4 is a vertical view of the present utility model;
Fig. 5 is an embodiment schematic diagram of the present utility model;
Fig. 5 A is the partial enlarged drawing of Fig. 5;
Fig. 6 is another embodiment schematic diagram of the present utility model;
Fig. 6 A is the partial enlarged drawing of Fig. 6.
Description of reference numerals:
10 metallic plates; 12 lug bosses; 14 openings; 16 base plate for packaging; 18 chips; 20 lead-in wires;
22 moulds stream thing; 30 metallic plates; 32 lug bosses; 34 openings; 36 support arms; 38 base plate for packaging;
40 chips; 42 lead-in wires; 44 moulds stream thing; 46 support arms.
Embodiment
The effect that describes the purpose of this utility model, technology contents, characteristics in detail and reached with instantiation below in conjunction with accompanying drawing.
The utility model is a kind of fin of semiconductor package part, is that a kind of tool support arm overflows into the fin on surface to prevent mould stream thing.
Fig. 3 to Fig. 5 is stereogram of the present utility model, vertical view and embodiment schematic diagram in regular turn.Fin of the present utility model is that central authorities raise up and form the metallic plate 30 of a lug boss 32, this metallic plate 30 is arranged on the base plate for packaging 38, be equipped with chip 40 in the center projections portion 32 and go between 42, sidewall then is equipped with a plurality of guided mode stream openings 34 around the lug boss 32, the wire sweep effect of these a plurality of guided modes stream openings 34 when alleviating the pressing mold processing procedure, other has a support arm 36 to be located in each guided mode stream opening 34, this support arm 36 is linked on the metallic plate 30 by the extension downwards of lug boss end face, and support arm 36 is formed in one with the connection relationship of metallic plate 30, shown in Fig. 5 A.
When carrying out the pressing mold processing procedure, one patrix die cavity can closely be pressed the end face of being located at this fin lug boss 32, prevent that by this mould slime flux from going into the stitching surface of patrix die cavity and fin, and and then prevent that mould stream thing 44 is attached to the end face of fin lug boss 32 and influences radiating effect and outward appearance, yet, because the stamping pressure during pressing mold can flow mould thing 44 and clamp-on between patrix die cavity and the fin, so the time provide extra support force by this support arm 36, can prevent that fin is out of shape because of stamping pressure, and avoid the end face of fin lug boss 32 to be covered by mould stream thing 44, use the loss that reduces the fin heat dissipation.
Fig. 6 and Fig. 6 A are another embodiment schematic diagram of the present utility model.Show semiconductor package part with heat sink design, this fin comprises a metallic plate 30, this metallic plate 30 is arranged on the base plate for packaging 38, and central authorities raise up and form a lug boss 32, these lug boss 32 inboards are equipped with chip 40 and go between 42, and sidewall is equipped with a plurality of guided mode stream openings on every side, one support arm 46 is located in each guided mode stream opening, each support arm 46 extends downward and metallic plate 30 bottom surface coplines by the end face of lug boss 32, that is extend to the surface of base plate for packaging 38, by this to obtain a stressed strong point.And when carrying out the pressing mold processing procedure, one patrix die cavity is pressed the end face of being located at fin lug boss 32, and the extra support power that provides by this support arm 46, prevent that fin is out of shape because of mould stream stamping pressure, so the end face of this lug boss 32 can not be attached with the mould stream thing 44 that overflows into, and then avoid the loss and the inaesthetic defective of external form of fin heat dissipation.
Claims (4)
1, a kind of fin of semiconductor package part is characterized in that having the metallic plate of center projections portion, and sidewall is equipped with plurality of openings around the described lug boss, and a support arm is located in each described opening, and is extended downwards by the end face of described lug boss.
2, the fin of semiconductor package part as claimed in claim 1, wherein each described support arm is extended downwards by the end face of described lug boss and is linked to described metallic plate.
3, the fin of semiconductor package part as claimed in claim 2, the end face and the root edge of wherein said support arm and described lug boss are one-body molded.
4, the fin of semiconductor package part as claimed in claim 1, wherein each described support arm extends downward bottom surface copline with described metallic plate by the end face of described lug boss.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03207199 CN2648599Y (en) | 2003-08-07 | 2003-08-07 | Radiating fin for semiconductor packaged element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03207199 CN2648599Y (en) | 2003-08-07 | 2003-08-07 | Radiating fin for semiconductor packaged element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2648599Y true CN2648599Y (en) | 2004-10-13 |
Family
ID=34324549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03207199 Expired - Lifetime CN2648599Y (en) | 2003-08-07 | 2003-08-07 | Radiating fin for semiconductor packaged element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2648599Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114582815A (en) * | 2022-05-05 | 2022-06-03 | 甬矽电子(宁波)股份有限公司 | Heat dissipation cover, packaging structure and manufacturing method of packaging structure |
-
2003
- 2003-08-07 CN CN 03207199 patent/CN2648599Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114582815A (en) * | 2022-05-05 | 2022-06-03 | 甬矽电子(宁波)股份有限公司 | Heat dissipation cover, packaging structure and manufacturing method of packaging structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20090109 Address after: Postcode of Hongkong Special Administrative Region of china: Patentee after: WEIYU SEMICONDUCTOR (HONGKONG) Co.,Ltd. Address before: Postcode of Taiwan, china: Patentee before: VATE TECHNOLOGY CO.,LTD. |
|
| ASS | Succession or assignment of patent right |
Owner name: WEIYU SEMICONDUCTOR HONGKONG CO., LTD. Free format text: FORMER OWNER: LIWEI SCIENCE AND TECHNOLOGY CO., LTD. Effective date: 20090109 |
|
| ASS | Succession or assignment of patent right |
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING (WEIHAI) CO., L Free format text: FORMER OWNER: ASE ASSEMBLY AND TEST (HONG KONG), LTD. Effective date: 20111124 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| C56 | Change in the name or address of the patentee |
Owner name: ASE ASSEMBLY AND TEST (HONG KONG), LTD. Free format text: FORMER NAME: WEIYU SEMICONDUCTOR (HONG KONG) CO., LTD. |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: HONG KONG, CHINA TO: 264205 WEIHAI, SHANDONG PROVINCE |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 000000 Hongkong Special Administrative Region of China Patentee after: Advanced packaging and testing (Hongkong) Co.,Ltd. Address before: 000000 Hongkong Special Administrative Region of China Patentee before: WEIYU SEMICONDUCTOR (HONGKONG) Co.,Ltd. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20111124 Address after: 264205 No. 16-1, Hainan Road, export processing zone, Weihai economic and Technological Development Zone, Shandong, China Patentee after: RIYUEGUANG SEMICONDUCTOR(WEIHAI) Co.,Ltd. Address before: Hongkong Special Administrative Region of China Patentee before: Advanced packaging and testing (Hongkong) Co.,Ltd. |
|
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20130807 Granted publication date: 20041013 |