CN2632940Y - High speed differential to monoterminal converter - Google Patents
High speed differential to monoterminal converter Download PDFInfo
- Publication number
- CN2632940Y CN2632940Y CN 03244025 CN03244025U CN2632940Y CN 2632940 Y CN2632940 Y CN 2632940Y CN 03244025 CN03244025 CN 03244025 CN 03244025 U CN03244025 U CN 03244025U CN 2632940 Y CN2632940 Y CN 2632940Y
- Authority
- CN
- China
- Prior art keywords
- mentioned
- metal oxide
- oxide semiconductor
- semiconductor transistor
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The utility relates to a converter which is capable of converting high-speed differential signals into single-ended signals and consists of a transduction amplifier, a current mirror, a buffer circuit and a resistance converting amplifier; wherein, the differential voltage signal is sent to the end of the transduction amplifier and is converted into a differential current signal; the current mirror and the buffer circuit then serve as senders for the differential current to the single-ended current and are used for separating the transduction amplifier from the resistance converting amplifier which is the later step of the current; finally, the single-ended current signal is sent to the input end of the resistance converting amplifier and converted into a single-ended voltage signal.
Description
Technical field
The utility model is about a kind of electronic circuit technology, particularly at a kind of complementary metal oxide semiconductors (CMOS) (CMOS)/two-carrier (bipolar)/differential commentaries on classics single-ended converter of two-carrier complementary metal oxide semiconductors (CMOS) (BiCMOS) (differential to single-ended converter) that does not need operational amplifier, in order to convert a differential wave to a single-ended signal.
Background technology
Differential form signals comprises a data-signal and inversion signal thereof, and it is widely used in the various analog circuits.Because its data-signal and inversion signal can cancel each other out, so differential wave are commonly used to get rid of noise and interference in the environment when being subjected to being referred to as the same noise of common-mode noise (common modenoise) and disturbing.Yet, differential wave in the use and the integrated circuit that is not suitable for having low pin number use, be the pin count that the single-ended signal comparison can effectively reduce integrated circuit on the contrary.Therefore, adopt a kind of differential commentaries on classics single-ended converter that is used for changing differential/single-ended signal at present mostly, can cooperate different practical application conditions.In addition, differential commentaries on classics single-ended converter also can be as an output buffer, in order to isolating internal circuit and outside output connection pad district, or as a data buffer, in order to isolate prime and to need back grade of single-ended input signal.
The differential commentaries on classics single-ended converter of tradition mostly is to adopt operational amplifier to make.Fig. 1 represents the circuit diagram of known differential commentaries on classics single-ended converter.As shown in Figure 1, transducer comprises an operational amplifier 10, is coupled to the resistance R 11 and the R21 of normal phase input end of operational amplifier 10 and resistance R 12 and the R22 that is coupled to the inverting input of operational amplifier 10.Data-signal in the differential wave is couple to the normal phase input end of operational amplifier 10 by resistance R 11; Its inversion signal is couple to the inverting input of operational amplifier 10 then by resistance R 12.Single-ended output signal Vout then sends from the output of the operational amplifier 10 that is couple to resistance R 21.
Yet therefore and be not suitable for the application of integrated circuit, because traditional differential commentaries on classics single-ended converter adopts operational amplifier can waste very big chip space, and can be subjected to the restriction on the speed.
United States Patent (USP) the 5th, 432 then discloses a kind of differential commentaries on classics single-ended converter that does not need operational amplifier No. 476.Fig. 2 represents to be exposed in United States Patent (USP) the 5th, 432, the block diagram of No. 476 differential commentaries on classics single-ended converter.As shown in Figure 2, differential input signal Vin delivers to input buffer 22.22 of input buffers are delivered to converter (V/Iconverter) 24 and 26 with data-signal among the differential wave Vin and inversion signal thereof respectively.Then, current mirror assembly 28 is then delivered in the output of converter 24.In addition, 30 of DC level setting apparatus are set up a direct current voltage level, and deliver to resistor assembly 32.At last, with the output of current mirror assembly 28, resistor assembly 32 and converter 26 in conjunction with producing single-ended output signal Vout.Though this known differential commentaries on classics single-ended converter does not use operational amplifier, yet has adopted too many resistance to realize its function.
In view of this, the purpose of this utility model then is to propose a kind of new differential commentaries on classics single-ended converter, can be under the situation that does not use operational amplifier, convert differential wave to single-ended signal, on realizing, circuit do not have United States Patent (USP) the 5th, 432, No. 476 problem simultaneously yet.
According to above-mentioned purpose, the utility model provides a kind of differential commentaries on classics single-ended converter, and it comprises:
One transduction amplifier (transconductance amplifier) links to each other with a differential voltage signal, and above-mentioned differential voltage conversion of signals is become differential current signal, and wherein above-mentioned transduction amplifier has a degeneration resistance;
One current mirror and buffer circuit (current mirror and buffer circuit) are coupled to above-mentioned transduction amplifier, are an one-terminal current signal in order to transmit above-mentioned differential current signal; And
One changes impedance amplifier (transimpedance amplifier), be coupled to above-mentioned current mirror and buffer circuit, in order to receive above-mentioned one-terminal current signal and above-mentioned one-terminal current conversion of signals is become single-ended voltage signal, wherein above-mentioned commentaries on classics impedance amplifier has a feedback resistance in parallel.Wherein above-mentioned current mirror and buffer circuit provide the isolation between above-mentioned transduction amplifier and above-mentioned commentaries on classics impedance amplifier.
The gain of above-mentioned differential commentaries on classics single-ended converter is determined with the resistance value of above-mentioned feedback resistance in parallel by above-mentioned degeneration resistance.
Above-mentioned transduction amplifier comprises:
First and second metal oxide semiconductor transistor, its grid links to each other with above-mentioned differential voltage signal, the above-mentioned differential current signal of its drain electrode output;
One degeneration resistance, it is coupled to the source electrode of above-mentioned first and second metal oxide semiconductor transistor; And
The the 3rd and the 4th metal oxide semiconductor transistor, its drain electrode is respectively coupled to the source electrode of above-mentioned first and second metal oxide semiconductor transistor, and its source electrode is coupled to first power end, and its grid then receives first bias voltage.
Above-mentioned current mirror and buffer circuit comprise:
The the 5th and the 6th metal oxide semiconductor transistor, its grid links to each other with second bias voltage, and its source electrode couples the second source end, and its drain electrode links to each other with above-mentioned differential current signal;
The the 7th and the 8th metal oxide semiconductor transistor, its grid links to each other with one the 3rd bias voltage, and its source electrode is coupled to the above-mentioned the 5th and the drain electrode of the 6th metal oxide semiconductor transistor respectively;
The 9th metal oxide semiconductor transistor, its drain and gate is coupled to the drain electrode of above-mentioned the 7th metal oxide semiconductor transistor, and its source electrode is coupled to first power end; And
The tenth metal oxide semiconductor transistor, its grid is coupled to the drain electrode of above-mentioned the 7th metal oxide semiconductor transistor, its source electrode is coupled to above-mentioned first power end, and its drain electrode is coupled to the drain electrode of above-mentioned the 8th metal oxide semiconductor transistor and above-mentioned one-terminal current signal is provided.
Above-mentioned commentaries on classics impedance amplifier comprises:
The 11 metal oxide semiconductor transistor, its grid links to each other with above-mentioned one-terminal current signal, and its source electrode couples the second source end;
The 12 metal oxide semiconductor transistor, its grid is coupled to the grid of above-mentioned the 11 metal oxide semiconductor transistor, its source electrode is coupled to first power end, its drain electrode is coupled to the drain electrode of above-mentioned the 11 metal oxide semiconductor transistor, in order to above-mentioned single-ended voltage signal to be provided; And
One feedback circuit in parallel, its be coupled to the above-mentioned the 11 and the grid of the 12 metal oxide semiconductor transistor and drain electrode between.
The purpose of this utility model also is to provide a kind of differential commentaries on classics single-ended converter, and it comprises:
First and second power end;
First and second metal oxide semiconductor transistor, its grid links to each other with a differential voltage signal;
One degeneration resistance, it is coupled to the source electrode of above-mentioned first and second metal oxide semiconductor transistor; And
The the 3rd and the 4th metal oxide semiconductor transistor, its drain electrode is respectively coupled to the source electrode of above-mentioned first and second metal oxide semiconductor transistor, and its source electrode is coupled to above-mentioned first power end, and its grid then links to each other with first bias voltage.
The the 5th and the 6th metal oxide semiconductor transistor, its grid links to each other with second bias voltage, and its source electrode couples above-mentioned second source end, and its drain electrode couples the drain electrode of above-mentioned first and second metal oxide semiconductor transistor respectively;
The the 7th and the 8th metal oxide semiconductor transistor, its grid links to each other with the 3rd bias voltage, and its source electrode is coupled to the drain electrode of above-mentioned first and second metal oxide semiconductor transistor respectively;
The the 9th and the tenth metal oxide semiconductor transistor, its drain electrode is coupled to the above-mentioned the 7th and the drain electrode of the 8th metal oxide semiconductor transistor respectively, its grid is coupled to the drain electrode of above-mentioned the 9th metal oxide semiconductor transistor, and its source electrode is coupled to above-mentioned first power end;
The 11 metal oxide semiconductor transistor, its grid couples the drain electrode of above-mentioned the tenth metal oxide semiconductor transistor, and its source electrode couples above-mentioned second source end;
The 12 metal oxide semiconductor transistor, its grid is coupled to the drain electrode of above-mentioned the tenth metal oxide semiconductor transistor, and its source electrode is coupled to above-mentioned first power end, and its drain electrode is coupled to the drain electrode of above-mentioned the 11 metal oxide semiconductor transistor; And
One feedback circuit in parallel, its be coupled to the above-mentioned the 11 and the grid of the 12 metal oxide semiconductor transistor and drain electrode between;
Wherein the above-mentioned the 11 and the continuous drain electrode of the 12 metal oxide semiconductor transistor one single-ended output signal then is provided.
Above-mentioned first and second metal oxide semiconductor transistor, the above-mentioned the 3rd and the 4th metal oxide semiconductor transistor, the above-mentioned the 9th and the tenth metal oxide semiconductor transistor and the 12 metal oxide semiconductor transistor are the PMOS transistor; The the above-mentioned the 5th and the 6th metal oxide semiconductor transistor, the above-mentioned the 7th and the 8th metal oxide semiconductor transistor and above-mentioned metal oxide semiconductor transistor are nmos pass transistor.
The gain of above-mentioned differential commentaries on classics single-ended converter is determined with the resistance value ratio of above-mentioned feedback resistance in parallel by above-mentioned degeneration resistance.
The utility model has following advantage compared to existing technology:
The utility model changes impedance amplifier by a transduction amplifier, a current mirror and buffer circuit and and is formed.Wherein a differential voltage signal provides to the transduction amplifier input terminal, and converts a differential current signal to.Current mirror and buffer circuit are then sent device (currentconveyer) as a differential commentaries on classics one-terminal current, and in order to the transduction amplifier of isolation prime and the commentaries on classics impedance amplifier of back level.At last, the one-terminal current signal is then delivered to the input that changes impedance amplifier, and converts single-ended voltage signal to.
The entire gain of the differential commentaries on classics single-ended converter of the utility model is determined with the resistance value ratio of feedback resistance in parallel by degeneration resistance, because it is more or less freely to control two resistance ratios between resistance in manufacture of semiconductor, so this characteristic can be so that circuit design be more easy.
Description of drawings
Fig. 1 represents to use in the known technology circuit diagram of the differential commentaries on classics single-ended converter of operational amplifier.
Fig. 2 represents not use in the known technology block diagram of the differential commentaries on classics single-ended converter of operational amplifier.
Fig. 3 represents the block diagram of differential commentaries on classics single-ended converter among the utility model embodiment.
Fig. 4 represents the circuit diagram of differential commentaries on classics single-ended converter among the utility model embodiment.
Number in the figure is described as follows:
1～differential commentaries on classics single-ended converter; 2～transduction amplifier; 4～current mirror and buffer circuit;
6～commentaries on classics impedance amplifier; 10～operational amplifier; 22～buffer; 24,26～converter;
28～current mirror assembly; The accurate setting apparatus in 30～direct current position; 32～resistor assembly; Vin～differential voltage letter
Number; I1, I2～differential current signal; I3～one-terminal current signal; Vout～single-ended voltage signal.
Concrete execution mode
Fig. 3 represents the block diagram of differential commentaries on classics single-ended converter 1 among the utility model embodiment.Shown in Figure 3, differential commentaries on classics single-ended converter 1 comprises that a transduction amplifier 2, a current mirror and buffer circuit 4 and change impedance amplifier 6.Differential voltage signal Vin then delivers to transduction amplifier 2, in order to this differential voltage signal Vin is converted to differential current signal I1, the I2 of a correspondence.Then, differential current signal I1, I2 then are sent to the input of current mirror and buffer circuit 4.4 of current mirror and buffer circuits are to send device as a differential commentaries on classics one-terminal current, and in order to isolate transduction amplifier 2 and to change impedance amplifier 6.Send an one-terminal current signal I3 after current mirror and buffer circuit 4 are handled, and deliver to and change impedance amplifier 6, I3 converts single ended output voltage signal Vout to this one-terminal current signal.
In the disclosed conversion regime of the utility model, be the differential current signal that earlier a differential voltage conversion of signals is become a correspondence, utilize current mirror and buffer circuit 4 to change into an one-terminal current signal again, convert single-ended voltage signal at last again to.Current mirror and 4 of buffer circuits in intergrade can adopt collapsible current mirror framework (folded current mirror structure) to be realized, become the one-terminal current signal in order to the conversion differential current signal, and isolate its prime (transduction amplifier 2) and level (changeing impedance amplifier 6) thereafter.
Fig. 4 represents the circuit diagram of differential commentaries on classics single-ended converter 1 among the utility model embodiment, yet this circuit structure is not in order to limit the utility model, for knowing this skill person, differential commentaries on classics single-ended converter of the present utility model can also and change impedance amplifier and implement by other various transduction amplifiers, current mirror and buffer circuit.As shown in Figure 4, differential commentaries on classics single-ended converter is by PMOS transistor M1, M2, M3, M4, M9, M10 and M12, nmos pass transistor M5, M6, M7, M8 and M11, resistance R e and resistance R _ f.In the composition and the mode of operation of differential commentaries on classics single-ended converter shown in Figure 4, then cooperate the detailed description of Fig. 3 as follows.
PMOS transistor M1, M2, M3 and M4 and resistance R e formation one have the transduction amplifier of degradation frame, and it is corresponding to the transduction amplifier 2 shown in Fig. 3.The grid of PMOS transistor M1 and M2 receives differential voltage signal Vin.The source electrode of PMOS transistor M1 and M2 then is coupled to the drain electrode of PMOS transistor M3 and M4.The source electrode of PMOS transistor M3 and M4 and grid then are coupled to power end VDD and bias voltage Vb1 respectively.In addition, resistance R e is then as the source-electrode degradation resistance of PMOS transistor M1 and M2, and is coupled between the source electrode of PMOS transistor M1 and M2.Differential current signal I1, I2 are then provided by the drain electrode of PMOS transistor M1 and M2.Therefore, by the transduction value g of the transduction amplifier 2 that resistance value determined of source-electrode degradation resistance R e
m, can be expressed as:
G wherein
M1, m2The transduction value of expression transistor M1 and M2, R
EThe resistance value of expression degeneration resistance R e.
Nmos pass transistor M5, M6, M7 and M8 and PMOS transistor M9 and M10 then constitute current mirror shown in Figure 3 and buffer circuit 4.The grid of nmos pass transistor M5 and M6 is connected with each other, and provides bias voltage by bias voltage Vb2.The drain electrode of nmos pass transistor M5 and M6 and source electrode then are coupled to drain electrode and the earth terminal GND of PMOS transistor M1 and M2 respectively.In addition, the grid of nmos pass transistor M7 and M8 is connected with each other, and provides bias voltage by bias voltage Vb3, and its source electrode equally also is the drain electrode that is coupled to PMOS transistor M1 and M2.The drain electrode of nmos pass transistor M7 and M8 then is coupled to the drain electrode of PMOS transistor M9 and M10 respectively.PMOS transistor M9 and M10 are then as a current mirror, and its source electrode then is coupled to power end VDD.As shown in Figure 4, in order to electric current I 1 and the I2 that represents differential current signal, deliver to the contact of nmos pass transistor M5 and M7 and the contact of nmos pass transistor M6 and M8 respectively.In addition, in order to the electric current I 3 of representing the one-terminal current signal, then, deliver to next stage from the contact of nmos pass transistor M8 and PMOS transistor M10.Utilize collapsible framework to realize that current mirror and buffer circuit 4 can increase voltage amplitude and isolate adjacent two-stage.As mentioned above, a differential current signal I1, I2 are sent in the effect of current mirror and buffer circuit, become an one-terminal current signal I3.
Nmos pass transistor M11, PMOS transistor M12 and resistance R _ f then constitute a feedback amplifier circuit in parallel, and it is corresponding to commentaries on classics impedance amplifier 6 shown in Figure 3.The grid of nmos pass transistor M11 and PMOS transistor M12 is connected with each other, and is coupled to the drain contact of nmos pass transistor M8 and PMOS transistor M10.The drain electrode of nmos pass transistor M11 and PMOS transistor M12 also is connected with each other.The source electrode of nmos pass transistor M11 and PMOS transistor M12 then is coupled to earth terminal GND and power end VDD respectively.Resistance R _ f then is a feedback resistance in parallel, and it is coupled to grid and the drain electrode of nmos pass transistor M11 and PMOS transistor M12.Single-ended voltage signal Vout then is the drain contact output by nmos pass transistor M11 and PMOS transistor M12.Commentaries on classics resistance R by the commentaries on classics impedance amplifier 6 that resistance value determined of feedback resistance Rf in parallel
Zi, can be expressed as:
G wherein
M11+m12The transduction value of expression transistor M11 and M12 and, and R
FThe resistance value of representing feedback resistance Rf in parallel.
According to formula (1) and (2), the overall voltage gain A of differential commentaries on classics single-ended converter
VCan derive by following manner:
Approximate establishment condition in formula (3) is g
M1, m2＞＞1 and g
M11+m12＞＞1.Select the correct bias current can be so that g
M1, m2And g
M11+m12Obtain bigger numerical value, just can satisfy its approximate condition whereby.In differential commentaries on classics single-ended converter of the present utility model, overall voltage gain is that the resistance value ratio by resistance R e and resistance R _ f is determined.Therefore, the voltage gain that obtain accurate ratio need not use the resistance of big resistance value, so can save needed chip space on integrated circuit is realized.In addition, even exist under the situation of big process variation, still can keep the accuracy of voltage gain.
In order to keep the characteristic of input signal, the linearity (linearity) is considerable problem for differential commentaries on classics single-ended converter.In preferred embodiment of the present utility model, then be to have adopted the technology that load resistance is degenerated and parallel connection is fed back to obtain the preferable linearity.As mentioned above, output voltage swing can utilize the resistance ratios of degeneration resistance R e and feedback resistance Rf in parallel to be controlled.These two resistance can utilize passive component or driving component to realize along with different application.
At last, in the differential commentaries on classics single-ended converter in the present embodiment, owing to adopted current mirror and buffer circuit to isolate its front and back level, therefore the common-mode voltage and the single-ended output signal of input have nothing to do.In practical application, output signal is almost completely controlled by MOS transistor M11 and M12 and feedback resistance Rf in parallel, does not need to consider the change of common mode input.
Though the utility model discloses as above with a preferred embodiment, so it is not in order to limiting the utility model, anyly has the knack of this skill person, in not breaking away from spirit and scope of the present utility model, when doing a little change and retouching.For example, current mirror and buffer circuit can be separated into a current mirroring circuit and a current buffering circuit, and each inter-module in the differential commentaries on classics single-ended converter can combine, or separately design.Therefore protection range of the present utility model is as the criterion when looking the accompanying Claim person of defining.
Claims (8)
1, a kind of differential commentaries on classics single-ended converter, it comprises:
One transduction amplifier links to each other with a differential voltage signal, and above-mentioned differential voltage conversion of signals is become differential current signal, and wherein above-mentioned transduction amplifier has a degeneration resistance;
One current mirror and buffer circuit are coupled to above-mentioned transduction amplifier, are an one-terminal current signal in order to transmit above-mentioned differential current signal; And
One changes impedance amplifier, is coupled to above-mentioned current mirror and buffer circuit, and in order to receive above-mentioned one-terminal current signal and above-mentioned one-terminal current conversion of signals is become single-ended voltage signal, wherein above-mentioned commentaries on classics impedance amplifier has a feedback resistance in parallel.
2, differential commentaries on classics single-ended converter as claimed in claim 1 is characterized in that the gain of above-mentioned differential commentaries on classics single-ended converter is determined with the resistance value of above-mentioned feedback resistance in parallel by above-mentioned degeneration resistance.
3, differential commentaries on classics single-ended converter as claimed in claim 1 is characterized in that above-mentioned transduction amplifier comprises:
First and second metal oxide semiconductor transistor, its grid links to each other with above-mentioned differential voltage signal, the above-mentioned differential current signal of its drain electrode output;
One degeneration resistance, it is coupled to the source electrode of above-mentioned first and second metal oxide semiconductor transistor; And
The the 3rd and the 4th metal oxide semiconductor transistor, its drain electrode is respectively coupled to the source electrode of above-mentioned first and second metal oxide semiconductor transistor, and its source electrode is coupled to first power end, and its grid then receives first bias voltage.
4, differential commentaries on classics single-ended converter as claimed in claim 1 is characterized in that above-mentioned current mirror and buffer circuit comprise:
The the 5th and the 6th metal oxide semiconductor transistor, its grid links to each other with second bias voltage, and its source electrode couples the second source end, and its drain electrode links to each other with above-mentioned differential current signal;
The the 7th and the 8th metal oxide semiconductor transistor, its grid links to each other with one the 3rd bias voltage, and its source electrode is coupled to the above-mentioned the 5th and the drain electrode of the 6th metal oxide semiconductor transistor respectively;
The 9th metal oxide semiconductor transistor, its drain and gate is coupled to the drain electrode of above-mentioned the 7th metal oxide semiconductor transistor, and its source electrode is coupled to first power end; And
The tenth metal oxide semiconductor transistor, its grid is coupled to the drain electrode of above-mentioned the 7th metal oxide semiconductor transistor, its source electrode is coupled to above-mentioned first power end, and its drain electrode is coupled to the drain electrode of above-mentioned the 8th metal oxide semiconductor transistor and above-mentioned one-terminal current signal is provided.
5, differential commentaries on classics single-ended converter as claimed in claim 1 is characterized in that above-mentioned commentaries on classics impedance amplifier comprises:
The 11 metal oxide semiconductor transistor, its grid links to each other with above-mentioned one-terminal current signal, and its source electrode couples the second source end;
The 12 metal oxide semiconductor transistor, its grid is coupled to the grid of above-mentioned the 11 metal oxide semiconductor transistor, its source electrode is coupled to first power end, its drain electrode is coupled to the drain electrode of above-mentioned the 11 metal oxide semiconductor transistor, in order to above-mentioned single-ended voltage signal to be provided; And
One feedback circuit in parallel, its be coupled to the above-mentioned the 11 and the grid of the 12 metal oxide semiconductor transistor and drain electrode between.
6, a kind of differential commentaries on classics single-ended converter, it comprises:
First and second power end;
First and second metal oxide semiconductor transistor, its grid links to each other with a differential voltage signal;
One degeneration resistance, it is coupled to the source electrode of above-mentioned first and second metal oxide semiconductor transistor; And
The the 3rd and the 4th metal oxide semiconductor transistor, its drain electrode is respectively coupled to the source electrode of above-mentioned first and second metal oxide semiconductor transistor, and its source electrode is coupled to above-mentioned first power end, and its grid then links to each other with first bias voltage.
The the 5th and the 6th metal oxide semiconductor transistor, its grid links to each other with second bias voltage, and its source electrode couples above-mentioned second source end, and its drain electrode couples the drain electrode of above-mentioned first and second metal oxide semiconductor transistor respectively;
The the 7th and the 8th metal oxide semiconductor transistor, its grid links to each other with the 3rd bias voltage, and its source electrode is coupled to the drain electrode of above-mentioned first and second metal oxide semiconductor transistor respectively;
The the 9th and the tenth metal oxide semiconductor transistor, its drain electrode is coupled to the above-mentioned the 7th and the drain electrode of the 8th metal oxide semiconductor transistor respectively, its grid is coupled to the drain electrode of above-mentioned the 9th metal oxide semiconductor transistor, and its source electrode is coupled to above-mentioned first power end;
The 11 metal oxide semiconductor transistor, its grid couples the drain electrode of above-mentioned the tenth metal oxide semiconductor transistor, and its source electrode couples above-mentioned second source end;
The 12 metal oxide semiconductor transistor, its grid is coupled to the drain electrode of above-mentioned the tenth metal oxide semiconductor transistor, and its source electrode is coupled to above-mentioned first power end, and its drain electrode is coupled to the drain electrode of above-mentioned the 11 metal oxide semiconductor transistor; And
One feedback circuit in parallel, its be coupled to the above-mentioned the 11 and the grid of the 12 metal oxide semiconductor transistor and drain electrode between;
Wherein the above-mentioned the 11 and the continuous drain electrode of the 12 metal oxide semiconductor transistor one single-ended output signal then is provided.
7, differential commentaries on classics single-ended converter as claimed in claim 6, it is characterized in that above-mentioned first and second metal oxide semiconductor transistor, the the above-mentioned the 3rd and the 4th metal oxide semiconductor transistor, the above-mentioned the 9th and the tenth metal oxide semiconductor transistor and the 12 metal oxide semiconductor transistor are the PMOS transistor; The the above-mentioned the 5th and the 6th metal oxide semiconductor transistor, the above-mentioned the 7th and the 8th metal oxide semiconductor transistor and above-mentioned metal oxide semiconductor transistor are nmos pass transistor.
8, differential commentaries on classics single-ended converter as claimed in claim 6, the gain that it is characterized in that above-mentioned differential commentaries on classics single-ended converter are determined with the resistance value ratio of above-mentioned feedback resistance in parallel by above-mentioned degeneration resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03244025 CN2632940Y (en) | 2003-04-10 | 2003-04-10 | High speed differential to monoterminal converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03244025 CN2632940Y (en) | 2003-04-10 | 2003-04-10 | High speed differential to monoterminal converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2632940Y true CN2632940Y (en) | 2004-08-11 |
Family
ID=34292382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03244025 Expired - Lifetime CN2632940Y (en) | 2003-04-10 | 2003-04-10 | High speed differential to monoterminal converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2632940Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8692179B2 (en) | 2010-08-13 | 2014-04-08 | National Tsing Hua University | Optical communication system using grounded coplanar waveguide |
| CN112448684A (en) * | 2019-08-27 | 2021-03-05 | 立积电子股份有限公司 | Operational amplifier |
-
2003
- 2003-04-10 CN CN 03244025 patent/CN2632940Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8692179B2 (en) | 2010-08-13 | 2014-04-08 | National Tsing Hua University | Optical communication system using grounded coplanar waveguide |
| CN112448684A (en) * | 2019-08-27 | 2021-03-05 | 立积电子股份有限公司 | Operational amplifier |
| CN112448684B (en) * | 2019-08-27 | 2024-04-05 | 立积电子股份有限公司 | Operational amplifier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1287523C (en) | Low current lost waiting state circuit for converting differential signal into monoterminal signal | |
| CN1084085C (en) | Operational amplification circuit | |
| CN1968014A (en) | Calibration circuit and semiconductor device incorporating the same | |
| CN1825174A (en) | Gray scale voltage generating circuit | |
| CN102176659B (en) | Transconductance-enhanced recovery current folded MOS (metal oxide semiconductor) transistor cascade amplifier | |
| CN106953606B (en) | Fully differential amplifier and margin gain circuit using same | |
| CN1897465A (en) | Sample-and-hold circuits having reduced channel conductance variation and methods of operation thereof | |
| CN101064497A (en) | Complementary metal oxide semiconductor cascade high-gain current-to-voltage converter | |
| CN1266838C (en) | Semiconductor integrated circuit device capable of generating stably constant current under low power voltage | |
| CN111200402A (en) | High-linearity dynamic residual error amplifier circuit capable of improving gain | |
| CN101047383A (en) | Current controlled full-balance differential current transmitter | |
| CN2632940Y (en) | High speed differential to monoterminal converter | |
| US7071778B2 (en) | High-speed low-power dynamic current biased operational amplifier | |
| CN1306696C (en) | Variable time constant circuit and filter circuit using it | |
| CN1186885C (en) | Differential line driver | |
| CN1622469A (en) | Semiconductor device having on-chip reference voltage generator | |
| CN1536758A (en) | High-speed differential rotation single-ended converter | |
| CN1167188C (en) | Amplifier | |
| CN2849790Y (en) | Auxiliary circuit, voltage regulator and circuit apparatus for improving rejection ratio of low frequency power | |
| CN113014232A (en) | Low-jitter differential clock receiving circuit | |
| US8847634B1 (en) | High-speed unity-gain input buffer having improved linearity and stability with a low supply voltage | |
| CN1279696C (en) | A CMOS voltage comparator | |
| CN1551490A (en) | Operational amplifier circuit, sample/hold circuit and filter circuit using the operational amplifier circuit | |
| CN1578146A (en) | Input buffer circuit, and semiconductor apparatus having the same | |
| CN106712731B (en) | Operational amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: MEDIATEK INC. Free format text: FORMER OWNER: INTEGRATED COMMUNICATION SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20050617 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20050617 Address after: Hsinchu, Taiwan Patentee after: MediaTek.Inc Address before: Palo Alto, California, USA Patentee before: Integrated Communication Science & Technology Co., Ltd. |
|
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20130410 Granted publication date: 20040811 |