CN2613882Y - Double-thickness assembly layer SOI chip structure - Google Patents

Abstract

Disclosed is a SOI structure of double thickness component layer, which comprises a component layer (which can be divided into a thinner layer and a thicker layer), a shallower buried oxide at least and a ground layer, wherein each buried oxide is arranged at the preset position under the component layer and is surrounded with a deep trench at least which is deeper than that of buried oxide. In the process of manufacturing, the component layer, buried oxide and deep trench are formed after processing the first wafer, besides the ground layer belongs to the second wafer. The SOI wafer with a double thickness component layer is formed by the connection of the first wafer and the second wafer.

Description

Two thickness component layer soi chip structures

Technical field

The utility model provides a kind of two thickness (dual-thickness) component layer (active devicelayer) soi chip structure that has, especially refer to contain a kind of than shallow-layer zoneofoxidation (shallower buried oxide), its periphery have by the bigger zanjon (deep trench) that the degree of depth is set around the zoneofoxidation structure.

Background technology

See also Fig. 1, Fig. 1 is the cross sectional representation of known SOI (Silicon on Insulator) chip structure 10.So-called soi chip structure is silicon (silicon) component layer on insulating barrier (insulator) (as silicon dioxide).This soi chip structure 10 includes the below that layout that a component layer 12 is used for doing integrated circuit package, below that an insulating barrier 14 is positioned at component layer 12 and a ground plane 16 are positioned at insulating barrier 14.In general, the thickness d 1 of component layer 12 is homogeneous (uniform), that is to say that known soi chip structure 10 is the soi chip of a single thickness component layer.Insulating barrier 14 is otherwise known as usually and imbeds oxide layer (buried oxide layer, be called for short BOX), this generation type of imbedding oxide layer has a lot, for example directly the oxonium ion implanting ions is entered in the middle of the silicon substrate, increase temperature the original silicon substrate of oxidation again, make original silicon substrate structure can form the oxide layer of imbedding of silicon dioxide in certain certain depth position that can be predetermined.And in general, the thickness d 1 of the component layer 12 of SOI wafer is probably between 0.03 micron to 10 microns.

Yet, at present system single chip (System on a Chip, SOC) become gradually under the situation of the market mainstream, component layer on the same chip structure may need the many different types of circuit units of layout, these circuit units have separately separately size and the feature of radiating condition, operating current or voltage swing, make on the soi chip structure of a thickness homogeneous, be difficult to satisfy the demand of all component.That is to say that the operating voltage of some assembly is big or electric current is big, heat dissipation capacity is more, it is fit to layout in the bigger component layer position of thickness (because of bigger or the like the reason of operating current and breakdown voltage greatly); And if operating voltage is less or the assembly that heat dissipation capacity is less, only needing layout is not that so big component layer position gets final product at thickness.If the component layer thickness homogeneous of whole soi chip structure, those need the big operating voltage or the more assembly that dispels the heat, equally can layout on this chip structure, but just need occupy bigger chip area relatively, on the single thus wafer can layout core number will therefore reduce, and do not meet economic needs.In addition, known soi chip structure 10, it is for static discharge (electrostatic discharge, ESD) resistivity seems not enough owing to its component layer 12 is difficult to the restriction that effective ground connection (effectivelygrounded) and assembly breakdown voltage (break-down voltage) be subjected to thickness d 1.

So as from the foregoing, the soi chip structure of above-mentioned known technology obviously has inconvenience and exists with disappearance on reality is used, and need be improved.

Thus, the utility model has carried out rational design and improvement to the soi chip structure, to overcome above-mentioned defective.

The utility model content

Main purpose of the present utility model is to provide a kind of soi chip structure with two thickness component layer, owing to form one on first wafer than the shallow-layer zoneofoxidation and around this zoneofoxidation and the degree of depth is provided with the degree of depth greater than this zoneofoxidation zanjon is set, make that this component layer thickness than shallow-layer zoneofoxidation (top) does not have the component layer thickness of setting than shallow-layer zoneofoxidation (top) less than all the other relatively, and can provide multiple packaging of different kinds of packages layout on this first wafer assemblies layer.After this first wafer upset, engage (bonding) with another second wafer (being also referred to as bearing wafer (handle wafer)) as ground plane, again first wafer after engaging is cut (split) and carries out surface treatment afterwards, form one and have two thickness component layer SOI wafers.

The above-mentioned soi chip structure that the utility model provides, be that first pre-position on first wafer is provided with a pair of alignment mark earlier, the annular zanjon that at least one has the first predetermined set degree of depth is set in second pre-position again, and the mode by thermal oxidation (thermal oxidation) forms the zoneofoxidation (this second predetermined set degree of depth is less than the first predetermined set degree of depth) with second predetermined set degree of depth in the inboard of this second precalculated position (zanjon just) more afterwards.The degree of depth (the first predetermined set degree of depth) that is provided with of zanjon is provided with the degree of depth (the second predetermined set degree of depth) greater than the zoneofoxidation that forms afterwards; and zanjon surface (and wafer surface) has the protection of a silicon nitride (silicon nitride) film; make when zoneofoxidation forms; because of the even incident beak of silicon crystal lattice non-homogeneous expansion (bird ' s beak) effect, thereby be unlikely to the adjacent assemblies layer is produced destruction in the time of can exempting the silicon crystal lattice thermal oxidation.Behind the zanjon and zoneofoxidation handled on first wafer, with this first wafer upset, engage with second wafer (being also referred to as bearing wafer) with a surperficial pure silicon layer (silicon layer) or a surface oxide layer (oxidized layer) or surface metal-layer (metal layer), afterwards again to the cutting of first wafer after engaging and carry out follow-up surface treatment, to obtain soi chip structure of the present utility model.

So the soi chip structure with two thickness component layer that the utility model provides includes: a component layer, it can be subdivided into thin component layer and a thicker component layer; On at least one precalculated position that is arranged on component layer than the shallow-layer zoneofoxidation; At least one zanjon is around zoneofoxidation, this zanjon the be provided with degree of depth of the degree of depth greater than zoneofoxidation be set; One ground plane be connected with component layer and zoneofoxidation (adjacently connected).

And this pair thickness component layer soi chip structure can be made through the following steps: one first wafer is provided; At least one pair of alignment mark (alignment marks) is set in first pre-position of first wafer; In second pre-position of first wafer, etch at least one ring-like zanjon (deep trench) with one first predetermined set degree of depth; Zanjon and wafer surface are deposited a silicon nitride (silicon nitride) film; The silicon material district of etching one less than the 4th predetermined set degree of depth of the first predetermined set degree of depth carried out to first wafer in zanjon inboard in second precalculated position; On the silicon face of finishing inboard, etched second precalculated position,, the silicon crystal lattice thermal oxidation is expanded, form the zoneofoxidation of a thermal oxidation silicon (thermal oxide) material by the mode of thermal oxidation (thermal oxidation); Deposit and fill up amorphous silica (amorphous silicon oxide) by chemical vapour deposition technique (CVD) at this zanjon; Use chemical mechanical milling method (CMP) to be used for leveling and remove surface unnecessary silica and silicon nitride film; One second wafer and first wafer that overturns are provided, and the mode of utilizing wafer to engage simultaneously is connected first wafer with second wafer; And first wafer after the cutting upset of one the 3rd predetermined set degree of depth place; Carry out follow-up surface treatment at last.

The beneficial effects of the utility model are: by utilizing the setting of zoneofoxidation in the wafer, can reach different component layer thickness.Therefore this different component layer thickness can be applicable to different integrated circuit packages, and do not need to yield to the difference between the circuit unit, to reach the result of the ccontaining different qualities circuit unit of energy.In addition, because the method for having used wafer to engage makes the soi chip structure can have direct ground plane, comparatively speaking, its resistivity to static discharge also increases thereupon.

In order to make your auditor can further understand the utility model is to reach technology, means and the effect that predetermined purpose is taked, see also following about detailed description of the present utility model and accompanying drawing, yet appended icon only provides reference and explanation usefulness, is not to be used for the utility model is limited.

Description of drawings

Fig. 1 is the cross sectional representation of known soi chip structure;

Fig. 2 A is the schematic diagram with first embodiment of two thickness component layer soi chip structures of the present utility model;

Fig. 2 B is the upward view of first wafer after manufacturing finishes among Fig. 2 A;

Fig. 2 C is another form of implementation among Fig. 2 A;

Fig. 3 A is the schematic diagram of second embodiment of soi chip structure of the present utility model;

Fig. 3 B is another form of implementation among Fig. 3 A;

Fig. 4 A is the schematic diagram of the 3rd embodiment of the utility model soi chip structure;

Fig. 4 B is another form of implementation among Fig. 4 A;

Fig. 5 A to Fig. 5 J is a manufacturing flow chart of simplifying of the utility model soi chip structure.

Wherein, symbol description is as follows:

The component layer of 10 known soi chip structure 12 known soi chips

The ground plane of the insulating barrier 16 known SIO chips of 14 known soi chips

50,80,90 SOI chip structures

60,81,91,100 first wafers (some before the wafer cutting)

61,82,92,120 second wafers

62,83,93 component layer, 64,84,94,142 zanjons

65,85,95,150 zoneofoxidations, 67,86,98,114 alignment marks

87 second wafer oxide layers, 96 metal systems

88,97 silicon layers (ground plane), 99 SOI assemblies

101 conductive plugs, 102 insulating barriers

The first surface of 110 first wafers

112 cutting planes (the 3rd predetermined set degree of depth)

140 second precalculated positions

144 silicon nitride films, 148 CVD silicon dioxide

68, the upper and lower surface of 69,891,892,103,104 first wafers (outer surface and lower surface)

Embodiment

See also Fig. 2 A, Fig. 2 B and Fig. 2 C, Fig. 2 A is the schematic diagram with first embodiment 50 of two thickness component layer soi chip structures of the present utility model, Fig. 2 B then is the upward view of first wafer 60 after manufacturing finishes among Fig. 2 A, and Fig. 2 C is another form of implementation of Fig. 2 A.Soi chip structure 50 of the present utility model includes one first wafer 60 and one second wafer 61, and this first wafer 60 is engaged with each other with the mode that second wafer 61 will utilize wafer to engage in process of production, forms soi chip structure 50 after cutting.

First embodiment 50 include a component layer 62 be used for layout integrated circuit package, at least one circle zanjon 64 and one by zanjon around imbed oxide layer (BOX) (zoneofoxidation just) 65, component layer 62 and zoneofoxidation 65 are connected with below one silicon layer 61.Wherein component layer 62, zanjon 64, and 64 of zanjons around the zoneofoxidation 65 of imbedding are somes for first wafer 60.The silicon layer 61 of component layer 62 and zoneofoxidation 65 belows is the silicon layer of second bearing wafer 61, its effect as same ground plane.

Shown in Fig. 2 B, wherein zanjon 64 is provided with around imbedding oxide layer 65, and it is provided with depth D 1 and greater than what imbed oxide layer 65 depth D 2 is set.Each zoneofoxidation 65 is arranged on the precalculated position of first wafer 60, also can be described as the inboard that is arranged on zanjon 64.In fact because zanjon 64 forms early than this zoneofoxidation 65, so as long as after having determined precalculated position that 65 desires of zoneofoxidation are provided with, can instead push away obtain zanjon 64 the position that should be provided with.

Because the mode of imbedding oxide layer 65 and being with a thermal oxidation lattice dilatation forms, so in forming process if not around the setting of zanjon 64, because the part silicon substrate is subjected to thermal oxidation, lattice will be won wafer assemblies layer 62 toward expanding up and down, making easily because zoneofoxidation 65 peripheries have the result of lattice fracture (crack) to produce in the thermal oxidation forming process because of beak effect.First wafer 60 zanjon 64 and zoneofoxidation 65 form finish after, will be inverted (flip) and engage with second wafer 61.Thus, (thermal oxidation forms it) zoneofoxidation 65 of first wafer 60 can both engage with the silicon face of second wafer 61 with component layer 62.In soi chip structure 50, second wafer 61 as same ground plane, make can be referenced to except the integrated circuit package of layout component layer 62 above the zoneofoxidation 65 (ground).With the angle of component layer 62, pairing component layer 62 on the precalculated position that zoneofoxidation 65 is set (i.e. thin component layer), its thickness D3 will be significantly less than the thickness D4 that zoneofoxidation 65 pairing component layer 62 (i.e. a thicker component layer) is not set.This pair thickness component layer (thickness is D3 and D4) soi chip structure 50 has been arranged, and component layer 62 can be used for being provided with different types of circuit unit.Circuit unit each other may be because the difference of required operating voltage, electric current or radiating requirements, make be fit to be provided with the position component layer 62 thickness differ from one another.Some need higher operating voltage, electric current or bigger power consumption or the circuit unit of bigger earth current, can be arranged on component layer 62 positions that thickness equals D4, and not be that so high circuit unit is arranged on component layer 62 positions that thickness equals D3 and gets final product other operating current or radiating requirements.The purpose of design like this, except the demand that cooperates circuit unit, compare with the soi chip structure that only has the single component layer thickness, can be because of operating current is not bigger, the circuit unit that radiating requirements is bigger need occupy than the wafer area influences chip (chip) number that entire wafer is carried.In addition, as ground plane, can make soi chip structure 50 of the present utility model resisting static discharge phenomenon more effectively with second wafer 61.

First wafer 60 includes at least one pair of (a pair of) in addition and is arranged on the alignment mark 67 in first precalculated position, and is arranged in component layer, imbeds on the plane of oxide layer.The purpose that is provided with of alignment mark is setting (all utilizing little shadow, etched mode) when zanjon 64 and zoneofoxidation 65 when carrying out, and stepper (stepper) and light shield thereof can directly corresponding above-mentioned alignment marks 67.When two alignment marks can provide contraposition when mechanism of a certain stepper, to such an extent as to can be easily at the little shadow in the pre-position of first wafer 60 and etch required zanjon and form this zoneofoxidation.

See also Fig. 2 C, Fig. 2 C is another schematic diagram with first embodiment 50 of two thickness component layer soi chip structures of the present utility model, is another form of implementation of Fig. 2 A.Wherein the outer surface (being the wafer cut surface) 69 that depth D 1 and first wafer 60 after cutting through wafer are set of zanjon 64 sees also Fig. 2 C with lower surface (promptly descending silicon face, just the wafer composition surface) 68.

See also Fig. 3 A, Fig. 3 A is the schematic diagram of second embodiment 80 of soi chip structure of the present utility model.This second embodiment 80 includes a component layer 83, at least one zanjon 84, and by 84 of zanjons around imbed zoneofoxidation 85.Component layer 83 and zoneofoxidation 85 belows and are imbedded oxide layer 87 and are connected, and imbedding oxide layer 87 belows has a silicon layer 88 effect as same ground planes.Wherein component layer 83, zanjon 84, and 84 of zanjons around the zoneofoxidation 85 of imbedding be the some of first wafer 81.Imbed oxide layer 87 and below one silicon layer 88 is the surface oxide layer and the silicon layer of second bearing wafer 82.

82 of second bearing wafers are engaging carrying and the ground connection use of back as this soi chip structure 80 with 81 upsets of first wafer.Zanjon 84 is in the processing procedure of first wafer 81, can insert earlier silicon nitride (silicon nitride) film in advance, the silicon dioxide that utilizes chemical vapour deposition technique (CVD) to be produced after zoneofoxidation 85 forms fills up afterwards, is thermal oxidation silicon material (thermal oxides) as for 85 of zoneofoxidations.About the selection of zanjon 84 with zoneofoxidation 85 materials, the different combination of materials of many kinds can be arranged, same situation also occurs in Fig. 2 A, and 2B is in the middle of the embodiment that 2C disclosed.In addition, the width of zanjon 84 is preferably 0.2 to 5 micron, and its degree of depth (i.e. the first predetermined set degree of depth) is preferably 0.1 to 10 micron.

Compare with first embodiment of the present utility model of Fig. 2 A and Fig. 2 B, the soi chip structure 80 of Fig. 3 A, its second wafer 82 is with before first wafer 81 engages, form a thermal oxide layer 87 on its second wafer, 82 surfaces earlier, make this thermal oxide layer 87 after two plates engages, can be connected with zoneofoxidation 85 and zanjon 84.With regard to the angle of component layer 83, there is component layer 83 (i.e. thin component layer) its thickness D5 that zoneofoxidation 85 is provided with will be less than the thickness D6 of the component layer 83 (i.e. a thicker component layer) of non-oxidation district 85 settings.In other words, the component layer 83 that does not have zoneofoxidation 85 to be provided with will can be used to layout needs big operating voltage or need be than the integrated circuit package of high heat radiation power; And have the component layer 83 that zoneofoxidation 85 is provided with, then can be used for the layout demand specially at a high speed or operating current does not need too big or radiating condition is not so high integrated circuit package.Two thickness component layer soi chip structures 80 that have of Fig. 3 A include at least one pair of alignment mark 86 equally in addition, stepper and light shield thereof can directly align with these alignment marks 86 when carrying out little shadow, so just can be at the little shadow in some precalculated position on first wafer 81, etch the silicon material that zanjon 84 and etching are positioned at zoneofoxidation 85 (before forming).The position that is provided with of alignment mark 86 is preferably the two-end-point that is positioned at the first wafer assemblies layer 83.

Second wafer 82 includes a silicon layer 88, as same ground plane in addition except forming the oxide layer 87 on its surface in advance.Soi chip structure 80 as shown in Figure 3A, even if in component layer 83 layout SOI assembly (not shown)s, even after the above-mentioned SOI assembly of assembly articulamentum (interconnect layer) (not shown) connection is set on the component layer, the SOI assembly of partly big operating current still needs conductive plug (via) to run through nonconducting zoneofoxidation 87 by component layer 83 and can be connected with silicon layer 88, to allow these SOI assemblies be able to ground connection.

See also Fig. 3 B, Fig. 3 B is another schematic diagram with second embodiment 80 of two thickness component layer soi chip structures of the present utility model, is another form of implementation of Fig. 3 A.Wherein zanjon 84 is provided with the degree of depth and sees also Fig. 3 B on surface (being the wafer cut surface) 891 outside first wafer 81 after the wafer cutting with lower surface (being the wafer composition surface) 892.

See also Fig. 4 A, Fig. 4 A is the schematic diagram of the 3rd embodiment 90 of the utility model soi chip structure.The 3rd embodiment 90 has a component layer 93, at least one circle zanjon 94, and by 94 of zanjons around imbed zoneofoxidation 95.Component layer 93 and zoneofoxidation 95 belows are connected with a metal level 96, and there is a silicon layer 97 metal level 96 belows, as same ground plane.

Wherein component layer 93, zanjon 94, and 94 of zanjons around the zoneofoxidation 95 of imbedding be the some of first wafer 91.Metal level 96 belows one silicon layer 97 is the silicon layer of second bearing wafer 92.Metal level 96 can be the surface metal-layer of second bearing wafer 92, also can be the surface metal-layer of first wafer 91.

Identical with embodiment before, first wafer 91 includes component layer 93 equally, and the zanjon 94 that the degree of depth equals D7 is set, and by 94 of this zanjons around, the zoneofoxidation 95 that the degree of depth equals D8 is set.Because the setting of zoneofoxidation 95, its relative thickness D9 will be less than the thickness D10 of the component layer 93 that is not provided with zoneofoxidation 95 correspondences (i.e. a thicker component layer) in the component layer 93 that is provided with this zoneofoxidation 95 (i.e. thin component layer) for feasible correspondence, thus, promptly form a soi chip structure with two thickness component layer, with SOI assembly in the different demands of component layer 93 location layouts of different-thickness.The zanjon 94 of first wafer 91 is to insert earlier after the silicon nitride film equally, just continues to be utilized the amorphous silica that chemical vapour deposition technique produces and fills up.As for 95 of the zoneofoxidations of imbedding is to form with thermal oxidation silicon.

Fig. 4 A and Fig. 3 A difference are that second wafer 92 of Fig. 4 A can be after its surface forms a metal level 96, engage with first wafer 91 after the upset.This metal level 96 can be a metal system (metalsystem), and just a metal level 96 is the layered composite of many different metals, as the combination of metal levels such as Ti, Ta, TiN, TaN, Au or Cu or metal alloy layer.First wafer 91 also can form a thin metal layer earlier, to increase the intensity (bonding strength) that wafer engages on its composition surface before joint.

In addition, as 99 when being grounded to ground plane 97, its conductive plug 101 (being coated by an other insulating barrier 102) need open to metal level 96 and get final product Fig. 4 layout at the SOI of component layer 93 assembly.SOI assembly 99 is to connect above-mentioned conductive plug 101 by the electric connection layer that is provided with on the component layer (interconnect layer) (not shown).

The soi chip structure 90 of Fig. 4 A includes the wafer two ends that at least one pair of alignment mark 98 is positioned at the first wafer assemblies layer 93 equally, and its purpose has had illustrated at preamble.

See also Fig. 4 B, Fig. 4 B is another schematic diagram with the 3rd embodiment 90 of two thickness component layer soi chip structures of the present utility model, is another form of implementation of Fig. 4 A.Wherein zanjon 94 is provided with depth D 7 and sees also Fig. 4 B at the outer surface (being the wafer cut surface) 103 of first wafer 90 after cutting with lower surface (promptly descending silicon face) 104.

See also Fig. 5 A to Fig. 5 J, Fig. 5 A to Fig. 5 J is the simplification manufacturing flow chart of the utility model soi chip structure.In general, whole manufacture method flow process is by first wafer 100 being handled beginning, being connected as second wafer 120 that ground plane uses with another with these first wafer, 100 upsets and by the mode that wafer engages afterwards again.

Fig. 5 A to Fig. 5 H is depicted as the processing to first wafer 100.Fig. 5 A is in the first surface 110 to first wafer 100, implants (ion implant) one deck hydrogen ion at the 3rd predetermined set degree of depth place ion; And the first surface 110 that the plane of the 3rd predetermined set degree of depth of first wafer 100 (forming the silicon wafer compartment of a lattice damage) is first wafer 100 is with after second wafer 120 engages, the predetermined cuts plane 112 of cutting this first wafer 100.This 3rd predetermined set degree of depth (being the degree of depth on predetermined cuts plane 112) is determined by an energy of implanting H rays.

Fig. 5 B promptly is provided with at least one pair of alignment mark 114 in first pre-position of the component layer of first wafer 100, the setting of this alignment mark 114 is alignings of stepper and light shield thereof for convenience later on, make can be in second precalculated position 140 of first wafer 100 and around the inboard in this second precalculated position 140 etch respectively zanjon and inboard around silicon material district.

Fig. 5 C is disclosed in second precalculated position 140 to etch a zanjon 142 with first predetermined set depth D 11.In first surface 110 and this zanjon 142, insert silicon nitride film afterwards in advance, form silicon nitride film layer 144, shown in Fig. 5 D.Afterwards, in second precalculated position 140 around the inboard etch a silicon material district with the 4th predetermined set depth D 12, wherein this 4th predetermined set depth D 12 is less than the first predetermined set depth D 11 (shown in Fig. 5 E).The bare silicon lattice thermal oxidation that will will be positioned at the medial area (the silicon material district before zoneofoxidation does not form) in second precalculated position 140 after a while in the mode of thermal oxidation (thermaloxidation) forms silicon dioxide, and the thickness of silicon nitride film layer 144 must protect the silicon crystal lattice of all the other coverings not by thermal oxidation.Because this silicon material district forms in the process of silicon dioxide in thermal oxidation, lattice expands up and down, so the setting of this zanjon 142 is arranged, avoiding the generation of so-called beak effect, and these zanjon 142 etched depth (the first predetermined set degree of depth) D11 is about more than one times greater than its medial area etched depth (the 4th predetermined set degree of depth) D12.

Shown in Fig. 5 F, be the zoneofoxidation of the silicon dioxide schematic diagram after the medial area of second precalculated position 140 (just zanjon 142) forms with the mode of thermal oxidation.Wherein the degree of depth of this zoneofoxidation (the second predetermined set degree of depth) D13 is less than the degree of depth of this zanjon 142 (the first predetermined set degree of depth) D11.

Fig. 5 G is depicted as the step of desiring to fill up zanjon 142 remaining spaces, above the preceding silicon nitride layer of inserting, the amorphous silica layer that utilizes chemical vapour deposition technique to produce, this amorphous silica layer can cover before equally by on the silicon dioxide layer (being zoneofoxidation 150) that thermal oxidation produced.Afterwards, must be except filling zanjon 142, CVD amorphous silica layer 148 and silicon nitride film unnecessary on first surface 110 are given removal.This use be the chemical mechanical milling method (CMP) that generally uses, be used for leveling and remove these unnecessary CVD silica and silicon nitride films, shown in Fig. 5 H.After a while, can be additionally to this first wafer first surface 110 of leveling to impose a high-temperature hydrogen tempering (hightemperature hydrogen anneal) impaired to repair the lattice that may occur in the manufacture process formerly, and the surface oxide layer that goes that utilizes hydrofluoric acid (HF) solution or steam that trace is carried out on this first wafer silicon surface is handled.Fig. 5 I is depicted as handle to first wafer upset that proceeds to Fig. 5 H step, and engages with second wafer that uses as ground plane with the method that wafer engages.Then the hydrionic plan position approach 112 of previous implantation (i.e. the 3rd predetermined set degree of depth place) cut with a water cutter (water jet), make it become soi chip structure shown in Fig. 5 J.Wherein, this 3rd predetermined set degree of depth place through cutting after, the step that need utilize CMP that cutting cut surface (wafer surface) is later carried out leveling equally, or carry out the processing of a high-temperature hydrogen tempering again.

If second wafer 120 is before engaging, make the oxide layer that generates a thermal oxidation silicon material on its surface with regard to carrying out a step of thermal oxidation earlier, or after its surface generates the metal system of a conduction, engage with first wafer 100 again, can obtain the have two thickness component layer soi chip structures identical equally with earlier figures 3 and Fig. 4.

Than prior art, soi chip structure of the present utility model is the setting that utilizes zoneofoxidation in the wafer, to reach the result of different component layer thickness.Therefore this different component layer thickness can be applicable to different integrated circuit packages, and not need to yield to the difference between those circuit units, to reach the result of the ccontaining different qualities circuit unit of energy.In addition, because the method for having used wafer to engage makes the soi chip structure of earlier figures 2 and Fig. 4 have direct ground plane, comparatively speaking, its resistivity to static discharge also increases thereupon.

The above only is preferred embodiment of the present utility model, and all equalizations of being done according to the utility model claim are modified and changed, and all should belong to the protection range of the utility model patent.

Claims (14)

1. one kind has two thickness component layer soi chip structures, it is characterized in that, includes:

One component layer;

At least one zoneofoxidation, each described zoneofoxidation are arranged in the precalculated position of described component layer;

At least one zanjon is around described zoneofoxidation, described zanjon the be provided with degree of depth of the degree of depth greater than described zoneofoxidation be set; And

One ground plane is connected with described component layer and described zoneofoxidation.

2. soi chip structure as claimed in claim 1, it is characterized in that, described component layer, zoneofoxidation and zanjon belong to one first wafer, and described ground plane then belongs to one second wafer, and described first wafer is to be connected in the mode that wafer engages with described second wafer.

3. soi chip structure as claimed in claim 1 is characterized in that, described ground plane is a monocrystalline silicon layer.

4. soi chip structure as claimed in claim 1 is characterized in that, described zoneofoxidation is the zoneofoxidation that a thermal oxidation silicon forms.

5. soi chip structure as claimed in claim 1 is characterized in that, also includes at least one pair of alignment mark, is arranged in the described component layer.

6. soi chip structure as claimed in claim 1 is characterized in that, also includes an oxide layer, and described oxide layer is positioned on the described ground plane, and directly is connected with the described component layer and the described zoneofoxidation of described oxide layer top.

7. soi chip structure as claimed in claim 6, it is characterized in that, described component layer, zoneofoxidation and zanjon belong to one first wafer, and described ground plane and described oxide layer then belong to one second wafer, and described first wafer is to be connected in the mode that wafer engages with described second wafer.

8. soi chip structure as claimed in claim 6 is characterized in that, described ground plane is a monocrystalline silicon layer.

9. soi chip structure as claimed in claim 6 is characterized in that, also includes at least one pair of alignment mark, is arranged in the described component layer.

10. soi chip structure as claimed in claim 1 is characterized in that, also includes a metal level, and described metal level is positioned on the described ground plane, and directly is connected with the described component layer and the described zoneofoxidation of described metal level top.

11. soi chip structure as claimed in claim 10, it is characterized in that, described component layer, zoneofoxidation and zanjon belong to one first wafer, and described ground plane and described metal level then belong to one second wafer, and described first wafer is to be connected in the mode that wafer engages with described second wafer.

12. soi chip structure as claimed in claim 10 is characterized in that, described metal level is an a kind of metal level or a complex metal layer.

13. soi chip structure as claimed in claim 10 is characterized in that, also includes at least one pair of alignment mark, is arranged in the described component layer.

14. soi chip structure as claimed in claim 10 is characterized in that, described ground plane is a monocrystalline silicon layer.

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