CN2607623Y - Digital image size-adjustable integrated circuit for display device - Google Patents
Digital image size-adjustable integrated circuit for display device Download PDFInfo
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- CN2607623Y CN2607623Y CN 03215500 CN03215500U CN2607623Y CN 2607623 Y CN2607623 Y CN 2607623Y CN 03215500 CN03215500 CN 03215500 CN 03215500 U CN03215500 U CN 03215500U CN 2607623 Y CN2607623 Y CN 2607623Y
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Abstract
The utility model relates to a digital-image-zooming integrated circuit for a display, pertains to the digital image display technology and consists of a housing, a circuit and pins. The circuit consists at least of a read-control module connected with an effective data signal input terminal of a object image and a clock input terminal of an output image, a write-control module connected with the effective clock and data signal input terminals of the input image, a row buffer module, a field zooming module, a row zooming module and a coefficient generating module. A zoomed RGB signal is finally output by the row zooming module. The coefficient generating module consists of a coefficient generator and a field coefficient generator respectively composed of a adder, a selector and a D trigger or a efficient latch. An eight-digit row coefficient or a field coefficient is finally output. The utility model has a simple way to generate the zooming coefficients and the memory read addresses, simultaneously realizes the zooming-in and zooming-out functions and has a simple structure, a lower cost and ahigh reliability, which can be widely used in digital image zooming for various displays.
Description
Technical field
The utility model belongs to the Digital Image Display Technology field, more specifically to the improvement of the digital image scaling integrated circuit of display.
Background technology
Traditional video standard converter ic that is used for the various types of flat panel display is all complicated.Wherein the generation of zoom factor and memory read address is particularly complicated.Too complicated because of it, more easily go wrong, reliability is also relatively poor.In addition, existing single circuit can not be realized upwards convergent-divergent (promptly being transformed into high-definition image from the low definition image) and convergent-divergent (promptly being transformed into the low definition image from high-definition image) function downwards simultaneously.
The purpose of this utility model, just be to overcome above-mentioned shortcoming and defect, provide the producing method of a kind of zoom factor and memory read address particularly simple, upwards convergent-divergent and downward two kinds of functions of convergent-divergent can be realized simultaneously by single circuit, thereby greatly reduce the complexity and the production cost of circuit structure, improved the digital image scaling integrated circuit of the display of reliability.
Summary of the invention
In order to achieve the above object, the utility model by shell, be encapsulated in the circuit in the shell and be connected the pin of drawing shell and form with circuit.Circuit comprises the control module of reading that is connected with the input end of clock of the data useful signal input end of target image and output image at least, write control module with the clock of input picture is connected with data useful signal input end, enable the row cache module that output terminal and RGB input end are connected with the write address of reading the address and and read to enable output terminal and writing the control module generation of reading that control module produces with writing, the field Zoom module that is connected with the RGB data output end of row cache module, capable Zoom module that is connected with the RGB data output end of field Zoom module and line of input step-length and step-length and with the zoom factor of output respectively with read the coefficient generation module that a control module and a Zoom module are connected with capable Zoom module.Rgb signal through convergent-divergent is exported by the row Zoom module at last.
When data arrive, earlier through four lines buffer buffer memory.Write control module generation write address and enable, read the control module generation and read the address and read to enable with writing.The rgb value of reading from line storage through the convergent-divergent of vertical direction convergent-divergent on the spot, passes through convergent-divergent convergent-divergent, the output at last at once of horizontal direction earlier again.In the coefficient that coefficient generation module (Coef-Gen) produces, Vcoef[5:0], Hcoef[5:0] be respectively applied for a convergent-divergent and row convergent-divergent, Vcoef[7:6], Hcoef[7:6] be respectively applied for the generation of reading to enable (promptly selecting to read line storage) and reading the address.
The effective generation module of data does not draw in the drawings, and it is responsible for producing the data useful signal (being Des-de) of target image.This signal is used for resetting of each module or data sync.Ori-clk, Ori-De and RGB-in are respectively clock, data useful signal and the pixel rgb values of input picture.Des-clk is the clock of output image, produces the back input by outside phaselocked loop.A row step-length (Htep) and a step-length (Vstep) are used to produce zoom factor.They are to be calculated according to input pattern and output mode by microprocessor MCU.Its formula is as follows:
For the convergent-divergent that makes progress, its value will be lower than 64.For downward convergent-divergent, its value will be greater than 64 less than 128.The utility model is not suitable for row, step-length greater than 128 situation.
Coefficient generation module comprises a row coefficient generator and a coefficient generator.The row coefficient generator adds that by the row step-length remainder of row coefficient mould 64 is Hcoef[5:0] totalizer, then through the selector switch and the d type flip flop of D-de-11 control, at last at the row coefficient Hcoef[7:0 of 8 of each rising edge clock outputs].Wherein D-de-11 is the signal that postpones a clock by D-de and D-de and obtain.It only exports high level (being the leading one of D-de) in D-de is high first clock period.As D-de-11 selector switch output 8 ' b0 when being high.Equally, the latch that coefficient generator is added the totalizer of the remainder of the coefficient module 64 of entering the court, enabled through the selector switch and the band of D-vde-11 control then by the field step-length is at last at the field coefficient of 8 of each rising edge clock outputs.The field coefficient also is to add Vcoef[5:0 by the field step-length when every row begins] obtain, and zero clearing (D-de-11 is 1 o'clock) when every beginning.Have only as D-de-11 and just export when being high, otherwise keep initial value.
Read control module and comprise that reading row controls and read the row selection.Read row control and add the totalizer of row coefficient every a clock cycle, then through the selector switch of D-de-11 control, after d type flip flop output by reading the address.Read to add when row is selected by every row beginning the totalizer of row coefficient, then through the selector switch of D-vde-11 control, after the latch output that band enables.
It is similar to coefficient generation module to read control module.Read the address and add Hcoef[7:6 every a clock cycle], and (during D-de-11=1) zero clearing when every row begins, after d type flip flop output.Row selects rd-1in (during D-de-11=1) when every row begins to add Vcoef[7:6], and (during V-de-11=1) zero clearing when each beginning.It is worth pairing line storage, and to read to enable rd-en be 1.Another is read address and row and selects respectively to be selected subtracting 1 and obtained by above address and the row read.
It is simpler to write control module.Write address and writing only enable need line by line, the pointwise increase just.
The field Zoom module is by capable with i, the totalizer of the field zoom factor addition that the rgb value of j row and i are capable, i+1 is capable, the totalizer of the field zoom factor addition that the rgb value of j row and i+1 are capable, totalizer with above-mentioned two totalizer income value additions, with the d type flip flop of this totalizer income value and read clock signal input and i is capable, the totalizer of the field zoom factor addition that the rgb value of j+1 row and i are capable is capable with i+1, the totalizer of the field zoom factor addition that the rgb value of j+1 row and i+1 are capable, totalizer with above-mentioned two totalizer income value additions, the d type flip flop of this totalizer and read clock signal input is constituted.Last d type flip flop is exported j row rgb value, and back one d type flip flop is exported j+1 row rgb value.
The row Zoom module is by with the rgb value of j row and the totalizer of the capable zoom factor addition of j row, the totalizer of the capable zoom factor addition that the rgb value and the j+1 of j row is listed as, the d type flip flop formation of importing with the totalizer of above-mentioned two totalizer income value additions, with this totalizer income value and read clock signal.D type flip flop is finally exported the rgb value behind convergent-divergent.
Vcoef-i+1, Hcoef-j+1 correspond respectively to the capable zoom factor of capable field zoom factor of i+1 and j+1 row.Its value is respectively Vcoef[5:0] and Hcoef[5:0].And Vcoef-i, Hcoef-j equal (64-Vcoef[5:0]) and (64-Hcoef[5:0]) respectively.For the field Zoom module, the rgb value of input multiply by the field zoom factor of corresponding row, and then with the corresponding product addition of same row, exports through d type flip flop again.For the row convergent-divergent, will multiply by the capable zoom factor of respective column through the rgb value behind the convergent-divergent of field, again with the product addition, after register is exported the rgb value behind the final convergent-divergent.
Task of the present utility model comes to this and finishes.
The utility model provides the producing method of a kind of zoom factor and memory read address very simple, upwards convergent-divergent and downward two kinds of functions of convergent-divergent can be realized simultaneously by single circuit, thereby greatly reduce the complexity and the production cost of circuit structure, improved the digital image scaling integrated circuit of the display of reliability.It can be widely used in the digital image scaling of various displays.
Description of drawings
Fig. 1 is a general structure block scheme of the present utility model.
Fig. 2 is the schematic diagram of coefficient generation module.
Fig. 3 is a schematic diagram of reading control module.
Fig. 4 is the schematic diagram of a Zoom module.
Fig. 5 is the schematic diagram of row Zoom module.
Shown in Figure 1, circuit of the present utility model comprise at least be connected with the input end of clock 2 of the data useful signal input end 1 of target image and output image read control module 3, write control module 6 with the clock 4 of input picture is connected with data useful signal input end 5, enable the row cache module 12 that output terminal 10 and pixel rgb value input end 11 are connected with read address 7 and the write address of reading to enable output terminal 8 and write control module 69 of reading that control module 3 produces with writing, field Zoom module 13, row Zoom module 14 and coefficient generation module 15 are exported by the row Zoom module at last through the rgb signal of convergent-divergent.The zoom factor 18 of coefficient generation module 15 outputs of line of input step-length 16 and step-length 17 with 19 respectively with read a control module 3 and a Zoom module 13 and be connected with capable Zoom module 14.
Shown in Figure 2, coefficient generation module 15 comprises a row coefficient generator and a coefficient generator.The row coefficient generator is made up of totalizer 20, selector switch 21 and d type flip flop 22, exports 8 row coefficient 18 at last.The field coefficient generator is made up of the latch 25 that totalizer 23, selector switch 24 and band enable, and exports 8 field coefficient 19 at last.
Shown in Figure 3, read control module 3 and comprise the generation of reading row control and reading the row selection.Read row control by totalizer 26, selector switch 27, after d type flip flop 28 outputs.Read row and select, after latch 31 outputs that band enables by totalizer 29, selector switch 30.
Shown in Figure 4, a Zoom module 13 is made up of totalizer 32 and 33, totalizer 34 and d type flip flop 35 and totalizer 36 and 37, totalizer 38 and d type flip flop 39.
Shown in Figure 5, row Zoom module 14 is made up of totalizer 40 and 41, totalizer 42 and d type flip flop 43.D type flip flop 43 is exported the target rgb value behind convergent-divergent at last.
Embodiment
The digital image scaling integrated circuit of 1. 1 kinds of displays of embodiment.It is made up of shell, die circuitry and pin.Circuit comprises the control module of reading that is connected with the input end of clock of the data useful signal input end of target image and output image at least, write control module with the clock of input picture is connected with data useful signal input end, enable the row cache module that output terminal and pixel rgb value input end are connected with the write address of reading the address and and read to enable output terminal and writing the control module generation of reading that control module produces with writing, the field Zoom module that is connected with the RGB data output end of row cache module, capable Zoom module that is connected with the RGB data output end of field Zoom module and line of input step-length and step-length and with the zoom factor of output respectively with read the coefficient generation module that a control module and a Zoom module are connected with capable Zoom module.
Coefficient generation module comprises a row coefficient generator and a coefficient generator.The row coefficient generator adds the totalizer of the remainder of row coefficient mould 64, selector switch and the d type flip flop controlled through a D-de-11 then by the row step-length, exports 8 row coefficient at last at each rising edge clock.The latch that coefficient generator is added the totalizer of the remainder of the coefficient module 64 of entering the court, enabled through the selector switch and the band of D-vde-11 control then by the field step-length is at last at the field coefficient of 8 of each rising edge clock outputs.
Read control module and comprise that reading row controls and read the row selection.Read row control and add the totalizer of row coefficient every a clock cycle, then through the selector switch of D-de-11 control, after d type flip flop output by reading the address.Read to add when row is selected by every row beginning the totalizer of row coefficient, then through the selector switch of D-vde-11 control, after the latch output that band enables.
The field Zoom module is by capable with i, the totalizer of the field zoom factor addition that the rgb value of j row and i are capable, i+1 is capable, the totalizer of the field zoom factor addition that the rgb value of j row and i+1 are capable, totalizer with above-mentioned two totalizer income value additions, with the d type flip flop of this totalizer income value and read clock signal input and i is capable, the totalizer of the field zoom factor addition that the rgb value of j+1 row and i are capable is capable with i+1, the totalizer of the field zoom factor addition that the rgb value of j+1 row and i+1 are capable, totalizer with above-mentioned two totalizer income value additions, the d type flip flop of this totalizer and read clock signal input is constituted.Last d type flip flop is exported j row rgb value, and back one d type flip flop is exported j+1 row rgb value.
The row Zoom module is by with the rgb value of j row and the totalizer of the capable zoom factor addition of j row, the totalizer of the capable zoom factor addition that the rgb value and the j+1 of j row is listed as, the d type flip flop formation of importing with the totalizer of above-mentioned two totalizer income value additions, with this totalizer income value and read clock signal.D type flip flop is finally exported the rgb value behind convergent-divergent.
The producing method of embodiment 1 zoom factor and memory read address is very simple, can realize upwards convergent-divergent and two kinds of functions of convergent-divergent downwards simultaneously.It can be converted to the original image (as 640 * 480) of lower resolution form the output image (as 1024 * 768) of higher resolution form.Also can realize outputing to the screen of supporting the lower resolution display format through conversion from the input signal of higher resolution.Its circuit structure is simple, and cost is low, the reliability height.It can be widely used in the digital image scaling of various displays.
Claims (9)
1. the digital image scaling integrated circuit of a display, it is by shell, be encapsulated in the circuit in the shell and be connected the pin of drawing shell and form with circuit, it is characterized in that said circuit comprises the control module of reading that is connected with the input end of clock of the data useful signal input end of target image and output image at least, write control module with the clock of input picture is connected with data useful signal input end, enable the row cache module that output terminal and pixel rgb value input end are connected with the write address of reading the address and and read to enable output terminal and writing the control module generation of reading that control module produces with writing, the field Zoom module that is connected with the RGB data output end of row cache module, capable Zoom module that is connected with the RGB data output end of field Zoom module and line of input step-length and step-length and with the zoom factor of output respectively with read the coefficient generation module that a control module and a Zoom module and row Zoom module are connected, export by going Zoom module at last through the rgb signal of convergent-divergent.
2. according to the digital image scaling integrated circuit of the described display of claim 1, it is characterized in that said coefficient generation module comprises a row coefficient generator and a coefficient generator, the row coefficient generator is added the totalizer of the remainder of row coefficient mould 64 by the row step-length, then through the selector switch and the d type flip flop of D-de-11 control, export 8 row coefficient at last at each rising edge clock, the field coefficient generator is added the totalizer of the remainder of the coefficient module 64 of entering the court by the field step-length, through the selector switch and the latch that band enables of D-vde-11 control, export 8 field coefficient at last at each rising edge clock then.
3. according to the digital image scaling integrated circuit of claim 1 or 2 described displays, it is characterized in that the said control module of reading comprises that reading row controls and read the row selection, read row control by reading the address adds row coefficient every a clock cycle totalizer, then through the selector switch of D-de-11 control, after d type flip flop output, read to add when row is selected by every row beginning the totalizer of row coefficient, then through the selector switch of D-vde-11 control, after the latch output that band enables.
4. according to the digital image scaling integrated circuit of claim 1 or 2 described displays, it is characterized in that said Zoom module is by capable with i, the totalizer of the field zoom factor addition that the rgb value of j row and i are capable, i+1 is capable, the totalizer of the field zoom factor addition that the rgb value of j row and i+1 are capable, totalizer with above-mentioned two totalizer income value additions, with the d type flip flop of this totalizer income value and read clock signal input and i is capable, the totalizer of the field zoom factor addition that the rgb value of j+1 row and i are capable, i+1 is capable, the totalizer of the field zoom factor addition that the rgb value of j+1 row and i+1 are capable, totalizer with above-mentioned two totalizer income value additions, the d type flip flop of this totalizer and read clock signal input is constituted, last d type flip flop is exported j row rgb value, and back one d type flip flop is exported j+1 row rgb value.
5. according to the digital image scaling integrated circuit of the described display of claim 3, it is characterized in that said Zoom module is by capable with i, the totalizer of the field zoom factor addition that the rgb value of j row and i are capable, i+1 is capable, the totalizer of the field zoom factor addition that the rgb value of j row and i+1 are capable, totalizer with above-mentioned two totalizer income value additions, with the d type flip flop of this totalizer income value and read clock signal input and i is capable, the totalizer of the field zoom factor addition that the rgb value of j+1 row and i are capable, i+1 is capable, the totalizer of the field zoom factor addition that the rgb value of j+1 row and i+1 are capable, totalizer with above-mentioned two totalizer income value additions, the d type flip flop of this totalizer and read clock signal input is constituted, last d type flip flop is exported j row rgb value, and back one d type flip flop is exported j+1 row rgb value.
6. according to the digital image scaling integrated circuit of claim 1 or 2 described displays, it is characterized in that the totalizer of said capable Zoom module by the capable zoom factor addition of rgb value that j is listed as and j row, with the totalizer of the rgb value of j row and the capable zoom factor addition of j+1 row, with the totalizer of above-mentioned two totalizer income value additions, with the d type flip flop formation that this totalizer income value and read clock signal are imported, d type flip flop is finally exported the rgb value behind convergent-divergent.
7. according to the digital image scaling integrated circuit of the described display of claim 3, it is characterized in that the totalizer of said capable Zoom module by the capable zoom factor addition of rgb value that j is listed as and j row, with the totalizer of the rgb value of j row and the capable zoom factor addition of j+1 row, with the totalizer of above-mentioned two totalizer income value additions, with the d type flip flop formation that this totalizer income value and read clock signal are imported, d type flip flop is finally exported the rgb value behind convergent-divergent.
8. according to the digital image scaling integrated circuit of the described display of claim 4, it is characterized in that the totalizer of said capable Zoom module by the capable zoom factor addition of rgb value that j is listed as and j row, with the totalizer of the rgb value of j row and the capable zoom factor addition of j+1 row, with the totalizer of above-mentioned two totalizer income value additions, with the d type flip flop formation that this totalizer income value and read clock signal are imported, d type flip flop is finally exported the rgb value behind convergent-divergent.
9. according to the digital image scaling integrated circuit of the described display of claim 5, it is characterized in that the totalizer of said capable Zoom module by the capable zoom factor addition of rgb value that j is listed as and j row, with the totalizer of the rgb value of j row and the capable zoom factor addition of j+1 row, with the totalizer of above-mentioned two totalizer income value additions, with the d type flip flop formation that this totalizer income value and read clock signal are imported, d type flip flop is finally exported the rgb value behind convergent-divergent.
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| CN 03215500 CN2607623Y (en) | 2003-03-07 | 2003-03-07 | Digital image size-adjustable integrated circuit for display device |
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| CN 03215500 CN2607623Y (en) | 2003-03-07 | 2003-03-07 | Digital image size-adjustable integrated circuit for display device |
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| CN2607623Y true CN2607623Y (en) | 2004-03-24 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010083711A1 (en) * | 2009-01-23 | 2010-07-29 | 中兴通讯股份有限公司 | Digital image scaling method and integrated system thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010083711A1 (en) * | 2009-01-23 | 2010-07-29 | 中兴通讯股份有限公司 | Digital image scaling method and integrated system thereof |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Qingdao Hisense Xinxin Technology Co., Ltd. Assignor: Hisense Group Co., Ltd. Contract fulfillment period: 2008.10.12 to 2013.10.11 Contract record no.: 2008370000073 Denomination of utility model: Digital image size-adjustable integrated circuit for display device Granted publication date: 20040324 License type: Exclusive license Record date: 20081030 |
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| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2008.10.12 TO 2013.10.11; CHANGE OF CONTRACT Name of requester: QINGDAO HAIXIN XINXIN SCIENCE CO., LTD. Effective date: 20081030 |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040324 |