CN2604725Y

CN2604725Y - Multipurpose bus terminal regulator with improved circuit

Info

Publication number: CN2604725Y
Application number: CN 03236131
Authority: CN
Inventors: 陈恒
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2003-01-17
Filing date: 2003-01-17
Publication date: 2004-02-25
Anticipated expiration: 2013-01-17

Abstract

A multi-purpose bus terminal voltage regulator with improved circuit, consists of the existing bus terminal voltage regulator as well as a CPU type discrimination and level translating circuit extended at the input end to discriminate the type selective signal on CPU and make the ALTL+ bus signal be isolated and transferred to the self operate level of the bus terminal voltage regulator. The front-end bus FSB which produces the second reference voltage Vref-2 according to the CPU type, regulates the circuit by refereeing voltage and selects corresponding reference voltage commutation control circuit from reference voltage output with three functional circuits connected in sequence; a fixed 1/2 voltage grading reference voltage circuit which produces the first reference voltage Vref-1 is connected to the other input end of the reference voltage commutation circuit. The integrated circuit can meet terminal matching requirement of DDR-SDRAM applying JEDEC SSTL 1/3 code or FSB applying AGTL+ bus technology and can be applied simultaneously to power supply for DDR-SDRAM memory and FSB bus terminal supporting different P4 CPUs without any additional peripheral circuit.

Description

Improve the bus termination adjusters of using of circuit more

Technical field

The utility model relates to a kind of integrated circuit (IC)-components, exactly, relates to a kind of the many with bus termination voltage adjuster (Bus Termination Regulator) of circuit that improve, and belongs to apparatus for adjusting power supply technical field in the computer organization parts.

Background technology

Current computer has extensively adopted DDR-SDRAM as Installed System Memory and display memory equipment.DDR-SDRAM defers to the bus specification of JEDEC SSTL 2/3, need satisfy the bus termination coupling power supply with Source and Sink ability that logic level and static transient state require.

The motherboard of current employing DDR-SDRAM or display card are at DDR-SDRAM bus termination coupling power pack, and extensively adopting specially is the terminal voltage adjuster integrated circuit of its exploitation.According to the power consumption requirement, much be the encapsulation of adopting SO-8 wherein, volume is small and exquisite, and precision consistance and reliability are all than higher, and it is convenient to use, and low price, and the market acceptance is the RT9173A of Taiwan Richtek company than higher representative.The LP2995 that U.S. NS company releases has done further improvement again, and reference voltage 1/2 potential-divider network of being made up of two precision resistances that RT9173A is required is integrated into chip internal, has improved precision, makes application more convenient.

But, along with development of computer, the speed fast lifting of processor and bus, Intel is about to the motherboard platform 865G series of new generation release in 2003, it adopts the Front Side Bus FSB of AGTL+ (AssistedGunning Transceiver Logic) bussing technique also to begin the bus termination coupling power supply Vtt that requirement has Source and Sink ability, and the 865G platform can be supported the P4 CPU of present Northwood kernel simultaneously and the P4 CPU of the Prescott kernel released for the end of the year 2003.The logic level of the bus termination coupling power supply that these two kinds of kernel CPU require is different, is respectively 1.45V and 1.225V.Like this, though bus termination coupling power requirement does not partly have essential difference with DDR, make to have the LP2995 that fixes 1/2 potential-divider network reference voltage and cannot use at the FSB place at all, RT9173 then will increase loaded down with trivial details peripheral circuit.So on the 865G platform, people are faced with two alternatives: select DDR to use LP2995 and FSB RT9173, increased the cost of part category and buying and maintenance; Perhaps select DDR and FSB all to use RT9173, all will increase peripheral circuit.(because the circuit of discrete device is loaded down with trivial details, do not have defencive function again, so poor reliability is not in the discussion scope).So, present terminal voltage adjuster integrated circuit substantially all belongs to RT9173 and LP2995 two major types, still do not have now a kind of many can the above-mentioned two-part designing requirement of simultaneous adaptation under the situation of using peripheral circuit hardly with the bus termination voltage adjuster.

Summary of the invention

The purpose of this utility model provides a kind of bus termination voltage adjuster that improves circuit structure, this integrated circuit only needs the internal circuit of existing bus termination voltage adjuster is improved a little, promptly can meet the bus termination coupling requirement of the DDR-SDRAM that adopts JEDEC SSTL 2/3 standard, or adopt the FSB terminal of AGTL+ bussing technique to mate requirement, be used for DDR-SDRAM internal memory and the FSB bus termination power supply of supporting different P4 CPU simultaneously, and do not need to increase in the periphery again additional circuit.

The purpose of this utility model is achieved in that a kind of bus termination voltage adjusters of using that improve circuit more, require to adopt the SO8 encapsulation according to power consumption, its internal circuit comprises existing bus termination voltage adjuster, it is characterized in that: the input end at this bus termination voltage adjuster is set up: CPU is gone up the type selecting signal, and (the pin sequence number is generally AD1 on present P4 CPU, pin is called BOOTSEL) BootSelect differentiates and the AGTL+ bus signals isolated and the cpu type that is converted to the operation level of bus termination voltage adjuster own is differentiated and level shifting circuit, according to the reference voltage control switching circuit that cpu type produces the Front Side Bus FSB reference voltage-regulating circuit of second reference voltage Vref-2 and selects corresponding reference voltage to export, three functional circuits orders connect successively; Another input end at the reference voltage control switching circuit is connected with the 1/2 dividing potential drop reference voltage circuit of fixing that produces first reference voltage Vref-1.The reference voltage control switching circuit is given to existing bus termination voltage adjuster kernel with correct reference voltage, produces the output voltage that meets application requirements.

Described cpu type is differentiated and level shifting circuit includes signal discrimination circuit and level shifting circuit, its circuit can be to be connected to form by two NPN triodes, wherein the base stage of first transistor circuit is an input end, the base stage of second transistor circuit directly is connected with first transistorized collector, its collector is an output terminal, and two transistorized emitters altogether.

Described cpu type is differentiated and level shifting circuit includes signal discrimination circuit and level shifting circuit, its circuit also can be to be connected to form by a NPN transistor circuit and a PNP transistor circuit, wherein the base stage of NPN transistor circuit is an input end, the emitter of PNP transistor circuit connects power supply, its base stage is connected to the collector of NPN transistor by resistance, its collector is by a resistance eutral grounding, and its collector is an output terminal.

Described FSB reference voltage-regulating circuit is that the bleeder circuit of the variable intrinsic standoff ratio of a field effect transistor and three series resistor formations is formed, the grid of field effect transistor is an input end, its drain electrode is connected on the 3rd resistance two ends respectively with source electrode, is output terminal between first resistance and second resistance.

Described reference voltage control switching circuit can be any alternative commutation circuit,

Described reference voltage control switching circuit is to utilize the gauge tap of the V_MEM power supply of DDR_SDRAM power supply in the system as two triple gates, and when being applied to the DDR circuit, output is fixed as first reference voltage Vref-1 of 1/2 V_MEM respectively; When being applied to the FSB circuit, still be Prescott kernel P4 CPU then according to being to use Northwood kernel P4 CPU in the system, export second reference voltage Vref-2 of 1.45V or 1.225V respectively.

Describedly fix the potential-divider network that 1/2 dividing potential drop reference voltage circuit is made up of two precision resistances.

The encapsulation of described this bus termination voltage adjuster can be SO-8, and its pin is respectively: input power supply V _DDQ(IN), output V _TT(OUT), IC internal logic power supply V _{CC_IC}Earth terminal GND, CPU starts selecting side BootSelect (BTSEL), system DDR feeder ear V_MEM, and the V_REF of reference voltage and confession are selected for use, the nonessential output feedback input end V_FB more accurately that makes for the reference voltage network of the variable intrinsic standoff ratio of FSB provides.

Described first reference voltage Vref-the 1st is fixed the reference voltage of 1/2 intrinsic standoff ratio, its magnitude of voltage is fixed as V_MEM/2, second reference voltage Vref-the 2nd still is Prescott kernel P4 CPU according to using Northwood kernel P4 CPU in the system, and its magnitude of voltage is respectively 1.45V or 1.225V.

Having of described this bus termination voltage adjuster confessed (Source) and drawn the output V of (Sink) ability _TT(OUT), be to produce according to the reference voltage that the reference voltage control switching circuit is exported, when being applied to the DDR circuit, it is output as 1/2 V_MEM respectively; When in being applied to Front Side Bus FSB Circuits System, using Northwood kernel P4 CPU, output 1.45V; When in being applied to Front Side Bus FSB Circuits System, using Prescott kernel P4 CPU, output 1.225V.

The utility model is the improved bus termination voltage adjuster of a kind of circuit, this bus termination voltage adjuster is at the some circuit of the inner increase of existing bus termination voltage adjuster, only needing externally during use, circuit carries out simple wires, promptly can meet the bus termination requirement of the DDR-SDRAM that adopts JEDEC SSTL 2/3 standard, or meet Front Side Bus (FSB) demanding terminal that adopts the different P4 CPU of AGTL+ bussing technique, can realize only using with a kind of bus termination voltage adjuster, be DDR-SDRAM internal memory on the computer platform of Intel 865G one class and the FSB bus termination power supply of supporting different P4 CPU, and do not need to increase in the periphery again additional circuit.Be particularly suitable for supporting simultaneously the DDR-SDRAM internal memory and support Intel existing (Northwood kernel) and in the future the motherboard of (Prescott kernel) P4 CPU select for use.

The utility model only needs to increase several resistance devices and MOSFET when integrated circuit silicon chip designs, substantially can not increase the manufacturing cost of integrated circuit, but can greatly simplify peripheral circuit, make the system designer save the additional devices and the circuit that originally need increase in the periphery, save the PCB space, reduced total cost.And the relevant quality of bus termination voltage adjuster product of the present utility model is not influenced by peripheral components can, and precision consistance and reliability all are improved; For manufacturer and user, as long as can satisfying two aspects, use a kind of materials and parts, reduced the materials and parts kind of final products, can reduce expenses at all too many levels such as plan, buying, storage, design, manufacturing and maintenances, reduce risk.

Description of drawings

Fig. 1 is the electric theory diagram of existing bus termination voltage adjuster internal circuit.

Fig. 2 is the electrical schematic diagram of the utility model bus termination voltage adjuster.

Fig. 3 fixes 1/2 dividing potential drop reference voltage network embodiment schematic diagram in the utility model.

Fig. 4 is that cpu type is differentiated and an embodiment schematic diagram of level shifting circuit in the utility model.

Fig. 5 is that cpu type is differentiated and another embodiment schematic diagram of level shifting circuit in the utility model.

Fig. 6 is a FSB reference voltage-regulating circuit embodiment schematic diagram in the utility model.

Fig. 7 is a reference voltage control switching circuit embodiment schematic diagram in the utility model.

Fig. 8 is the application circuit embodiment schematic diagram that the utility model produces Vtt_MEM.

Fig. 9 is the application circuit embodiment schematic diagram that the utility model produces Vtt_FSB.

Embodiment

Referring to Fig. 2, the utility model is a kind of bus termination voltage adjusters of using that improve circuit more, require to adopt the SO-8 encapsulation according to present power consumption, its internal circuit comprises existing bus termination voltage adjuster 1, its circuit improvements are to set up at the input end of this bus termination voltage adjuster 1: to CPU go up sequence number be AD1 " start and select " (BootSelect) the pin signal differentiate and the AGTL+ bus signals isolated and the cpu type that is converted to the operation level of bus termination voltage adjuster own is differentiated and level shifting circuit 2, according to the cpu type signal, 4, three functional circuits 2 of reference voltage control switching circuit that produce the FSB reference voltage-regulating circuit 3 of second reference voltage Vref-2 and select corresponding reference voltage to export, 3,4 orders connect successively; Another input end at reference voltage control switching circuit 4 is connected with the 1/2 dividing potential drop reference voltage circuit 5 of fixing that produces first reference voltage Vref-1.The reference voltage control switching circuit is given to existing bus termination voltage adjuster kernel with correct reference voltage, produces the output voltage that meets application requirements.

Because confessing (source) and drawing the ability of (sink) electric current of DDR-SDRAM internal memory and the FSB bus termination coupling power supply that requires is approaching, the power that chip self dissipates is basic identical, so how the utility model still can adopt original SO-8 encapsulation with the bus termination voltage adjuster, but owing to increased new function, therefore need need redefine layout to original pin, its pin is respectively: input power supply V _DDQ(IN), output V _TT(OUT), IC internal logic power supply V _{CC_IC}Earth terminal GND, CPU starts selecting side BootSelect (BTSEL), system DDR feeder ear V_MEM, make output feedback input end V_FB (, in schematic diagram-Fig. 2 of the present utility model, not showing) more accurately for what the reference voltage network of the variable intrinsic standoff ratio of FSB provided that the V_REF of reference voltage and confession select for use because V_FB is nonessential; Make it more realistic application demand.

Each circuit how the utility model is set up with the bus termination voltage adjuster specifies below:

Referring to Fig. 3, at first, at the DDR certain applications, 1/2 dividing potential drop reference voltage network 5 is fixed in the utility model increase.Because DDR partly requires bus termination voltage V _TT(OUT) need to keep 1/2 of DDR supply voltage V_MEM, and follow the variation of V_MEM and change, so reference voltage should not adopt fixedly 1.25V, the utility model will be integrated in the chip by the potential-divider network that two precision resistance R1 and R2 form, and first reference voltage Vref-1 of fixing 1/2 intrinsic standoff ratio is provided for output driving circuit in the chip.Can satisfy power requirement like this, simplify external circuit, and make output accuracy not be subjected to external devices to influence (the bus termination voltage adjusters of using of fixing 1/2 dividing potential drop reference voltage network have been arranged more, do not need to increase again fix 1/2 dividing potential drop reference voltage network) for this class of LP2995.

Secondly, at the FSB certain applications, the utility model has increased the cpu type differentiation and level shifting circuit 2, FSB reference voltage-regulating

circuit

3 and 4, three functional circuits of reference voltage control switching circuit, 2,3,4 orders connect successively.Below respectively it is described.

Referring to Fig. 4, cpu type is differentiated and the effect of level shifting circuit 2 is that output reference voltage keeps 1.45V when using Northwood kernel P4CPU, and output reference voltage keeps 1.225V when using Prescott kernel P4 CPU.This cpu type is differentiated and level shifting circuit 2 is differentiated by type signal and level conversion two parts circuit is formed.Wherein the cpu type signal discrimination circuit mainly utilizes CPU to go up the BootSelect pin of sequence number for AD1, and this pin level of Northwood kernel P4 CPU is low (Low), and this pin level of Prescott kernel P4 CPU is high (Hi).But because be AGTL+ signal (level has only about 1.5V) on the FSB, be connected, must carry out level conversion with the bus termination voltage adjuster kernel of CMOS (or Bi-CMOS) technology.Fig. 4, Fig. 5 have introduced the electrical schematic diagram of two circuit embodiments that can specifically adopt respectively.Be to connect to form among Fig. 4 by two NPN triode Q3, Q4 circuit, wherein the base stage of first transistor circuit is an input end, the base stage of second transistor circuit directly is connected with first transistorized collector, and its collector is an output terminal, and two transistorized emitters altogether.Promptly utilize Q3, the Q4 transistor circuit is with the AGTL+ Signal Spacing and be converted to the Vcc_Drive level signal, the required voltage of promptly former bus termination voltage adjuster kernel driven MOS pipe.This cpu type is differentiated and level shifting circuit 2 can have multiple implementation method, and Fig. 5 is its another embodiment.Fig. 5 is connected to form by a NPN transistor Q5 and a PNP transistor Q6, wherein the base stage of NPN transistor Q5 circuit is an input end, the emitter of PNP transistor Q6 circuit connects power supply, its base stage is connected to the collector of NPN transistor Q5 by resistance R 11, its collector is by a resistance R 12 ground connection, and its collector is an output terminal.

Then, increase FSB reference voltage-regulating circuit 3.Utilize the cpu type judgment signal that IC internal logic level requires that meets of cpu type differentiation and level shifting circuit 2 generations, just can adjust generation second reference voltage Vref-2 that the rear end potential-divider network changes intrinsic standoff ratio.FSB reference voltage-regulating circuit 3 is to utilize the reference voltage potential-divider network of a variable intrinsic standoff ratio to realize, referring to Fig. 6.This circuit selects that V3.3STB is reference voltage V _ REF on the mainboard for use, because the V3.3STB on the mainboard is transformed through mu balanced circuit, is substantially can be with power source change, and is quite accurate.When on the mainboard Prescott CPU being installed, the CONTROL signal is high (Hi), field effect transistor Q8 conducting, and then resistance R 22 no longer participates in dividing potential drop, can Vref-2 accurately be adjusted into 1.225V by regulating the value of R20 and R21 during debugging; When on the mainboard Northwood CPU being installed, the CONTROL signal is low (Low), and field effect transistor Q8 ends, and then R22 and R21 series connection and R20 dividing potential drop can accurately be adjusted into 1.45V with Vref-2 by regulating the value of R22 during debugging.Make that like this output Vref-2 keeps 1.45V when using Northwood kernel P4 CPU, output Vref-2 keeps 1.225V when using Prescott kernel P4 CPU.

At last, increase reference voltage control switching circuit 4.The commutation circuit of the in fact available any alternative of this circuit realizes.Only need to use a simple electronic switch, between second reference voltage Vref-2 of first reference voltage Vref-1 of fixing 1/2 V_MEM and 1.45V or 1.225V, carry out switching controls, result with alternative exports to bus termination voltage adjuster control output driving circuit, this control output driving circuit effect such as same operational amplifier, promote the MOSFET of back level, the level that produces the ability with source and sink electric current is the V of 1/2V_MEM or 1.45V or 1.225V _TTOutput.Fig. 7 is its a kind of embodiment, here utilize the gauge tap of the V_MEM of DDR_SDRAM power supply in the system as two triple gates, when being applied to the DDR circuit, V_MEM is connected on the DDR power supply, then first reference voltage Vref-1 conducting, second reference voltage Vref-2 is ended; When being used in the FSB circuit, the V_MEM outside does not connect, thus meet GND by the divider resistance of IC inside, then second reference voltage Vref-2 conducting, first reference voltage Vref-1 is ended.

Use bus termination voltage adjuster of the present utility model when DDR part that is applied to the motherboard design and FSB part, peripheral circuit as long as be communicated with corresponding signal, no longer needs peripheral components except the power filtering capacitor of necessity, very simple and direct.

Shown in Figure 8 is that the utility model is used for the DDR part, produces the V of DDR terminal power supply _TTThe application circuit embodiment of (being Vtt_MEM).Input power supply V _DDQ(IN) with as the inner gauge tap V_MEM that selects reference voltage Vref-1, receive DDR power supply VDD_MEM in the system together; IC internal logic power supply V _{CC_IC}Receive 3.3V power Vcc 3 in the system; The earth terminal of earth terminal GND connected system; Output V _TT(OUT) connect DDR terminal power supply Vtt_MEM, and add necessary filter capacitor; CPU starts selecting side BTSEL and provides two pins of V_REF of reference voltage to connect for the reference voltage network of the variable intrinsic standoff ratio of FSB.If also have feedback input end V_FB, as long as it and V _TT(OUT) connection gets final product.

Shown in Figure 9 is that the utility model is used for Front Side Bus FSB part, produces the V of FSB terminal power supply _TTThe application circuit embodiment of (being Vtt_FSB).Input power supply V _DDQ(IN) with as the V of IC internal logic power supply _{CC_IC}Receive 3.3V power Vcc 3 in the system together; CPU starts selecting side BTSEL connection CPU and goes up the BOOTSELECT that the AD1 pin is sent; For providing the V_REF of reference voltage, the reference voltage network of the variable intrinsic standoff ratio of FSB is connected to the power supply V3.3STB that is converted through mu balanced circuit in the system; The earth terminal of earth terminal GND connected system, output V _TT(OUT) connect FSB terminal power supply Vtt_FSB, and add necessary filter capacitor, the inner gauge tap V_MEM pin of reference voltage Vref-1 of selecting is unsettled, need not connect.If also have feedback input end V_FB, as long as it and V _TT(OUT) connection gets final product.

The utility model is only done the elaboration of method, principle to the improvement circuit of bus termination adjuster; physical circuit method for designing according to this thinking is not done any qualification; to any part of the utility model circuit design or circuit integrated, disassemble, combination, refinement, imitation, all should be included within the protection domain.

Claims

1, a kind of bus termination voltage adjusters of using that improve circuit more, its internal circuit comprises existing bus termination voltage adjuster, it is characterized in that: the input end at this bus termination voltage adjuster is set up: cpu type differentiation and the level shifting circuit of the last type selecting signal of CPU being differentiated and the AGTL+ bus signals is isolated and is converted to the operation level of bus termination voltage adjuster own, according to the reference voltage control switching circuit that cpu type produces the Front Side Bus FSB reference voltage-regulating circuit of second reference voltage Vref-2 and selects corresponding reference voltage to export, three functional circuits orders connect successively; Another input end at the reference voltage control switching circuit is connected with the 1/2 dividing potential drop reference voltage circuit of fixing that produces first reference voltage Vref-1.

2, the bus termination voltage adjusters of using of improvement circuit according to claim 1 more, it is characterized in that: described cpu type is differentiated and level shifting circuit includes signal discrimination circuit and level shifting circuit, its circuit can be to be connected to form by two NPN triodes, wherein the base stage of first transistor circuit is an input end, the base stage of second transistor circuit directly is connected with first transistorized collector, its collector is an output terminal, and two transistorized emitters altogether.

3, the bus termination voltage adjusters of using of improvement circuit according to claim 1 more, it is characterized in that: described cpu type is differentiated and level shifting circuit includes signal discrimination circuit and level shifting circuit, its circuit also can be to be connected to form by a NPN transistor circuit and a PNP transistor circuit, wherein the base stage of NPN transistor circuit is an input end, the emitter of PNP transistor circuit connects power supply, its base stage is connected to the collector of NPN transistor by resistance, its collector is by a resistance eutral grounding, and its collector is an output terminal.

4, the bus termination voltage adjusters of using of improvement circuit according to claim 1 more, it is characterized in that: described FSB reference voltage-regulating circuit is that the bleeder circuit of the variable intrinsic standoff ratio of a field effect transistor and three series resistor formations is formed, the grid of field effect transistor is an input end, its drain electrode is connected on the 3rd resistance two ends respectively with source electrode, is output terminal between first resistance and second resistance.

5, the bus termination voltage adjusters of using of improvement circuit according to claim 1 more, it is characterized in that: described reference voltage control switching circuit can be any alternative commutation circuit,

6, the bus termination voltage adjusters of using of improvement circuit according to claim 5 more, it is characterized in that: described reference voltage control switching circuit is to utilize the gauge tap of the V_MEM power supply of DDR_SDRAM power supply in the system as two triple gates, when being applied to the DDR circuit, output is fixed as first reference voltage Vref-1 of 1/2V_MEM respectively; When being applied to Front Side Bus FSB circuit, still be Prescott kernel P4 CPU then according to being to use Northwood kernel P4 CPU in the system, export second reference voltage Vref-2 of 1.45V or 1.225V respectively.

7, the bus termination voltage adjusters of using of improvement circuit according to claim 1 is characterized in that more: describedly fix the potential-divider network that 1/2 dividing potential drop reference voltage circuit is made up of two precision resistances.

8, the bus termination voltage adjusters of using of improvement circuit according to claim 1, it is characterized in that: the encapsulation of described this bus termination voltage adjuster can be SO-8, and its pin is respectively: input power supply V more _DDQ(IN), output V _TT(OUT), IC internal logic power supply V _{CC_IC}Earth terminal GND, CPU starts selecting side BOOTSELECT (BTSEL), system DDR feeder ear V_MEM, and the V_REF of reference voltage and confession are selected for use, the nonessential output feedback input end V_FB more accurately that makes for the reference voltage network of the variable intrinsic standoff ratio of FSB provides.

9, the bus termination voltage adjusters of using of improvement circuit according to claim 1 is characterized in that more: described first reference voltage Vref-the 1st, fix the reference voltage of 1/2 intrinsic standoff ratio, and its magnitude of voltage is fixed as V_MEM/2; Second reference voltage Vref-the 2nd still is Prescott kernel P4 CPU according to using Northwood kernel P4 CPU in the system, and its magnitude of voltage is respectively 1.45V or 1.225V.

10, according to Claim 8 or the bus termination voltage adjusters of using of 9 described improvement circuit, it is characterized in that: having of described this bus termination voltage adjuster confessed (Source) and drawn the output V of (Sink) ability more _TT(OUT), be to produce according to the reference voltage that the reference voltage control switching circuit is exported, when being applied to the DDR circuit, it is output as 1/2V_MEM respectively; When in being applied to Front Side Bus FSB Circuits System, using Northwood kernel P4 CPU, output 1.45V; When in being applied to Front Side Bus FSB Circuits System, using Prescott kernel P4 CPU, output 1.225V.