CN2560949Y

CN2560949Y - Direct-current collecting device

Info

Publication number: CN2560949Y
Application number: CN 02235348
Authority: CN
Inventors: 周全; 刘万峰
Original assignee: YANTAI DONGFANG ELECTRONIC INFORMATION INDUSTRY Co Ltd
Current assignee: YANTAI DONGFANG ELECTRONIC INFORMATION INDUSTRY Co Ltd
Priority date: 2002-05-31
Filing date: 2002-05-31
Publication date: 2003-07-16
Anticipated expiration: 2012-05-31

Abstract

The utility model discloses a DC rate collecting device, wherein, a terminal interface (1) behind a casing is connected with a preceding stage filter circuit network (2) through a contact pin, a temperature automatic calibration circuit (9), a preceding stage filter circuit network (2), a difference scale adjusting circuit (8) and a channel control circuit (4) are connected with an analog quantity change-over switch device (3) through a printed circuit, the difference scale adjusting circuit (8) is connected with a A/D converter (7) and a channel control circuit (4) through the printed circuit, the A/D converter (7) is connected with the FPGA site programmable logic device (5) through the printed circuit and the FPGA site programmable logic device (5) is connected with a CPU processor plug piece (6) through a flat cable. The utility model can be extensively used for the DC rate collection of an electric power system, an electrified railroad traction power supply system ad an industry control system.

Description

A kind of DC quantity harvester

1, technical field

The utility model relates to a kind of DC quantity harvester that is applicable in electric system, electric railway traction power supply system and the industrial control system.

2, background technology

The various DC quantity harvesters or the unit that use in China's electric system, electric railway traction power supply system and industrial control system at present, methods such as general direct employing approaches one by one, V/F conversion or ∑-Δ are carried out the DC quantity collection.Often there is the contradiction of sample rate and vulnerability to jamming in these methods, especially under electromagnetic compatibility requires than higher environment for use, realize that the synchronous raising of sample rate and vulnerability to jamming level just becomes difficult more.

3, summary of the invention

The purpose of this utility model provides a kind of Novel DC amount harvester, to remedy the deficiency of existing DC quantity acquisition technique, improves sample rate and vulnerability to jamming level synchronously.

In order to reach the purpose of this utility model, the utility model is achieved in that a kind of DC quantity harvester, by terminal interface behind the cabinet (1), prime filtering circuit network (2), analog quantity change-over switch device (3), channel control circuit (4), FPGA field programmable logic device (5), CPU processor card (6), A/D converter (7), the difference ratio is adjusted circuit (8), and temperature auto-calibration circuits (9) is formed, terminal interface behind the cabinet (1) is by the contact pin temperature auto-calibration circuits (9) that is connected with prime filtering circuit network (2), prime filtering circuit network (2), the difference ratio is adjusted circuit (8) and is connected with analog quantity change-over switch device (3) by track respectively with channel control circuit (4), the difference ratio is adjusted circuit (8) and is connected with channel control circuit (4) with A/D converter (7) respectively by track, A/D converter (7) is connected with FPGA field programmable logic device (5) by track, and FPGA field programmable logic device (5) is connected by flat cable with CPU processor card (6).

The utlity model has following advantage: the first, the utility model adopts the FPGA field programmable logic device to control the channel selecting of sampling in real time, the gain of amplifier, and signal type is selected (voltage/current), the sampling interval of discrete sampling; The second, by the discrete sampling of high-speed real-time and the ram cell of FPGA field programmable logic device inside, can realize the continuity of sampling, greatly shortened holding time to the CPU processor, simultaneously, can eliminate power frequency well by software algorithm and disturb and various electromagnetic interference (EMI), reach very high electromagnetic compatibility grade; Three, the utlity model has ethernet, RS232 serial port, two kinds of field-bus interfaces such as CAN, and the optional optical fiber interface of using are realized intelligent requirements; Four, the utility model not only can isolated operation, and can group net operation, as ethernet, and fieldbus network etc.; Five, the utility model has been realized the electrical isolation of simulation part and numerical portion; Six, the utility model adopts advanced temperature-compensation circuit, can satisfy the stability of precision in wide temperature range (25 ℃～+ 55 ℃);

4, description of drawings

Fig. 1 is a general principles block diagram of the present utility model;

Fig. 2 is a prime filtering circuit of the present utility model;

Fig. 3 is a channel control circuit of the present utility model;

Fig. 4 is that difference ratio of the present utility model is adjusted circuit.

5, embodiment

Be illustrated the utility model for illustrating better below in conjunction with accompanying drawing.

Wherein figure number: x represents the sequence number of the type device, and Vx is TVS; Cx is a capacitor; Dx is an integrated circuit; Ex is a photoelectrical coupler; Lx is a magnetic bead; Rx is a resistor.

The utility model by cabinet after terminal interface 1, prime filtering circuit network 2, analog quantity change-over switch device 3, channel control circuit 4, FPGA field programmable logic device 5, CPU processor card 6, A/D converter 7, the difference ratio is adjusted circuit 8, and composition such as temperature auto-calibration circuits 9, the DC quantity signal arrives analog quantity change-over switch device 3 through prime filtering circuit network 2, the internal logic control channel control circuit 4 of FPGA field programmable logic device 5 switches analog quantity change-over switch device 3 thereby reach, and realizes channel selecting and ratio adjustment that DC quantity is gathered, cycle data after A/D converter 7 conversion stores in the FPGA field programmable logic device 5 the most at last, the reading and start the next sampling period of waiting for CPU processor card 6.

The utility model adopts the FPGA field programmable logic device, by to its programming, automatically channel control circuit and difference ratio adjustment circuit are controlled in real time, switch different measurement passages, adjust corresponding measurement range, realize high speed discrete sampling all input circuits.Simultaneously, disturb by software algorithm filtering power frequency.

The utility model adopts electric capacity, TVS ground networks and magnetic bead, and with the high frequency interference in the DC quantity signal, balance resistance is used to realize the balance input of DC quantity.Simultaneously, by changing the setting of short-circuiting device, realize the mixing setting of the voltage and the magnitude of current.

The utility model adopts channel control circuit and difference ratio to adjust circuit at the FPGA field programmable logic

Under the control of device inside logic, realize voltage, current system, the real time calibration of temperature coefficient and the online setting of different gains.

Embodiment 1:

As shown in Figure 1, the DC quantity signal arrives analog quantity change-over switch device 3 through prime filtering circuit network 2, the internal logic control channel control circuit 4 of FPGA field programmable logic device 5, switch analog quantity change-over switch device 3 thereby reach, realize channel selecting and ratio adjustment that DC quantity is gathered, cycle data after A/D converter 7 conversion stores in the FPGA field programmable logic device 5 the most at last, the reading and start the next sampling period of waiting for CPU processor card 6.Simultaneously, can save the holding time of CPU, guarantee the continuity of sampling.The temperature auto-calibration circuits adopts the precision resistance network and the reference voltage source chip of high-temperature stability, under laboratory condition, with high precision reference source calibration coefficient, the output signal of real-time sampling temperature auto-calibration circuits in the sampling process, by the automatic calibration of special algorithm realization temperature effect, can guarantee to satisfy in the wide temperature range (25 ℃～+ 55 ℃) stability of precision;

Embodiment 2:

Prime filtering circuit as shown in Figure 2, C1, C2 are filter capacitor, and V1, V2 are the TVS pipe, and L1, L2 are magnetic bead, and the three realizes the weakening effect of high-frequency interferencing signal jointly; R1, R4 are the sampling resistor of voltage input mode; R2, R5 are the balance resistance of electric current input mode, and R3 is the sampling resistor of current system; X1, X2 are short-circuiting device, are provided with by changing it, can realize the selection of voltage/current mode.After the selection of process filtering and electric current, voltage system, signal is delivered to the analog quantity change-over switch respectively.

Embodiment 3:

Channel control circuit as shown in Figure 3, R12～R20 are resistance, R12 wherein, and R15 and R18 play metering function, draw effect on all the other 6 resistance play; E1～E3 is a photoelectrical coupler, is used for isolating simulation

Part and numerical portion; D5, D6 is an integrated circuit, plays serial/parallel conversion, is used to realize that serial data controls to parallel data.S0 shown in the figure, PCS0, PCLK0 are the serial control signal that the FPGA field programmable logic device sends.By the control command that the CPU primary processor sends, can revise the gain of sample frequency, voltage/current selection and amplifying return circuit flexibly, thereby the mixing that realizes polymorphic type and multirange sampling is carried out.

Embodiment 4:

Difference ratio is as shown in Figure 4 adjusted circuit, and R6～R11 is a resistance, and wherein R11 is the balance stake resistance of operational amplifier, and R6～R10 is the gain control resistance of ratio amplifier, works to regulate gain; D1 is a differential operational amplifier, and the conversion of signals that balance is imported becomes single-ended bipolar signal, delivers to A/D converter via ratio amplifier loop.Ratio is adjusted circuit by resistance R 6～R11, operational amplifier D2, and analog quantity change-over switch device D3 forms jointly.Ratio adjustment control is accepted channel control circuit control by D3, adjusts gain.Wherein analog quantity change-over switch device D4 realizes jointly that with the prime filtering circuit passage switches under channel control circuit control.

Claims

1, a kind of DC quantity harvester, by terminal interface behind the cabinet (1), prime filtering circuit network (2), analog quantity change-over switch device (3), channel control circuit (4), FPGA field programmable logic device (5), CPU processor card (6), A/D converter (7), the difference ratio is adjusted circuit (8), and temperature auto-calibration circuits (9) is formed, it is characterized in that: terminal interface behind the cabinet (1) is connected with prime filtering circuit network (2) by contact pin, temperature auto-calibration circuits (9), prime filtering circuit network (2), the difference ratio is adjusted circuit (8) and is connected with analog quantity change-over switch device (3) by track respectively with channel control circuit (4), the difference ratio is adjusted circuit (8) and is connected with channel control circuit (4) with A/D converter (7) respectively by track, A/D converter (7) is connected with FPGA field programmable logic device (5) by track, and FPGA field programmable logic device (5) is connected by flat cable with CPU processor card (6).