CN2547007Y - Non-volatile random storage with carbon nano-tube structure - Google Patents
Non-volatile random storage with carbon nano-tube structure Download PDFInfo
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- CN2547007Y CN2547007Y CN 02237210 CN02237210U CN2547007Y CN 2547007 Y CN2547007 Y CN 2547007Y CN 02237210 CN02237210 CN 02237210 CN 02237210 U CN02237210 U CN 02237210U CN 2547007 Y CN2547007 Y CN 2547007Y
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Abstract
The utility model relates to a nonvolatile random memory with carbon nano-tube structure. The memory comprises an arbon nano-tube array with upper and lower layer on a underlay, wherein, the carbon nano-tube on each layer is a group of carbon nano-tubes arranged in parallel, the carbon nano-tube on the upper and lower layers are vertical and separated with each other, and each cross node of the two-layer carbon nano-tube structures a storage unit of the memory. The utility model discloses the adoption principle of various important parameters in the process of preparing the memory and the working conditions under which the apparatus have the optimal storage feature, resulting in solving the problems of traditional memory in such aspects as heat radiation, power consumption and stability in high-density integration.
Description
Technical field
The utility model belongs to memory device, particularly a kind of non-volatile random asccess memory of utilizing carbon nano-tube to make.
Background technology
Memory has occupied 40% share in whole world semi-conductor market, per 2 years of other semiconductor product beyond the memory is more of new generation, memory then is per 18 months generation, the example that develops into dynamic memory (DRAM), the size of each function element constantly reduces, price is in continuous decline, and the required number of electrons of each memory cell work is also fewer and feweri.Japan's live width of groove on silicon chip had reached 0.8 micron in 1988, and chip integration has reached 10
6More than the individual element, the dynamic random access memory DRAM of 4Mb comes out, thereby has entered the integrated ULS of imperial scale generation in man-hour; The 16Mb chip that live width in 1992 is 0.5 micron is gone into operation; The 64Mb chip that live width in 1994 is 0.35 micron is gone into operation; Soon just will realize the DRAM of 0.13 micron 4Gb.But keep the ever-reduced trend surface of yardstick facing to extremely serious challenge, be that electric capacity in the memory cell can not be too little, so whole memory will be flooded by noise to not providing abundant electronics to amplifier if this electric capacity is little, reliability that can not the guarantee information storage; Simultaneously, when the number of electrons of each memory cell becomes more and more hour because of the raising of integrated level, it is unstable that the MOS field-effect transistor in the memory will become gradually.For this reason, our more memory device of high integration of having to seek to have.And the development of nano material and nanofabrication technique makes nano-device obtain faster development, is with a wide range of applications.
In the past few years, research work mainly concentrates on the single-electron device, and some memory devices based on the single electron phenomenon are produced out, and demonstrates stable operating state under certain condition.But these single-electron devices are faced with a lot of problems, and some need improve working temperature, and some need improve operating frequency, and these single-electron devices have very complicated structure usually.In order to solve these difficulties, the carbon nano-tube of utilizing Thomas Rueckes has designed a kind of non-volatile random asccess memory (" science " Science, 2000,289,94), sort memory comprises two-layer carbon nano-tube, and the upper strata carbon nano-tube is to place on the little bearing that separates one by one, and each bearing is only placed a Single Walled Carbon Nanotube.Such structure has following three point defects: 1) spacing of the size of each bearing and bearing has the size of several nanometers even tens nanometers usually because be subjected to the restriction of technology, and the integrated level of device is difficult to improve like this; 2) technology of device is very complicated, the little bearing of each row and column must be remained on the straight line; 3) a large amount of bearings that separate are provided with obstacle for the accurate location of carbon nano-tube, because integrated back size of devices is very big, be difficult to a carbon nano-tube accurately is positioned on every row's the bearing and do not depart from and landing, the carbon nano-tube on bearing has taken place to come off and just may cause whole memory generation storage errors.
Summary of the invention
The purpose of this utility model is in order to overcome above-mentioned memory 3 defectives structurally, with accurate location that reaches carbon nano-tube and the purpose of avoiding carbon nano-tube to come off; In order to improve the storage density of memory, and make the speed of memory faster, finally realize the ultrahigh density storage of information, thereby a kind of non-volatile random asccess memory read-write, that have carbon nano tube structure is provided.
The purpose of this utility model is achieved in that
The non-volatile random asccess memory that the utility model provides with carbon nano tube structure, comprise with material that one deck oxidation insulating layer is arranged on the silicon chip as substrate, bilevel carbon nano pipe array is arranged on substrate, each layer carbon nano-tube be arranged in parallel, and be vertical and separated from one another mutually between the bilevel carbon nano-tube; The carbon nano-tube of lower floor directly is placed on the surface of substrate, relies on the interaction force of carbon nano-tube and table top to fix the carbon pipe; There is an insulated leg in parallel between the adjacent carbon nano-tube of per two lower floors, so just formed one group of bearing parallel to each other; The carbon nano-tube on upper strata is placed on these bearings, quantity of carbon nanotubes on every bearing is n (n＞1), carbon nano-tube fixes by the active force with bearing, so just realized the independence of each memory cell, each crossbar contact of two-layer carbon nano-tube is exactly a memory cell of memory thus; Form electrode at the two ends plated metal of two-layer each root carbon nano-tube up and down, just can realize the control of memory.
The carbon nano-tube that described each layer carbon nano-tube be arranged in parallel by n root or n bundle is formed, and wherein n is the positive integer more than 2.
Described carbon nano-tube is a Single Walled Carbon Nanotube.
Described insulated leg is with the oxidation insulating layer material on the silicon chip.
Advantage of the present utility model is: non-volatile random asccess memory of the present utility model, all be different from traditional memory from principle and structure, it uses Single Walled Carbon Nanotube as stock, unique electrical, mechanics and the chemical property of carbon nano-tube have been made full use of, therefore the memory construction of designing is more simpler than single-electron memory, neither be subjected to the influence of random background charge, can at room temperature work again; Utilize the active force of carbon nano-tube and bearing just can finish the integrated of device simultaneously, storage density reaches draws very much level (10
12), also more than the 100G hertz, heat radiation and power consumption are but all very little for operating frequency.This shows that sort memory is simple in structure and integrated easily, not only solved the difficulty that legacy memory faces, also avoided the problem of single-electron memory complex structure, integrated difficulty; Compare with the device of Thomas Rueckes, just can finish the integrated of device with bearing still less, during the carbon nano-tube of location, even whole carbon pipe departs from a bit, device just can operate as normal as long as do not influence each other between the memory cell, this shows that device prepares to be more prone to; Simultaneously, the chemical inertness of carbon nano-tube and good toughness have determined device to have very long useful life, these advantages make the predicament that the utility model is faced in can the evolution of fine solution memory, compare with the memory of other type, have many-sided advantage.
In a word, memory of the present utility model has the following advantages than legacy memory:
1) simple in structure, 2) operating frequency height, 3) storage density is big, 4) low in energy consumption, 5) heat dissipation capacity is little, and 6) integrated simple.
Description of drawings
The perspective view of a memory cell of Fig. 1 the utility model memory.
The side schematic view of a memory cell off status of Fig. 2 the utility model memory.
Memory cell of Fig. 3 the utility model memory is opened the side schematic view of state.
Memory cell of Fig. 4 the utility model memory is applied to the state of the potential pulse on the electrode when off status changes by the state of opening.
Memory cell of Fig. 5 the utility model memory is applied to the state of the potential pulse on the electrode when opening state variation by off status.
Memory cell storage of Fig. 6 the utility model is applied to the state of the potential pulse on the electrode in the sense data process.
Fig. 7 represents the potential energy value of system and the relation of two-layer carbon nano-tube initial separation.
Memory cell of Fig. 8 the utility model memory is in the potential energy characteristics of system under the data preservation state.
The potential variation trend of memory cell of Fig. 9 the utility model memory when opening state variation to off status.
Potential variation trend when memory cell of Figure 10 the utility model memory changes to out state by off status.
The schematic perspective view of 3 * 3 storage matrix that the integrated back of Figure 11 forms.
The floor map of Figure 12 3 * 3 storage matrix.
Indicate among the figure:
1. the electrode of electrode 2. lower floor's carbon nano-tube of upper strata carbon nano-tube
3. silicon dioxide insulating layer 4. substrates
5. insulated leg 6. lower floor's carbon nano-tube
7. first memory cell in upper strata carbon nano-tube 8. storage arrays
9. the 3rd memory cell in second memory cell, 10. storage arrays in the storage array
10. electrode
Embodiment
Embodiment 1:
The substrate of selecting for use 4 is that the method for utilizing ion to inject on the silicon chip of a kind of (001) orientation forms highly doped p type silicon conducting layer.Utilize the wet-oxygen oxidation method, oxidizing temperature is 800 ℃, and oxidation goes out the silicon dioxide insulating layer 3 of one 25 nanometer thickness.
Its insulated leg 5 is on silicon dioxide insulating layer 3, utilizes lithographic technique to prepare the silicon dioxide insulator bearing 5 of several rows of high 2 nanometers * wide 3 nanometers, and insulated leg 5 spacings are 10 nanometers.
The array that is placed with 3 parallel carbon nano-tube compositions on substrate 4 is a lower floor, relies on the interaction force of carbon nano-tube and substrate to fix the carbon pipe; There is an insulated leg in parallel 5 between per two adjacent lower floor's carbon nano-tube 6, so just formed one group of bearing parallel to each other; The carbon nano-tube 7 on upper strata is placed on this insulated leg 5, fix carbon nano-tube 7 by active force with insulated leg 5, so just realized the independence of each memory cell, this moment, each crossbar contact of two-layer carbon nano-tube was exactly a memory cell of memory.Vertical and separated from one another mutually between the two-layer up and down carbon nano-tube; Form electrode 10 at the two ends plated metal of two-layer each root carbon nano-tube up and down, just can realize the control of memory.
Embodiment 2:
The substrate of selecting for use 4 is that the method for utilizing ion to inject on the silicon chip of a kind of (001) orientation forms highly doped p type silicon conducting layer.Utilize the wet-oxygen oxidation method, oxidizing temperature is 800 ℃, and oxidation goes out the silicon dioxide insulating layer 3 of one 25 nanometer thickness.
Select earth silicon material as the insulated leg material, utilize lithographic technique to prepare several rows of bearing 5, the height of insulated leg 5 is 2 nanometers, and spacing is 10 nanometers.Deposit two gold electrodes 1 or 2 with sputtering method this moment on the direction in parallel of the both sides of device isolation bearing 5, width is 150 nanometers, height is 5 nanometers, utilize etching to become several portions to form these two dividing electrodes, each part is separate, can be used as the electrode 2 of upper strata carbon nano-tube.After utilizing this moment the probe of atomic force microscope to move carbon nano-tube formation lower floor carbon nano pipe array, carry out the arrangement of upper strata carbon nano-tube.The two ends of each root carbon nano-tube ride on the electrode for preparing 2 in the upper strata carbon nano-tube 7, and each electrode only allows above a Single Walled Carbon Nanotube is placed on.The two ends of each root carbon nano-tube in lower floor's carbon nano-tube 6 are deposited the gold of one deck 50 nanometer thickness with sputtering method, form the electrode 1 of lower floor's carbon nano-tube.At last device is encapsulated.
Embodiment 3:
The preparation of table top and the preparation of bearing and embodiment 1 utilize carbon nanotube bundles (carbon nanotube ropes) to replace single made of carbon nanotubes device at this moment together.On the surface of insulating layer of substrate, form lower floor's carbon nanotube bundles array earlier, have a bundle carbon nanotube bundles between two insulated legs 5; Utilize the scan-probe technology that the upper strata carbon nano-tube bundle is positioned, form the array of upper strata carbon nano-tube bundle, any contact can not take place in two bundle carbon nano-tube bundles each other.The two ends of each bundle carbon pipe deposit the gold of one deck 80 nanometer thickness with sputtering method in bilevel carbon nano-tube bundle array then, form electrode 1 and electrode 2.At last device is encapsulated.
The operating state of each memory cell of the utility model memory is as follows: the electrode 1 and 2 at carbon nano-tube two ends all has+V in memory cell
0During voltage (as Fig. 4), they repel mutually, and spacing is big, and the resistance between two carbon nano-tube is very big up and down, and this moment, memory cell was in off status (as Fig. 2); Electrode 1 when carbon nano-tube two ends, upper strata has-V
0Voltage, and lower electrode 2 has+V
0During voltage (as Fig. 5), two carbon nano-tube attract each other, pitch smaller, and therefore the resistance between them also diminish, and the unit is in out state (as Fig. 3).Said process is exactly the process that this memory system data writes.Give this unit two voltage differences of carbon nano-tube (as Fig. 6) up and down by electrode 1 and electrode 2, just can determine the residing state of system, the process that data that Here it is are read according to the size of resistance.
Memory of the present utility model is compared with traditional memory, and is integrated more convenient.It utilizes the interaction force between carbon nano-tube and the bearing to realize, the upper strata carbon nano-tube is as being bonded on the bearing, and the carbon nano-tube of lower floor then is fixed on the table top, as shown in figure 11.Such characteristics have determined the independence of each unit, and each controlled memory cell can deposit the information of a bit in.In a such storage matrix, control a corresponding memory cell by the electrode of each row and column and realize read-write, if the voltage of electrode is suitable, the storage of a unit can be regarded as independently behavior, other memory cell can not be affected, though so each row or column has only a carbon nano-tube, the various piece of being cut apart by bearing but is independent of each other.Fig. 12 has provided the vertical view of device architecture, utilizes this system to demonstrate and how to store three triad codings.For example need to deposit 111 successively in, 000 and 101, the utility model utilizes following table to describe the voltage condition of each electrode, wherein open state and be " 1 " with two carbon nano-tube, off status is " 0 ", the electrode 2 of lower floor's carbon nano-tube is always positive voltage pulse, by applying the storage that different potential pulses is realized each unit for upper strata carbon nanotube electrode 1, any one controlled memory cell can be stored the data of a bit, for example, deposit 111 these triad codings in, can utilize memory cell 8, memory cell 9 and memory cell 10 these three memory cell realize that as shown in the table, the electrode 2 of lower floor's carbon nano-tube all applies voltage+V
0The electrode of upper strata carbon nano-tube then adds negative voltage respectively, according to top discussion can know this moment storage matrix in deposited 111 these codings in, if want to read this coding, then measure the resistance of each memory cell upper strata carbon nano-tube and lower floor's carbon nano-tube respectively, can determine the information of memory cell 8, memory cell 9 and memory cell 10 successively according to height, so just finished writing and reading of data, the behavior of each memory cell all is independently with respect to other memory cell in this process.000 and 101 write can be with reference to corresponding electrode voltage in the following table, and the lower floor's carbon nano-tube in the storage matrix is+V
0 Positive voltage pulse+the V that represents electrode respectively
0And negative voltage pulse-V
0 Three three binary coding is deposited in this storage matrix of 3 * 3 after the process on the process shown in the table, if read three above-mentioned data, then as shown in Figure 6, give the levels carbon nano-tube with voltage difference, measure the size of resistance, just can judge the data of respective memory unit, so just can determine the state of whole memory, above process has just realized writing and reading in of three triad codings.What realize in the last example is the read-write of triad coding, if will realize the storage of long numeric data, can realize by bigger memory cell matrix.
The utility model memory operate as normal has two primary conditions: (1) spacing and a seat material of two-layer carbon nano-tube up and down can guarantee that bistable state appears in system; (2) operating voltage that applies can guarantee that the storage switch process has invertibity, can not damage device architecture.
If each memory cell is of a size of 10nm * 10nm, the so integrated storage density of memory afterwards can reach every square centimeter 10
12Bit, obviously this random asccess memory based on carbon nano-tube has very high storage density.And bit of dynamic random access memory (DRAM) storage needs a transistor and an electric capacity, and its storage density is subject to the size of storage capacitance, and this is that operation principle by DRAM causes.And bit of static random access memory SRAM storage needs 4 to 6 transistors.Except having higher storage density, this random asccess memory based on carbon nano-tube has very low power consumption, and it does not need continuous refreshing as traditional DRAM, also need support a plurality of transistor work unlike SRAM; In addition, the heat dissipation capacity of sort memory is very low, and the raising of integrated level can not cause the heat radiation difficulty, compares with traditional memory to have remarkable advantages.Use the device of such low-power consumption can solve the energy crisis that the legacy memory development is faced.
If each memory cell is of a size of 10nm * 10nm, then the operating frequency of this memory can reach 100GHz, this shows, this operating frequency that has significantly improved memory based on the non-volatile random asccess memory of carbon nano-tube, and can improve operating frequency by the size that reduces memory cell, and can not cause the problem that power consumption and heat dissipation capacity are excessive, therefore have more advantage than traditional SRAM and DRAM.
The utility model also can utilize carbon nano-tube bundle (carbon nanotube ropes) to come fabricate devices, and utilize carbon nano-tube as the lead-in wire on each electrode, such line capacitance is very little, the RC time is also very little, therefore the device operating frequency after integrated is very high, in preparation process, to accurately determine the optimum span of each basic parameter, improve the memory property of device to greatest extent.
Claims (3)
1. non-volatile random asccess memory with carbon nano tube structure, comprise a silicon substrate, with one deck oxidation insulating layer is arranged at substrate, and two-layer up and down single-wall carbon nanotube array by one group of parallel placement, its upper strata single-wall carbon nanotube array is placed on the oxidation insulating layer of substrate, mutually vertical between the bilevel carbon nano-tube, and form electrode at the two ends plated metal of two-layer each root carbon nano-tube up and down; It is characterized in that: between per two lower floor's carbon nano-tube, be provided with one parallel-oriented, that make by the oxidation insulating layer on the substrate with the lower floor carbon nano-tube, do the insulated leg of support for n root or n bundle upper strata carbon nano-tube simultaneously, the two ends of the root carbon nano-tube in one group of parallel carbon nano-tube of lower floor are placed on the insulated leg.
2. by the described non-volatile random asccess memory with carbon nano tube structure of claim 1, it is characterized in that: described quantity of carbon nanotubes is the positive integer of n＞1.
3. by the described non-volatile random asccess memory with carbon nano tube structure of claim 1, it is characterized in that: described carbon nano-tube is a Single Walled Carbon Nanotube.
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| CN 02237210 CN2547007Y (en) | 2002-06-05 | 2002-06-05 | Non-volatile random storage with carbon nano-tube structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101267002B (en) * | 2007-03-14 | 2011-02-09 | 韩国科学技术院 | Non-volatile memory element and its fabrication method |
| CN109962069A (en) * | 2017-12-25 | 2019-07-02 | 南亚科技股份有限公司 | Memory component |
-
2002
- 2002-06-05 CN CN 02237210 patent/CN2547007Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101267002B (en) * | 2007-03-14 | 2011-02-09 | 韩国科学技术院 | Non-volatile memory element and its fabrication method |
| CN109962069A (en) * | 2017-12-25 | 2019-07-02 | 南亚科技股份有限公司 | Memory component |
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