CN2522937Y

CN2522937Y - Extending bus framework and its bridge

Info

Publication number: CN2522937Y
Application number: CN 01264318
Authority: CN
Inventors: 张乃舜
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2001-09-27
Filing date: 2001-09-27
Publication date: 2002-11-27
Anticipated expiration: 2011-09-27

Abstract

The utility model provides an extension bus structure and bridges of the extension bus structure; the extension bus structure consists of a first accelerated graphics port bus, a first bridge, a second accelerated graphics port bus and a first extension bus. Signals and data on the first accelerated graphics port bus and the first extension bus or the second accelerated graphics port bus are transformed mutually based on compatibility, so as to expand the first accelerated graphics port bus. Since a high speed large bandwidth accelerated graphics port bus is used for extending and expanding to obtain one or a plurality of extension buses, the utility model can free data from passing through a south bridge chip and can provide more expanding slots, so as to greatly improve the expansion flexibility of a computer system.

Description

Extend bus architecture and middle bridge thereof

Technical field

The utility model relates to AGP (Accelerated Graphics Port the is called for short AGP) bus in a kind of computer system, and particularly gets the framework of different types of extension bus relevant for a kind of accelerated graphics port bus is expanded.

Background technology

Drawing display card in the early stage computer system is on the system bus that is inserted in as pci bus and so on, because the frequency range of system bus is lower, and various output input peripheral devices all may use, so can't be in response to the computer utility of high speed and multimedia etc., so develop drawing display card at a high speed is inserted on the special-purpose accelerated graphics port bus, mostly has the figure OverDrive Processor ODP in the drawing display card of this kind high speed.

Fig. 1 is the system schematic of common a kind of personal computer.Please refer to Fig. 1, central processing unit 10 is couple to pci bus 14 via chipset (chip set) 12, chipset 12 comprises South Bridge chip 15 and north bridge chips 18 again, and South Bridge chip 15 is to link together by exclusive VLINK bus 17 to move with north bridge chips 18.14 of pci buss couple the peripheral unit 16 of a plurality of PCI compatibilities.Each peripheral unit 16 all can be sent and require signal (request REQ) require to use pci bus 14, and the moderator in the chipset 12 (arbiter) then can be sent approval signal, and (grant GNT) gives primary controller, agrees that it uses pci bus 14.The peripheral unit of obtaining pci bus 14 controls comes access system internal memory 11 through chipset 12.In addition, this system comes access figure OverDrive Processor ODP 13 by dedicated graphics acceleration port bus.

The framework of above-mentioned Fig. 1 needs at a high speed and the demand of the bus of big frequency range though can solve figure OverDrive Processor ODP 13.But arriving along with the high frequency epoch, various peripheral units 16 all send and collect at a high speed and mass data, and these peripheral units 16 must be through South Bridge chip 15, VLINK bus 17 and north bridge chips 18 ability access system internal memories 11, originally the processing energy of South Bridge chip 15 can't adapt to gradually, the restriction of especially special-purpose VLINK bus 17 just more need not want to have had bigger extendibility again.Therefore, researching and developing a kind of new extension bus architecture is necessary in fact.

Summary of the invention

The utility model provides a kind of bus architecture and bridge wherein of extending, it extends the accelerated graphics port bus that expands existing big frequency range, extend bus and get one or more, can avoid the data approach through South Bridge chip, and provide more expansion slot for system, and the expansion elasticity of computer system is heightened, especially can be applicable to the server environment of the various high-speed peripheral devices that need a greater number.

For achieving the above object, the utility model provides a kind of extension bus architecture, comprises at least: first accelerated graphics port bus, first bridge and first extend bus.First bridge is coupled to first accelerated graphics port bus and first simultaneously and extends bus, be used for signal and data that first accelerated graphics port bus and first extends on the bus are done the conversion mutually of compatible ground, use so that first accelerated graphics port bus is expanded, and get this first extension bus.In most application, the utility model can include second graph again and quicken port bus, it is coupled to first bridge equally, first bridge is done signal on first accelerated graphics port bus and the second graph acceleration port bus and data to change mutually and buffering compatiblely, can use so that computer system is still possessed accelerated graphics port bus.

Extension bus architecture according to the utility model preferred embodiment, more provide second and extend bus, above-mentioned first bridge is changed signal on first accelerated graphics port bus and the second extension bus and the compatible ground of data work mutually, can use so increase an extension bus again.These extend bus for example is pci bus.Among the embodiment of the present utility model, first bridge can be connected in series second bridge as itself again, uses second graph to quicken port bus so can expand again, extends bus or the 3rd accelerated graphics port bus and get the 3rd or the 4th.

A kind of bridge provided by the utility model is used for first accelerated graphics port bus is expanded and the extension bus of winning comprises at least: main graphic quickens port controller, first and extends bus controller and flow controller.The main graphic that is coupled to first accelerated graphics port bus quickens port controller, is used for receiving compatiblely or transmit data and signal on first accelerated graphics port bus.Be coupled to first and extend the first extension bus controller of bus, be used for receiving compatiblely or transmitting first data and the signal that extends on the bus.Flow controller then is coupled to main graphic simultaneously and quickens the port controller and the first extension bus controller, is used to arbitrate and control the data of these controllers and the flow direction of signal.In most application, bridge of the present utility model gets second graph with the expansion of first accelerated graphics port bus more again and quickens port bus, extend figure acceleration port controller so have more in the bridge, it is coupled to second graph and quickens port bus and flow controller, is used for receiving compatiblely or transmit second graph and quickens data and signal on the port bus.And the data of all these controllers that are connected to itself and the flow direction of signal are arbitrated and controlled to above-mentioned flow controller.

The utility model is owing to extend the accelerated graphics port bus that expands big frequency range, it is directly to be coupled to north bridge chips, can avoid the data approach through South Bridge chip and VLINK bus, thus can not influence existing pci bus, and can provide computer system more expansion slot.

Description of drawings

Fig. 1 is the system schematic of common a kind of personal computer;

Fig. 2 is a kind of system schematic of extending bus architecture according to the utility model preferred embodiment, and it is for expanding the AGP bus;

Fig. 3 is the block diagram according to the bridge of the utility model preferred embodiment.

10: central processing unit

11: Installed System Memory

12: chipset

13: the figure OverDrive Processor ODP

The 14:PCI bus

15: South Bridge chip

16: peripheral unit

The 17:VLINK bus

18: north bridge chips

200: control chip group

220:AGP bus I

225:AGP bus II

230: bridge I

235:AGP bus III

240:PCI bus I

245:PCI bus II

250: bridge II

255:PCI bus III

260,270,280: peripheral unit

265:PCI bus IV

310: main graphic quickens port controller

320: flow controller

330: extend figure and quicken port controller

340,350: extend bus controller

Embodiment

Fig. 2 please refer to Fig. 2 for a kind of system schematic that expands the extension bus architecture of AGP bus according to the utility model preferred embodiment.The extension bus architecture that the utility model provides comprises at least: AGP bus I 220, bridge I 230 and first extend bus.The first extension bus is pci bus II 245 in this preferred embodiment.In this preferred embodiment, more comprise: AGP bus II 225 and second extends bus, and for example pci bus III 255.

Bridge I 230 is coupled to AGP bus I 220 and pci bus II 245 simultaneously.Its with signal on the AGP bus I 220 and data compatibility be transformed on the pci bus II 245; In like manner, its with signal on the pci bus II 245 and data compatibility be transformed on the AGP bus I 220.Therefore, AGP bus I 220 can be expanded and use, and get pci bus II 245.So the peripheral unit 260,270 and 280 that is inserted on the pci bus II 245 all can come access system internal memory 11 through bridge I 230, AGP bus I 220 and control chip group 200; And CPU (central processing unit) 10 can be controlled these peripheral units 260,270 and 280 through control chip group 200, AGP bus I 220, bridge I 230 and pci bus II 245.

The bridge I 230 of present embodiment is coupled to AGP bus II 225 and pci bus III 255 again.Bridge I 230 does compatible ground conversion and buffering mutually with AGP bus I 220 with signal and data on the AGP bus II 225, can use so that computer system is still possessed accelerated graphics port bus.In the same manner, bridge I 230 changes signal on AGP bus I 220 and the pci bus III 255 and the compatible ground of data work mutually, can use so increase an extension bus again.

Those of ordinary skills can know easily, and the extension bus example that present embodiment is given an example all is a pci bus, certainly the also bus of other kind.Among the utility model embodiment, bridge I 230 can be connected in series the bridge II 250 as itself again, uses AGP bus II 225 so can expand again, extends bus and get the 3rd or the 4th, for example be pci bus IV 265 etc., or the 3rd accelerated graphics port bus-AGP bus III 235.

Fig. 3 is the block diagram according to the bridge of the utility model preferred embodiment.The bridge I 230 that is provided among the embodiment, be mainly used in AGP bus I 220 expanded and pci bus II 245, it comprises at least: main graphic quickens port controller 310, extends bus controller 340 and flow controller 320.Main graphic quickens port controller 310 and is coupled to AGP bus I 220, and it receives compatiblely or transmit data and signal on the AGP bus I 220.Extend bus controller 340 and be coupled to pci bus II 245, it receives compatiblely or transmits data and signal on the pci bus II 245.And flow controller 320 is coupled to main graphic acceleration port controller 310 and extends bus controller 340, and its function is in arbitration and controls the data of these controllers 310,340 and the flow direction of signal.

In the utility model preferred embodiment, have more among the bridge I 230 and extend figure acceleration port controller 330 and second extension bus controller 350.Extend figure acceleration port controller 330 and be coupled to AGP bus II 225 and flow controller 320, this extension figure acceleration port controller 330 receives compatiblely or transmits data and the signal on the AGP bus II 225.Extend bus controller 350 and be coupled to pci bus III 255 and flow controller 320, this extension bus controller 350 receives compatiblely or transmits data and the signal on the pci bus III 255.And the data of all these controllers that are connected to itself and the flow direction of signal are arbitrated and controlled to above-mentioned flow controller 320.

Because the AGP bus is a bus that point-to-point form is used basically, the clock pulse frequency height of its use has higher frequency range, and proves a reliable and stable bus through use on the spot.Therefore, the utility model provides a kind of bus architecture and bridge wherein of extending, it extends and expands the AGP bus, extend bus and get one or more, further provide system more expansion slot, and the expansion elasticity of computer system is heightened, especially can be applicable to the server environment of the various high-speed peripheral devices that need a greater number.

Claims

1, a kind of extension bus architecture is characterized in that, this framework comprises:

One first accelerated graphics port bus;

One first extends bus, is used for expanding this first accelerated graphics port bus of use; And

One first bridge is coupled to this first accelerated graphics port bus and this first extension bus, and this first accelerated graphics port bus and this first signal and data of extending on the bus are done the mutual conversion in compatible ground.

2, extension bus architecture as claimed in claim 1 is characterized in that, this first bridge comprises:

One main graphic quickens port controller, is coupled to this first accelerated graphics port bus, receives compatiblely or transmit data and signal on this first accelerated graphics port bus;

One first extends bus controller, is coupled to this first extension bus, receives compatiblely or transmit this first data and signal that extends on bus; And

One flow controller is coupled to this main graphic and quickens port controller and this first extension bus controller, arbitrates and control the data of those controllers and the flow direction of signal.

3, extension bus architecture as claimed in claim 1 is characterized in that, this framework more comprises:

One second graph quickens port bus, is coupled to this first bridge, is used for expanding this first accelerated graphics port bus of use;

This first bridge is done signal on this first accelerated graphics port bus and this second graph acceleration port bus and data to change mutually and buffering compatiblely.

4, extension bus architecture as claimed in claim 3 is characterized in that, this first bridge comprises:

One first extends bus controller, is coupled to this first extension bus, receives compatiblely or transmit this first data and signal that extends on bus;

One extends figure quickens port controller, is coupled to this second graph and quickens port bus, receives compatiblely or transmit data and signal on this second graph acceleration port bus; And

One flow controller is coupled to this main graphic and quickens port controller, this extension figure acceleration port controller and this first extension bus controller, arbitrates and control the data of those controllers and the flow direction of signal.

5, extension bus architecture as claimed in claim 3 is characterized in that, more comprises:

One second extends bus, is used for expanding using this second graph to quicken port bus; And

One second bridge is coupled to this second graph and quickens port bus and this second extension bus, and this second graph is quickened port bus and this second signal and conversion mutually compatiblely of data do of extending on the bus.

6, extension bus architecture as claimed in claim 1 is characterized in that, more comprises:

One second extends bus, is coupled to this first bridge, is used for expanding this first accelerated graphics port bus of use;

This first bridge is done the conversion mutually of compatible ground with this first accelerated graphics port bus and this second signal and data of extending on the bus.

7, extension bus architecture as claimed in claim 6 is characterized in that, this first bridge comprises:

One second extends bus controller, is coupled to this second extension bus, receives compatiblely or transmit this second data and signal that extends on bus; And

One flow controller is coupled to this main graphic and quickens port controller, this first extension bus controller and the second extension bus controller, arbitrates and control the data of those controllers and the flow direction of signal.

8, extension bus architecture as claimed in claim 1 is characterized in that, more comprises a control chip group, and it is coupled to this first accelerated graphics port bus.

9, extension bus architecture as claimed in claim 1 is characterized in that, more comprises a peripheral unit, and it is coupled to this first extension bus.

10, a kind of bridge is used for expanding one first accelerated graphics port bus to such an extent that one first extend bus, it is characterized in that this bridge comprises:

11, bridge as claimed in claim 10 is characterized in that, it expands this first accelerated graphics port bus to such an extent that a second graph quickens port bus more again, and this bridge more comprises:

One extends figure quickens port controller, is coupled to this second graph and quickens port bus and this flow controller, receives compatiblely or transmit data and signal on this second graph acceleration port bus;

The arbitration of this flow controller is also controlled the data of those controllers of all connections and the flow direction of signal.

12, bridge as claimed in claim 10 is characterized in that, this first accelerated graphics port bus is expanded to such an extent that one second extend bus more again, and this bridge more comprises:

One second extends bus controller, is coupled to this second extension bus and this flow controller, receives compatiblely or transmit this second data and signal that extends on bus;