CN100345136C - System for making 64 bit processor compatibe with 32 bit bridge chip and conversion device - Google Patents
System for making 64 bit processor compatibe with 32 bit bridge chip and conversion device Download PDFInfo
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Abstract
The present invention discloses a system for making a 64 bit processor compatible with a 32 bit bridge chip, and a converting device. The system comprises a 64 bit processor, a 32 bit bridge chip and a converting device, wherein the converting device comprises a 64 bit processor system interface module, a 64-32 bit system bus command converting circuit, a 64-32 bit system bus address / data transformation circuit, a 32-64 bit system bus data transformation circuit and a 32 bit processor system interface module. The system can also comprises an off-chip CACHE, and correspondingly, the converting device comprises an off-chip CACHE control module connected with the CACHE. After the converting device of the present invention is used, when a 64 bit MIPS processor works under the 32 bit mode, the 64 bit processor can be compatible with the 32 bit bridge chip. Thereby, the cost is reduced. The converting device of the present invention also provides support of the processor off-chip CACHE for the 32 bit MIPS bridge chip, and the performance of the 64 bit MIPS processor is fully displayed.
Description
Technical field
The present invention relates to computer realm, more particularly, relate to a kind of system and conversion equipment that makes compatible 32 bridging chips of 64 MIPS processors.
Background technology
In general, 64 MIPS processors have higher performance than 32 MIPS processors, and 64 systems of MIPS can backward compatible 32 system softwares.When 64 MIPS processors worked in for 32 bit pattern following time, there is no need to use 64 bridging chips fully, because relative 32 bridging chips of the price of 64 bridging chips will exceed a lot.But, because the data width of 64 MIPS processor system bus read-write operations is 64, and the data width of 32 MIPS bridging chip system bus read-write operations is 32, causes 64 MIPS processors can not run in the system environments that is made up by 32 MIPS system bridges chips like this.In addition, 64 MIPS bridging chips provide the processor piece support of CACHE outward, and existing 32 MIPS bridging chips do not provide the support to the outer CACHE of processor piece, can largely reduce the performance of 64 MIPS processor performances like this.
Summary of the invention
One of purpose of the present invention is to provide a kind of system that makes compatible 32 bridging chips of 64 bit processors, in this system, by a conversion equipment make 64 bit processors can with 32 bridging chip collaborative works; Two of purpose of the present invention is to provide a kind of conversion equipment that makes compatible 32 bridging chips of 64 bit processors, this device is connected between 64 MIPS processors and 32 bridging chips, so that order, address and/or data that 64 MIPS processors or 32 bridging chips are sent are changed; A further object of the present invention is to provide a kind of conversion equipment that makes compatible 32 bridging chips of 64 bit processors, and this conversion equipment provides the processor piece support of CACHE outward for 32 MIPS bridging chips.
To achieve these goals, the invention provides a kind of system that makes compatible 32 bridging chips of 64 bit processors, comprise 64 bit processors, 32 bridging chips and a conversion equipment, this conversion equipment is converted to 32 system commands with 64 system commands, and this conversion equipment also carries out the mutual conversion of the address/data of the address/data of 64 systems and 32 systems; Described conversion equipment comprises 64 bit processor system interface modules, is used to finish described conversion equipment and is connected with bus between the described processor; Described conversion equipment also comprises 32 bit processor system interface modules, is used to finish described device and is connected with bus between the bridging chip.
Described conversion equipment also comprises: 64-32 position system bus command conversion circuit, be used for 64 system commands that processor sends are converted to 32 system commands, and the order after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications; 64-32 position system bus address/data converting circuit, be used for 64 the address/data that processor sends is converted to 32 address/data form, and the address/data after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications; 32-64 position system bus data converting circuit is used for 32 bit data that bridging chip sends are converted to 64 bit data, so that send to 64 bit processor chips; 32 bit processor system interface modules are used to finish described device and are connected with bus between the bridging chip.
Described 32-64 position system bus data converting circuit has one " individual character---double word state flag bit ", is used to control the double word that two 32 bit data are converted to one 64 bit data and splices.32-64 position system bus data converting circuit also has one first judging unit, and whether last the double word splicing that is used for the decision block read operation is finished.
Described 64-32 position system bus address/data converting circuit has one second judging unit, and whether last individual character that is used for the decision block write operation is write and finished.
For the support of CACHE outside 32 MIPS bridging chips provide processor piece, described system also comprises the outer CACHE of a slice, and described conversion equipment also comprises the outer CACHE control module of a sheet that is connected with described CACHE.
The present invention also provides a kind of conversion equipment that makes compatible 32 bridging chips of 64 bit processors, is connected between 64 bit processor processors and 32 bridging chips, and this conversion equipment comprises:
64 bit processor system interface modules are used to finish described conversion equipment and are connected with bus between the processor chips;
64-32 position system bus command conversion circuit is used for 64 system commands that processor sends are converted to 32 system commands, and the order after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications;
64-32 position system bus address/data converting circuit, be used for 64 the address/data that processor sends is converted to 32 address/data form, and the address/data after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications;
32-64 position system bus data converting circuit is used for 32 bit data that bridging chip sends are converted to 64 bit data, so that send to 64 bit processor chips;
32 bit processor system interface modules are used to finish described conversion equipment and are connected with bus between the bridging chip.
Described 32-64 position system bus data converting circuit has one " individual character---double word state flag bit ", is used to control the double word that two 32 bit data are converted to one 64 bit data and splices.Described 32-64 position system bus data converting circuit also has one first judging unit, and whether last the double word splicing that is used for the decision block read operation is finished.
Described 64-32 position system bus address/data converting circuit has one second judging unit, and whether last individual character that is used for the decision block write operation is write and finished.
Behind the conversion equipment of the present invention that adopts,, can make 32 bridging chips of 64 bit processors compatibility, thereby reduce cost when 64 MIPS processors worked in for 32 bit pattern time following.Conversion equipment of the present invention also provides the processor piece support of CACHE outward for 32 MIPS bridging chips, has given full play to 64 MIPS performance of processors.
Description of drawings
Fig. 1 is the composition synoptic diagram that makes the system of compatible 32 bridging chips of 64 bit processors provided by the invention;
Fig. 2 is the composition synoptic diagram of conversion equipment of the present invention;
Fig. 3 is the form of 64 and 32 system read-write orders;
Fig. 4 is the read operation conversion process process flow diagram that conversion equipment of the present invention sends processor;
Fig. 5 is the write operation conversion process process flow diagram that conversion equipment of the present invention sends processor;
Fig. 6 is the process flow diagram of the outer cache operation of conversion equipment supporting pieces of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
As shown in Figure 1, conversion equipment of the present invention is positioned between 64 MIPS processor (CPU) chips and 32 bridging chips.This conversion equipment is connected by system bus with processor chips, generally is to link to each other with 9 order of the bit buses by 64 bit address/data bus.This conversion equipment is connected by system bus with bridging chip, generally is to link to each other with 9 order of the bit buses by 32 bit address/data bus.
It is 32 system command forms by 64 system command format conversion that conversion equipment of the present invention is realized the system bus order between processor and the bridging chip, realizes that simultaneously system bus address/data are by the mutual conversion between 64 bit formats and 32 bit formats.In order to realize this conversion, conversion equipment of the present invention comprises as shown in Figure 2:
64 bit processor system interface modules are used to finish this device and are connected with bus between the processor chips, mainly realize the mutual and caching function of 64 bit address between this device and the processor chips/data bus and 9 order of the bit buses.64 bit processor system interface modules are received the order that reads or writes that processor sends from the order bus interface, and this order is sent to 64-32 position system bus command conversion circuit.When processor send be write order the time, 64 bit processor system interface modules also will receive the address and the data of write operation from 64 bit address/data bus, then with the write data buffer memory, and the address are sent to 64-32 position system bus address/data converting circuit;
64-32 position system bus command conversion circuit is used for 64 system commands that processor sends are converted to 32 system commands, and the order after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications;
64-32 position system bus address/data converting circuit, be used for 64 the address/data that processor sends is converted to 32 address/data form, and the address/data after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications;
32-64 position system bus data converting circuit is used for 32 bit data that bridging chip sends are converted to 64 bit data, so that send to 64 bit processor chips; When processor send be read command the time, the bridging chip end is sent to 32-64 position system bus data converting circuit with the data that read, 32 bit data that will be read by 32-64 position system bus data converting circuit are converted to one 64 bit data, and send to processor by 64 bit processor system interface modules through 64 bit address/data bus;
32 bit processor system interface modules are used to finish this device and are connected with bus between the bridging chip, mainly realize the mutual and caching function of 32 bit address between this device and the bridging chip/data bus and 9 order of the bit buses.
From above narration as can be known, system bus address/data need be changed between 64 system formats and 32 system formats at conversion equipment of the present invention.In general, the address/data width in 64 systems is 64, and the address/data width in 32 systems is 32.When 64 MIPS processors worked in for 32 bit pattern following time, high 32 of the address that it reads and writes data is zero, therefore 64-32 position system bus address/data converting circuit with system bus address when 64 system formats are transformed into 32 system formats, only need low 32 of 64 system addresss of foundation to get final product, concrete operations will describe in detail hereinafter.64-32 position system bus address/data converting circuit only needs data with 64 system buss be divided into high 32 and low 32 two parts and gets final product with 64 system bus data-switching to 32 system bus data the time.32-64 position system bus data converting circuit is with 32 system bus data-switching to 64 system bus data the time, and only needing two 32 bit data are stitched together gets final product.64-32 position system bus address/data converting circuit and the 32-64 position system bus data converting circuit of realizing above-mentioned functions are easy to design for a person skilled in the art.
Conversion equipment of the present invention also needs the system bus order is transformed into 32 system formats from 64 system formats.As shown in Figure 3,64 system bus orders and 32 system bus orders all are made up of 9 data positions.For 64 system bus orders, the size of its 0-2 bit representation byte number, 8 kinds of situations are represented in 8 kinds of combinations of 3 data bit respectively, 000 expression byte, 001 expression double byte, 010 expression, three bytes, 011 expression word, 100 expressions, five bytes, 101 expressions, six bytes, 110 expressions, seven bytes, 111 expression double words.Its 3-4 bit representation piece/non-selection, 00 and 01 expression is invalid, 10 expression pieces, non-of 11 expressions, when being piece, which kind of situation no matter the 0-2 position be, and is all inoperative, has only when for non-, the size of byte number is just represented in the 0-2 position.Its 5-7 position is used to distinguish read-write operation, is read operation when the 5-7 position is 000, be 010 o'clock be write operation.Its No. 8 positions keep, and unification is 0.As shown in Figure 3, for 32 system bus orders, the size of its 0-1 bit representation byte number, four kinds of situations of four kinds of combination expressions of 2 data bit, 00 expression byte, 01 expression double byte, 10 expressions, three bytes, 11 expression words.Its 2 reservations, unification is 0.Its 3-4 bit representation piece/non-selection, 00 and 01 expression is invalid, 10 expression pieces, non-of 11 expressions, when being piece, which kind of situation no matter the 0-1 position be, and is all inoperative, has only when for non-, the size of byte number is just represented in the 0-1 position.Its 5-7 position is used to distinguish read-write operation, is read operation when the 5-7 position is 000, be 010 o'clock be write operation.Its No. 8 positions keep, and unification is 0.In the present invention, 64 system commands that 64-32 position system bus command conversion circuit sends processor chips are 32 system commands according to the format conversion of Fig. 3, realize that the 64-32 position system bus command conversion circuit of this function is easy to design for a person skilled in the art.
Fig. 4 and Fig. 5 show respectively and adopt conversion equipment of the present invention to carry out the detailed process of read-write operation.In conjunction with Fig. 4 and Fig. 5, and the narration by hereinafter, will being readily appreciated that of conversion equipment various piece of the present invention.Generally speaking, 64 supported read-write operations of MIPS processor have piece, double word, seven bytes, six bytes, five bytes, word, three bytes, half-word and nine kinds of patterns of byte, need 4 system clock cycles to carry out data when block operations and transmit.And the read-write operation that 32 MIPS processor bridging chips can be supported has only piece, word, three bytes, half-word and five kinds of patterns of byte, and needs 8 clock period to transmit data for block operations.In order to know among the present invention conversion, need to understand the form of 64 system bus orders and 32 system bus orders to read write command.
Fig. 4 shows the treatment scheme that read operation that conversion equipment of the present invention sends processor is changed.
As shown in Figure 4, if the read operation request right and wrong piece read operation that processor sends, and when this request is double word, seven bytes, six bytes or five byte read requests, conversion equipment of the present invention is split as twice read operation with this read operation, twice read operation can be read the data of two words, thereby double word, seven bytes, six bytes or five byte read request desired datas are read out, and this twice read operation for the read operation of low 32 correspondences, once is high 32 pairing read operations once.Correspondingly, in the present invention, 64 system's read commands that 64-32 position system bus command conversion circuit sends processor are converted to two 32 system's read commands, and one of them read command is used to read low 32 bit data, and another read command is used to read high 32 bit data; And it is two 32 bit address that 64-32 of the present invention position system bus address/data converting circuit will be read address translation, and one of them address is pointed to and will be read low 32 bit data, and high 32 bit data that will read are pointed in another address.According to order and the address after the conversion, from bridging chip, read out low 32 bit data and high 32 bit data respectively, and 32 bit data that will return are mapped on 64 bit data bus.Because the data that the bridging chip end returns are 32, and the address/data bus of processor end is 64, the data splicing that the 32-64 position system bus data converting circuit among the present invention will read at twice is for to send to the processor end one 64 bit data.When carrying out data splicing, can control by one " individual character---double word state flag bit " is set at 32-64 position system bus data converting circuit, when the data of twice read operation of double word, seven bytes, six bytes or five byte read request correspondences are returned, this state position is 1, and all the other situations are 0.When " individual character---double word state flag bit " is 1, sign has twice 32 read operation data to return, the data that this moment, the 32-64 position system bus data converting circuit in apparatus of the present invention just returned twice read operation are stitched together and send corresponding read operation return data to processor system bus, then " individual character---double word state flag bit " clear 0.If " individual character---double word state flag bit " is 0, wait for that then the splicing processing of not doing data becomes till 1 until zone bit.
In one embodiment, what 64 MIPS processors sent is five byte read commands, and wherein reading the address is 0x00000000110a5d22, and read command is 000011100.As previously mentioned, conversion equipment of the present invention is with this read command and read the address and be split as two read commands and read the address, sends read request to bridging chip at twice.In this embodiment, be 2 owing to read the address lowest order, expression begins to read from byte 2, so be split as low 32 a double byte read command and three high 32 byte read commands.Be low 32 read operations for the first time, it is 0x110a5d22 that the 64-32 position system bus address/data converting circuit of conversion equipment of the present invention will be read address translation, and it is 000011001 that read command is converted to 32 system's double byte read commands; Be high 32 read operations for the second time, reading address translation is 0x110a5d24, and it is 000011010 that read command is converted to the three byte read commands of 32 systems.Bridging chip returns two 32 bit data of twice read operation, by 64-32 position system bus address/data converting circuit two 32 bit data is spliced into 64 bit data and returns.In system initialization, the value of " individual character---double word state flag bit " is 0, receives this mark position 1 after two 32 bit data.When the value of " individual character---double word state flag bit " was 1, conversion equipment of the present invention returned 64 bit data and with " individual character---double word state flag bit " clear 0 to processor.
Return Fig. 4, if processor sends read request is the read operation that is less than or equal to a word, the processing of conversion equipment of the present invention is simple relatively.After sending the read request that is less than or equal to a word when processor, 64-32 position system bus command conversion circuit is converted to read command the form of 32 system's correspondences earlier.Be readily appreciated that from Fig. 3 in fact, for the read operation that is less than or equal to a word, 32 system's read commands after the conversion are consistent with changing 64 preceding system's read commands in form.64-32 position system bus address/data converting circuit is the form of 64 system's 32 system's correspondences in read operation address translation position, then to send a read operation to the bridging chip circuit, when bridging chip had data, 32 bit data that the 32-64 position system bus data converting circuit in the conversion equipment returns bridging chip converted 64 bit data to and send processor to.The data-switching here can be mapped on the 64 bit processor buses by 32 bit data that 32-64 position system bus data converting circuit will read, 32 bit data that are about to read are sent on low 32 or high 32 of 64 buses, and correspondingly with high 32 or low 32 position zero.
In one embodiment, what 64 MIPS processors sent is three byte read commands, and wherein reading the address is 0x00000000110a5d20, and read command is 000011010.Conversion equipment of the present invention the read operation address translation of 64 system's correspondences be 32 system's correspondences read address 0x110a5d20,32 three byte read commands are all 000011010 mutually with 64 three byte read commands, send read request to bridging chip.Bridging chip returns 32 bit data, by 32-64 position system bus data converting circuit 32 bit data is placed on 64 low 32, and high 32 bit positions directly add 0.
Refer again to Fig. 4, if the read operation that processor sends is the piece read operation, the 64-32 position system bus command conversion circuit of apparatus of the present invention is converted to read command the form of 32 system's correspondences earlier, the 64-32 position system bus address/data converting circuit of apparatus of the present invention is the read operation address translation form of 32 system's correspondences, sends read operation to bridging chip then.Be readily appreciated that from Fig. 3 in fact, for the piece read operation, 32 system block read commands after the conversion are consistent with changing 64 preceding system block read commands in form.Bridging chip response read operation is returned the data that read to 32 bit processor system interface circuit, and realizes the conversion of corresponding 32-64 position in the system bus data converting circuit of the 32-64 position of apparatus of the present invention.The conversion of this 32-64 position also can aforesaid by being provided with " individual character---double word zone bit " be controlled, and when the data of twice read operation of read request correspondence were all returned, this state position was 1, otherwise is 0.When " individual character---double word zone bit " when being 1, sign has twice 32 read operation data to return, the data that the 32-64 position system bus data converting circuit of apparatus of the present invention returns twice read operation are stitched together and send corresponding read operation return data to processor system bus, and with " individual character---double word state flag bit " clear 0.Judge simultaneously whether current return data is last splicing data of processor piece read operation correspondence, if not, continue to receive the data that bridging chip returns, if the current block read operation is finished.
In one embodiment, what 64 MIPS processors sent is the piece read command, and wherein reading the address is 0x00000000110d5dc0, and read command is 000010001.Conversion equipment of the present invention the read operation address translation of 64 system's correspondences be 32 system's correspondences read address 0x110d5dc0,32 system block read operation orders are all 000010001 mutually with 64 piece read operation orders, send read request to bridging chip.Bridging chip returns 32 bit data at every turn, and 32-64 position system bus data converting circuit is combined into 64 with 32 bit data and returns.In system initialization, the value of " individual character---double word state flag bit " is 0, receives this mark position 1 after two 32 bit data.When the value of " individual character---double word state flag bit " was 1, built-up circuit returned 64 bit data and with " individual character---double word state flag bit " clear 0 to processor.Judge simultaneously whether current return data is last data of processor piece read operation correspondence, if not, continue to receive the data that bridging chip returns, if the current block read operation is finished.
Fig. 5 shows the treatment scheme that write operation requests that conversion equipment of the present invention sends processor is changed.
As shown in Figure 5, if the write request that processor sends operation, and when this write request is double word, seven bytes, six bytes or five byte write requests, conversion equipment of the present invention is split as write operation twice with this write operation, twice write operation can be write the data of two words, thereby double word, seven bytes, six bytes or five byte write request desired datas are write, and this twice write operation for the write operation of low 32 correspondences, once is high 32 pairing write operations once.Because the bridging chip end is 32 bit address/data bus, once can only receive word or less than the write operation of a word, so 64 write data buffer memorys that 64 system bus interface circuits in apparatus of the present invention need be sent processor get off, as through fractionation the second time write operation correspondence data.After finishing the write data buffer memory that the processor end sends, correspondingly, in the present invention, 64 system's write orders that 64-32 position system bus command conversion circuit sends processor are converted to two 32 system's write orders, one of them write order is used to write low 32 bit data, and another write order is used to write high 32 bit data; And 64-32 of the present invention position system bus address/data converting circuit is converted to two 32 bit address with write address, the address of low 32 bit data that one of them sensing will write, the address of high 32 bit data that another sensing will write.According to write order and the write address after the conversion, in bridging chip, write low 32 bit data and high 32 bit data at twice, promptly respectively low 32 and high 32 of 64 bit data in the buffer memory are mapped on 32 bit data bus.
In one embodiment, what 64 MIPS processors sent is five byte write orders, and write address is 0x00000000110d5dc3, and write order is 001011100, write data 0x7f6e5d4c3b2a1800.64 write datas that conversion equipment of the present invention sends processor are in 64 bit processor system interface modules under the buffer memory.As previously mentioned, conversion equipment of the present invention is split as two write orders and write address with this write order and write address, sends write request to bridging chip at twice.In this embodiment, because the address lowest order is 3, expression begins to write from byte 3, writes with high 32 word and writes so be split as a byte of low 32.Be low 32 write operations for the first time, change-over circuit is converted to 0x110d5dc3 with write address, and the byte write order that write order is converted to 32 systems is 001011000, and write data is converted to the low 32 bit data 0x3b2a1800 of former data; Be high 32 write operation for the second time, write address is converted to 0x110d5dc4, and it is 001011011 that write order is converted to that 32 bit format words write, and write data is converted to the high 32 bit data 0x7f6e5d4c of former data.
Return Fig. 5, if processor sends is the write operation order that is less than or equal to a word, the 64-32 position system bus command conversion circuit of conversion equipment is converted to this write order the form of 32 system's correspondences earlier.Be readily appreciated that from Fig. 3 in fact, for the write operation that is less than or equal to a word, 32 system's write orders after the conversion are consistent with changing 64 preceding system's write orders in form.64-32 position system bus address/data converting circuit becomes the write operation address translation form of 32 system's correspondences, change-over circuit judges it is that high 32 data or low 32 bit data are write in the bridging chip by address decoding, select 64 according to judged result in corresponding 32 write datas send corresponding write operation to bridging chip.
In one embodiment, what 64 MIPS processors sent is three byte write orders, and write address is 0x00000000110d5dc5, and write order is 001011010, write data 0x7f6e5d4c3b2a1800.64 write datas that conversion equipment of the present invention sends processor are in 64 bit processor system interface modules under the buffer memory.In this embodiment, because the address lowest order is 5, expression begins to write from byte 5, so these 64 three byte command can be exchanged into one three high 32 bytes is write.Correspondingly, 32 systems, the three byte write orders after the conversion are 001011010, and the write address after the conversion is 0x110d5dc5, and write data is converted to the high 32 bit data 0x7f6e5d4c of former data.
Return Fig. 5 again, the piece write operation that sends for processor, because the length of a CACHE piece is 256, data width at the processor end is 64, finish a write operation and need continuous 4 write datas, and the bridging chip system bus width is 32, finish a write operation and need continuous 8 write datas, so 4 write datas and buffer memory that conversion equipment of the present invention needs that receiving processor sends get off, and whether write to be ready to judge when send 32 continuous write datas 8 times according to bridging chip then.Processor sends after the piece write operation requests, and the 64-32 position system bus command conversion circuit of conversion equipment of the present invention is converted to the piece write order of 64 systems the form of 32 system's correspondences earlier.Be readily appreciated that from Fig. 3 in fact, for the piece write operation, 32 system block write orders after the conversion are consistent with changing 64 preceding system block write orders in form.64-32 position system bus address/data converting circuit becomes piece write operation address translation the form of 32 system's correspondences.After bridging chip is write and is ready to, 64-32 position system bus address/data converting circuit splits into twice write operation in 32 bridging chips with a write operation in 64 bit processors, realize low 32 and high 32 writing respectively, this fractionation is described in detail in preamble.In the process that realizes the piece write operation, judge by 64-32 position system bus address/data converting circuit that last individual character is write and whether finish, if not, then continue to write, all data in piece all write till the bridging chip, if then the current block write operation stops.
As depicted in figs. 1 and 2, support for CACHE outside 32 MIPS bridging chips provide processor piece, conversion equipment of the present invention preferably also link to each other (Fig. 1) with the outer CACHE of a sheet, correspondingly, this conversion equipment preferably also comprises the outer CACHE control module (Fig. 2) of a sheet, finishes the support function to the outer CACHE of sheet.As shown in Figure 1, the outer CACHE of this sheet is connected with 64 bit address/data bus, cpu chip by read-write control signal to control the read-write of CACHE outward of this sheet.The outer CACHE of this sheet is connected by signal wire with conversion equipment of the present invention (being the outer CACHE control module of sheet in the conversion equipment specifically), be used for the hit id signal of the outer CACHE of transmission sheet to the conversion equipment transmission, and the conversion equipment filling command signal that CACHE sends outside sheet.
As shown in Figure 1, when processor sent read-write requests to built-up circuit, also CACHE sent read-write control signal outside sheet.Because the read-write control of the outer CACHE of sheet is directly by the processor support, so built-up circuit need not the processor read-write operation that CACHE sends outside sheet is handled, only processor to sheet outside the CACHE read operation of sending when not hitting, built-up circuit CACHE outside sheet sends and fills order.As shown in Figure 6, when conversion equipment of the present invention receive processor send the piece read request after, outer CACHE hits id signal by the sampling processor sheet, judge whether that the outer CACHE of sheet hits, if hit, data corresponding to read operation among the outer CACHE of sheet directly turn back to processor by address/data bus, and conversion equipment of the present invention does not then send read request to bridging chip, and begins to accept next processor request; Outer CACHE does not hit as chankings, conversion equipment of the present invention then sends corresponding read request to bridging chip, and when data are returned outside sheet CACHE send to fill command signal, the outer CACHE of sheet reads the data of returning from address/data bus, finishes the filling of data.The piece write operation that sends for processor is because 64 processor end has been realized the write control circuit to the outer CACHE of sheet, so conversion equipment of the present invention does not deal with the write operation of the outer CACHE of sheet.
Claims (10)
1, a kind of system that makes compatible 32 bridging chips of 64 bit processors, comprise 64 bit processors, it is characterized in that, also comprise 32 bridging chips and a conversion equipment, this conversion equipment is converted to 32 system commands with 64 system commands, and this conversion equipment also carries out the mutual conversion of the address/data of the address/data of 64 systems and 32 systems; Described conversion equipment comprises 64 bit processor system interface modules, is used to finish described conversion equipment and is connected with bus between the described processor; Described conversion equipment also comprises 32 bit processor system interface modules, is used to finish described conversion equipment and is connected with bus between the bridging chip.
2, the system that makes compatible 32 bridging chips of 64 bit processors according to claim 1 is characterized in that described conversion equipment also comprises:
64-32 position system bus command conversion circuit is used for 64 system commands that processor sends are converted to 32 system commands, and the order after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications;
64-32 position system bus address/data converting circuit, be used for 64 the address/data that processor sends is converted to 32 address/data form, and the address/data after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications;
32-64 position system bus data converting circuit is used for 32 bit data that bridging chip sends are converted to 64 bit data, so that send to 64 bit processor chips.
3, the system that makes compatible 32 bridging chips of 64 bit processors according to claim 2, it is characterized in that, described 32-64 position system bus data converting circuit has one " individual character---double word state flag bit ", is used to control the double word that two 32 bit data are converted to one 64 bit data and splices.
4, the system that makes compatible 32 bridging chips of 64 bit processors according to claim 3, it is characterized in that, 32-64 position system bus data converting circuit also has one first judging unit, and whether last the double word splicing that is used for the decision block read operation is finished.
5, the system that makes compatible 32 bridging chips of 64 bit processors according to claim 2, it is characterized in that, described 64-32 position system bus address/data converting circuit has one second judging unit, and whether last individual character that is used for the decision block write operation is write and finished.
6, the system that makes compatible 32 bridging chips of 64 bit processors according to claim 2 is characterized in that, also comprises the outer CACHE of a slice, and described conversion equipment also comprises the outer CACHE control module of a sheet that is connected with described CACHE.
7, a kind of conversion equipment that makes compatible 32 bridging chips of 64 bit processors is connected between 64 bit processor processors and 32 bridging chips, it is characterized in that this conversion equipment comprises:
64 bit processor system interface modules are used to finish described conversion equipment and are connected with bus between the processor chips;
64-32 position system bus command conversion circuit is used for 64 system commands that processor sends are converted to 32 system commands, and the order after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications;
64-32 position system bus address/data converting circuit, be used for 64 the address/data that processor sends is converted to 32 address/data form, and the address/data after will changing sends to bridging chip by 32 bit processor system interface modules, so that 32 bridging chips identifications;
32-64 position system bus data converting circuit is used for 32 bit data that bridging chip sends are converted to 64 bit data, so that send to 64 bit processor chips;
32 bit processor system interface modules are used to finish described conversion equipment and are connected with bus between the bridging chip.
8, the conversion equipment that makes compatible 32 bridging chips of 64 bit processors according to claim 7, it is characterized in that, described 32-64 position system bus data converting circuit has one " individual character---double word state flag bit ", is used to control the double word that two 32 bit data are converted to one 64 bit data and splices.
9, the conversion equipment that makes compatible 32 bridging chips of 64 bit processors according to claim 8, it is characterized in that, 32-64 position system bus data converting circuit also has one first judging unit, and whether last the double word splicing that is used for the decision block read operation is finished.
10, the conversion equipment that makes compatible 32 bridging chips of 64 bit processors according to claim 7, it is characterized in that, described 64-32 position system bus address/data converting circuit has one second judging unit, and whether last individual character that is used for the decision block write operation is write and finished.
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| CNB2004100092847A CN100345136C (en) | 2004-06-30 | 2004-06-30 | System for making 64 bit processor compatibe with 32 bit bridge chip and conversion device |
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| CNB2004100092847A CN100345136C (en) | 2004-06-30 | 2004-06-30 | System for making 64 bit processor compatibe with 32 bit bridge chip and conversion device |
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| CN1716226A CN1716226A (en) | 2006-01-04 |
| CN100345136C true CN100345136C (en) | 2007-10-24 |
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| CN102098510B (en) * | 2010-11-25 | 2014-07-09 | 深圳市融创天下科技股份有限公司 | Methods and devices for decoding and coding audio/video data |
| CN105094870A (en) * | 2014-05-13 | 2015-11-25 | 中标软件有限公司 | Compatible method of 64-bit Linux operating system for 32-bit application software |
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| CN1716226A (en) | 2006-01-04 |
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