CN2498665Y - 24 point matrix display processing chip - Google Patents

Abstract

The utility model relates to a 24 dot matrix displaying and processing chip which is mainly used for finishing display control, clock control and peripheral control of a graphic terminal, wherein the display control comprises DRAM transparent refreshment, character library access, dot matrix display, attribute synthesis, etc. The peripheral control comprises the control of two XT keyboard interface control units and the control of parallel printing openings. The clock control comprises the control of a character clock, a dot frequency clock and a cursor flash frequency. A GW710 display terminal exploited by combining the chip with other chips has the characteristics of few chip number, low cost and strong function, and the specific requirements of departments, such as banks, tax affairs, etc., can be satisfied.

Description

24 dot matrix display process chips

Technical field:

The utility model relates to a kind of integrated circuit (IC) chip, is meant a kind of 24 dot matrix display process chips especially.

Technical background:

Along with fast development of computer technology, computing machine has been widely used in all trades and professions, because the characteristics of every profession and trade, often different industries is all different to the requirement of hardware, as the display terminal that is applied to departments such as bank, the tax has higher requirement to Chinese character demonstration, transparent refresh, display terminal in the past is the requirement of satisfying these industries, general employing polylith display control chip makes up and achieves the goal, but improved the cost of display terminal so on the one hand, also reduced security, the reliability of terminal on the other hand.

Summary of the invention:

The purpose of this utility model is to overcome the deficiency of prior art and a kind of integrated level height, powerful 24 dot matrix display process chips is provided.

For achieving the above object, the utility model comprises:

XT keyboard interface control module is used for the serial data from keyboard is converted to parallel data and exports to CPU;

Character library reference address unit, the character code that is used for visiting from the need of system's input converts the specific address of word-base chip to and outputs to word-base chip;

DRAM transparent refresh control module is used for CPU not disturbing under the normal situation about showing of screen, finishes the read and write access of contraposition video memory DRAM;

Show the synthetic control module of dot matrix converting attribute, 12 point data that are used for reading in from video memory in the character clock convert the point data of serial to, and then under the driving of a frequency, get a position, process display properties, cursor position and demonstration generate video output signals after enabling to synthesize;

Parallel print control unit, the IO chip selection signal that is used for CPU is sent carries out two-stage decode, respectively the address signal of output and line printing control mouth, parallel print data mouth and parallel print state mouth.

The utility model has been owing to adopted above-mentioned parts to constitute, and it has integrated level height, powerful characteristics.

Below in conjunction with accompanying drawing the utility model is described in further detail.

Description of drawings:

Accompanying drawing 1 is a structured flowchart of the present utility model.

Accompanying drawing 2 is pin arrangements figure of the present utility model.

Accompanying drawing 3 is a Keysheet module circuit diagram of the present utility model.

Accompanying drawing 4 is a clock module circuit diagram of the present utility model.

Accompanying drawing 5 is a display module circuit diagram of the present utility model.

Accompanying drawing 6 is a character library access modules circuit diagram of the present utility model.

Embodiment:

Referring to Fig. 1, the utility model comprises XT keyboard interface control module, character library reference address control module, shows the control of DRAM transparent refresh, shows the synthetic control of dot matrix converting attribute, LPTx ports control.Described XT keyboard interface control module will be from the serial data of keyboard, convert parallel data to and export to CPU, 9 of one frame keyboard datas, 1 start bit, 8 bit data positions, start bit is preceding, and high level is effective, and displacement output back receives look-at-me notice CPU as keyboard data data are taken away; Character library reference address control module, the character code that system will visit is input to this control module, code is converted to the specific address CGA[15..0 of visit word-base chip by this control module] output to word-base chip, this control module can be realized the visit to two kinds of character libraries, and when visit GB2312 character library, the code of character is made up of two 7 byte, BIT15 is used to deposit half information about Chinese character shows, half, the 1 expression right side half, 0 an expression left side, font address and code are changed with algorithm; During the big character library of visit GB13000GBK, the code of character is made up of two 8 byte, the linear corresponding relation of font address and code.Show DRAM transparent refresh control module, the transparent refresh of DRAM refers to that promptly CPU is not disturbing the read and write access of finishing contraposition video memory DRAM under the normal situation about showing of screen, DRAM is the deposit data space of screen display point, it wants display controller CRTC6445 constantly to scan to read to send screen display on the one hand, visited by CPU frequently again on the other hand, the rewriting of carrying out data content refreshes.Therefore for coordinating CPU and CRTC6445 access relation, avoid taking place read/write conflict, this control module specialized designs the CPU read-write sequence of DRAM, CPU only could be read and write DRAM at the low half cycle of character clock, and the high half cycle of character clock is left CRTC6445 scanning demonstration for, finally realizes the transparent refresh of DRAM.Show the synthetic control module of dot matrix converting attribute, this control module reads in 12 parallel point data with a character clock from video memory, and (promptly half Chinese character converts the point data of serial to, then under the driving of a frequency, get a position, through display properties (4 grades gray scale, counter look, glimmer), cursor position and demonstration enable synthetic after, generate three bit digital vision signals, output on the chip pin.The LPTx ports control module, this unit carries out two-stage decode to the IO chip selection signal that CPU sends, and produces the address chip selection signal that mouth and digital mouthful of line printing and parallel print state mouth are controlled in also line printing respectively.

Referring to Fig. 3, Fig. 3 is the logical diagram of keyboard/print module, wherein Keysheet module comprises XT keyboard 0 and 12 keyboard interface controls of XT keyboard, with keyboard 0 is example, KBD0 (keyboard serial data), KBC0 (keyboard clock), KBCLR0 (keyboard clearance) they are the module by signal input end, KBINT0 (keyboard interrupt), D00[7:0] (keyboard parallel data) be the module by signal output terminal.Wherein KBD0, KBC0 come from keyboard, and KBCLR0 comes from CPU; KBINT0 and D00[7:0] output to CPU.PQI (choosing of parallel port address slice), SWR ' (system is write), SRD ' (system is read), A1 ', A2 ' (system address) are the print module signal input parts, PRTC (printing the control mouth), PRTD (print data mouth), PRTS (print state mouth) are the print module signal output parts, by A1 ', A2 PAI and port address being carried out two-stage decode produces respectively and prints control mouthful, data port and the choosing of state mouth sheet, the input signal of this module all comes from system bus, and output signal is to the LPT buffer.Referring to Fig. 4, Fig. 4 is the logical diagram of clock module, and it mainly finishes the read-write control timing of CPU to video memory DRAM.Wherein DCS (choosing of video memory DRAM sheet), SWR ' (system is write), SRD ' (system is read), DOTCLK (point is clock frequently), CCLK (character clock) signal input part, DMRD (video memory DMRA reads), DMWR (video memory DRAM writes), CRD (read lock is deposited in the video memory sheet), READY (wait), CLK6445 (display controller clock) are the module by signal output terminal, except that CCLK in video module, other input signals all come from the outer master control system of sheet.READY outputs to that system CPU, DMWR output to system's video memory, CLK6445 outputs to mainboard display controller 6445.DMRD, CRD output to the display module in the sheet.

Referring to Fig. 5, Fig. 5 is the logical diagram of display module, and this module is mainly finished display process, the inside and outside data bus of sheet switches two functions.When 1) making display process; VDI[15:0] (demonstration parallel data), DOTIN (point frequently), BLKFC0, BLKFC1 (cursor blink rate selection), CUR (cursor position), DISP (demonstration enables), CRTSAVE (screen protection), RESET (system reset) be the module by signal input end; VIDOUT[0:2] (serial video data), CCLK (character clock) be the module by signal output terminal, VDI[15:0] come from the outer system's video memory of sheet.DOTIN comes from the outer clock generator of sheet, and BLKFC0, BLKFC1, CRTSAVE come from the comprehensive register of character access module, and CUR, DISP come from the outer system's display controller of sheet, and RESET comes from system reset.Convert serial to and generate video point data VIDOUT[0:2 by the above-mentioned signal controlling video data that will walk abreast through the processing of display properties such as cursor, flicker and gray scale] output to outside the sheet, sheet outside, send the display demonstration after the AD conversion.2), when making the inside and outside data bus of sheet and switching, VDI[15:0] (video data), DI[15:0] (system bus data), D03[11:8] (display properties data), D00[7:0] (keyboard 0 data), D01[7:0] (keyboard 1 data), DMRD (showing that DRAM reads), DMWR (video memory DRAM writes), CRD (read lock is deposited in the video memory sheet), ATRIBUTE_RD (display properties is read), KBRD0, KBRD1 (keyboard data is read) is the module by signal input end, D[15:0] (system bus), VDO[15:0] (video data), DTEN0, DTEN1 (system bus output enable), VDOTEN (video memory data output enable) is the module by signal output terminal, 4 groups of data bus (keyboards 0 in the sheet, keyboard 1, display properties dot matrix and video memory data) in corresponding C PU read access, data are discharged into system bus D[15:0 by internal control] on.Internal control is with system bus DI[15:0 when CPU writes video memory] on data be discharged into bus VD0[15:0] on.

Referring to Fig. 6, Fig. 6 is the logical diagram of character access module, and this module is mainly finished the character library reference address and produced.MCS3 (Flash-Sel), PCS5 (register slice choosing in the sheet), SWR (system is write), SRD (system is read), A1, A2 (system address), DI[15:0] (system reset is the module by signal input end for (system data bus), RST.CGAD[16:0], BLKFC0, BLKFC1 (flicker frequency selection), LLINE (left side line enables), RLINE (right line enables), ATRIBUTE_RD (display properties is read), NMINE (non-shielding is interrupted enabling), D03[11:8] (display properties), KBCLR0 (keyboard clearance 0), KBCLR1 (keyboard clearance 1), KBRST0 (keyboard clearance 0), KBRST1 (keyboard clearance 1), CRTSAVE (screen protection enables) be the module by signal output terminal, this module controls will convert font address to from system's reveal codes.Finish the control function of some keyboards and demonstration simultaneously by the comprehensive register in inside.

This display process pin of chip is described as follows:

The sequence number pin name is said the name of sth. bright

The choosing of 1 MCS3 character library register slice

The choosing of 2 PAI parallel port address slice

The choosing of 3 PCS5 peripheral hardware sheets

4 MODE keep chip testing and use

5 KBRD1 XT keyboards 1 are read to enable

6 KBRD0 XT keyboards 0 are read to enable

7,42～45, CGAD[0..16] font address

47～56，58～59

8 RST reset signals

10～11 A[1..2] system address

12～15 DATA[0..15] system data

18～21

23～30

16 VSV?VCCA +5V40，65，66，6717，90 VCCI

9,22,34, GND ground

46，57，64，84，96

31 38 KBC0 XT keyboard clocks

KBC1

32 37 KBD0 XT keyboard datas

KBD1

33 36 KBRST0 XT keyboard clearances

KBRST1

The control of 39 PRTC parallel port enables

41 PRTS parallel port states enable 60～63,68～71,73～80 VD[0..15] the VRAM data

81 CLK6445 character clocks

The line of 82 a LLINE Hanzi attributes left side

The right line of 83 RLINE Hanzi attributes

85 SWR systems are write

86 SRD systems are read

87 DMWR DRAM write

88 CUR cursor positions

89 DISP demonstration enables

91,93,94 VIDOUT[0..2] vision signal

92 DOTIN point-frequency signals

97,98 KBINT[0..1] the XT keyboard interrupt

The choosing of 99 DCS system on chip

The non-shielding of 100 NMIEN is interrupted

Claims (1)

1. A kind of 24 dot matrix display process chips, it is characterized in that: it comprises:

   XT keyboard interface control module is used for the serial data from keyboard is converted to parallel data and exports to CPU;

   Character library reference address unit, the character code that is used for visiting from the need of system's input converts the specific address of word-base chip to and outputs to word-base chip;

   DRAM transparent refresh control module is used for CPU not disturbing under the normal situation about showing of screen, finishes the read and write access of contraposition video memory DRAM;

   Show the synthetic control module of dot matrix converting attribute, 12 point data that are used for reading in from video memory in the character clock convert the point data of serial to, and then under the driving of a frequency, get a position, process display properties, cursor position and demonstration generate video output signals after enabling to synthesize;

   Parallel print control unit, the IO chip selection signal that is used for CPU is sent carries out two-stage decode, respectively the address signal of output and line printing control mouth, parallel print data mouth and parallel print state mouth.

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