CN2483914Y - Digital video distribution amplifier - Google Patents
Digital video distribution amplifier Download PDFInfo
- Publication number
- CN2483914Y CN2483914Y CN 01237538 CN01237538U CN2483914Y CN 2483914 Y CN2483914 Y CN 2483914Y CN 01237538 CN01237538 CN 01237538 CN 01237538 U CN01237538 U CN 01237538U CN 2483914 Y CN2483914 Y CN 2483914Y
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- chip
- digital video
- pin
- distribution amplifier
- resistance
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Abstract
A digital video distribution amplifier is characterized in that a cable equilibrium data and clock recovery circuit and a cable drive distribution amplifying circuit are respectively formed by a chip GS9005A and a chip GS9009. A D1 format serial digital video signal is connected to the input end of the chip GS9005A after resistance-capacitance coupled, and the OUT end exports the serial digital video signal in four channels after the distribution and amplification of the GS9009. The utility model has simple structure, easy to debug, high integration, good stability, high reliability, easy to expand.
Description
The utility model relates to serial digital video signal and distributes amplifying device.
Along with the develop rapidly of microelectric technique and TV tech, traditional anolog TV signals will progressively be substituted by digital video signal.And the digital video distribution amplifier is handled the place in various video such as the scheduling of the editing saving of radio data system, making, vision signal, program broadcasts and is had a wide range of applications.Transmission range is long, the simple advantage of physical connection is extremely paid attention to because of having more with respect to the parallel digital video distribution amplifier again for the serial digital video distribution amplifier.Because the high-frequency characteristic of serial digital video signal adopts the ECL logic in the transmission, and to transmission data scrambler.Therefore, the receiving terminal of distribution amplifier must carry out clock, data recovery to the input data that receive earlier, to reduce error code.If adopt resolution element to design, then design circuit is complicated unusually, and index is difficult to control.
The purpose of this utility model is to avoid the complexity of resolution element design, and a kind of digital video distribution amplifier of realizing with large scale integrated circuit is provided, with simplified design, raising performance index.
The purpose of this utility model is achieved through the following technical solutions:
Design feature of the present utility model is to constitute cable equalization and data clock recovery circuit by GS9005A chip U1, constitute cable drive by GS9009 chip U2 and distribute amplifying stage, one road D1 form serial digital video signal inserts the SDI end of chip U1 through resistance R 8, capacitor C 3 couplings, the SDO of chip U1 end ,/output of SDO end differential level insert respectively chip U2 /IN end and IN end, and divide four the tunnel to export serial digital video signals at the OUT of chip U2 end.
Compared with the prior art, the utlity model has following advantage:
1, the utility model directly receives one road input signal by U1 as digital video signal 1 minute 4 o'clock, exports four road signals by U2, its overall structure is simplified greatly, easily debugging, good stability, the reliability height, performance index such as signal jitter, overshoot all are better than relevant national standard.
2, can drive multi-disc GS9009 by chip U1 data recovered in the utility model.When with two GS9009 chips and when connecing, can realize one tunnel serial input, 8 tunnel serials distribute amplifies output.Has favorable expansibility.
Accompanying drawing is the utility model structural representation.
By the following examples, in conjunction with the accompanying drawings the utility model being done a step describes.
Embodiment:
Referring to accompanying drawing, present embodiment is to constitute cable equalization and data clock recovery circuit by GS9005A chip U1, constitutes cable drive by GS9009 chip U2 and distributes amplifying stage.
Shown in the figure, owing to be input as the single-ended input of serial digital video, therefore, the A/D of chip U1 holds 1 pin to connect+5V by resistance R 86, controls as automatic gain in the capacitor C 57 that its AGC holds 2 pin to insert.One road serial digital video signal D1 holds 8 pin through the SDI that resistance R 8, capacitor C 3 couplings insert chip U1, the SDO of chip U1 hold 25 pin ,/SDO hold 24 pin differential level output insert respectively chip U2 /IN holds 10 pin and IN to hold 11 pin, and divides four tunnel output serial digital video signals at the OUT of chip U2 end.
In the present embodiment, hold 13 pin, the temperature-compensation circuit that is made of resistance R 1, R2, adjustable resistance RT3 and capacitor C 15, voltage-stabiliser tube D3 is set at the RV0 of chip U1.Guaranteeing in wide temperature range, chip U1 can stablize and catches serial digital signal, realizes the stable recovery of data clock.
In the present embodiment, hold 12 pin, the peripheral charging and discharging circuit of the phase-locked loop that is made of resistance R 8, capacitor C 1, C10 is set at the LOP of chip U1.With the serial data signal that guarantees that phase-locked loop pll can be caught 270 Mb/s.
In the present embodiment, hold 7 pin settings to adjust circuit by the output amplitude that variable resistor R33 constitutes at the Vset of chip U2.So that the output serial digital video signal is adjustable continuously in 0-1000 mV scope, realize that the wide region of serial signal amplitude is regulated.
In addition,, the cable matching network that is made of resistance R 35, capacitor C 22, C19 is set, in order to drive serial digital video output at the OUT of chip U2 output.
Claims (5)
1, digital video distribution amplifier, it is characterized in that constituting cable equalization and data clock recovery circuit by chip U1 (GS9005A), constitute cable drive by chip U2 (GS9009) and distribute amplifying stage, one road D1 form serial digital video signal inserts the SDI end (8 pin) of chip U1 through resistance R 8, capacitor C 3 couplings, the SDO of chip U1 end (25 pin) ,/output of SDO end (24 pin) differential level insert respectively chip U2 (GS9009) /IN end (10 pin) and IN end (11 pin), and divide four the tunnel to export serial digital video signals at the OUT of chip U2 end.
2, digital video distribution amplifier according to claim 1 is characterized in that the RV0 end (13 pin) at described chip U1, and the temperature-compensation circuit that is made of resistance R 1, R2, adjustable resistance RT3 and capacitor C 15, voltage-stabiliser tube D3 is set.
3, digital video distribution amplifier according to claim 1 is characterized in that the LOP end (12 pin) at described chip U1, and the peripheral charging and discharging circuit of the phase-locked loop that is made of resistance R 8, capacitor C 1, C10 is set.
4, digital video distribution amplifier according to claim 1 is characterized in that at the Vset end (7 pin) of described chip U2 the output amplitude regulating circuit that is made of variable resistor R33 being set.
5, digital video distribution amplifier according to claim 1 is characterized in that the output at the OUT of described chip U2, and the cable matching network that is made of resistance R 35, capacitor C 22, C19 is set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01237538 CN2483914Y (en) | 2001-04-26 | 2001-04-26 | Digital video distribution amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01237538 CN2483914Y (en) | 2001-04-26 | 2001-04-26 | Digital video distribution amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2483914Y true CN2483914Y (en) | 2002-03-27 |
Family
ID=33650318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01237538 Expired - Fee Related CN2483914Y (en) | 2001-04-26 | 2001-04-26 | Digital video distribution amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2483914Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103188450A (en) * | 2011-12-30 | 2013-07-03 | 北京同步科技有限公司 | Digital video distributor and processing method of the same |
-
2001
- 2001-04-26 CN CN 01237538 patent/CN2483914Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103188450A (en) * | 2011-12-30 | 2013-07-03 | 北京同步科技有限公司 | Digital video distributor and processing method of the same |
| CN103188450B (en) * | 2011-12-30 | 2015-11-11 | 北京同步科技有限公司 | digital video distributor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |