CN2469535Y

CN2469535Y - Anti-shaking button

Info

Publication number: CN2469535Y
Application number: CN 01207933
Authority: CN
Inventors: 李长来; 赵晓彤; 杨建杰
Original assignee: 李长来
Priority date: 2001-03-15
Filing date: 2001-03-15
Publication date: 2002-01-02
Anticipated expiration: 2011-03-15

Abstract

The utility model discloses a dither preventing push button, which consists of a push button and a dither preventing circuit, wherein the dither preventing circuit consists of a D latch trigger and a return circuit consisting of and-not gates, resistors and capacitors. One end of the push button connects with the input end of the trigger, and the other end connects with a first input end of the return circuit; the output end of the trigger connects with a second input end of the return circuit; the output end of the return circuit connects with the control end of the trigger. The output signals of the push button are output after passing though the D latch trigger and the return circuit, and therefore, the output signals are more regular, therefore can be better utilized by follow-up circuits.

Description

Anti-shake button

The utility model relates to a kind of button, refers to the button of a kind of stable output signal, non-jitter especially.

Button uses very extensive on various electrical equipment, instrument, and people are the work by button control electrical equipment often.In use, people may have such experience, and after pressing the button, electrical equipment is not worked, or, obviously be that electrical equipment has been carried out multi-pass operation by a knob down.Cause the reason of this phenomenon to be: button produces shake, generates hash, and the circuit that makes the back is identification signal correctly, down to misoperation.In order to eliminate shake, people have added the RC circuit in the button back.Though adopt this method can eliminate some shakes, effect is not fine, and treated signal is rule inadequately, can not be used well by subsequent conditioning circuit.

In view of the foregoing, the purpose of this utility model provides a kind of stable output signal, rule, the anti-shake button that can be used by subsequent conditioning circuit well.

For achieving the above object, the utility model adopts following design: a kind of anti-shake button, and it is made of a button and a preventing jittering circuit; Described preventing jittering circuit is again to be made of trigger and reset circuit; One end of described button links to each other with the input of trigger; The other end links to each other with the first input end of reset circuit; The output of trigger links to each other with second input of reset circuit; The output of reset circuit links to each other with the control end of trigger.

Be described in further detail below in conjunction with the drawings and specific embodiments.

Fig. 1 is the anti-shake button circuit schematic diagram of the utility model.

As shown in Figure 1, the utility model is to adhere to a preventing jittering circuit behind conventional push button S.Preventing jittering circuit is to be made of D latched flip flop U1 and reset circuit 2; Reset circuit 2 is made up of NAND gate U2 and resistance R, capacitor C again, and the input of reset circuit 2 links to each other with the output of trigger U1, and the output of reset circuit is that the CLR end links to each other with the control end of trigger.

As shown in the figure, the end of button S links to each other with the input D of D latched flip flop U1, and the other end links to each other with the input 1 of NAND gate U2 with the PR end of U1; The output Q of U1 links to each other with the input 2 of NAND gate U2; The output of U2 links to each other with the CLR end of U1 by resistance R; A capacitor C in parallel between the signal output part Q of U1 and CLR end.

When button S was not pressed, the signal output part Q of D latched flip flop U1 was low level " 0 ".When button S was pressed, the signal output part Q of U1 was high level " 1 ", and the output of reset circuit is a high level, and both the CLR of trigger U1 end was high level.Therefore, this moment, no matter how button S shook, and the output Q of U1 can not change.After a while, when the CLR of U1 end was " 0 ", the output Q of U1 became " 0 ", waits for next button signal.U1 output Q keeps the time of high level, and promptly the CLR of U1 end can change by R, the C that adjusts in the reset circuit for the time of " 1 ".

Because the utility model is to adhere to a preventing jittering circuit after conventional push button, the output signal that makes button through a D latched flip flop and reset circuit after output again, the output signal of button is more regular, stable, can be used by subsequent conditioning circuit well.

The above only is preferred embodiment of the present utility model, and the equivalent transformation of any basic utility model technical scheme all belongs within the utility model protection range.

Claims

1, a kind of anti-shake button is characterized in that: it is made of a button and a preventing jittering circuit;

Described preventing jittering circuit is again to be made of trigger and reset circuit;

One end of described button links to each other with the input of trigger; The other end links to each other with the first input end of reset circuit;

The output of trigger links to each other with second input of reset circuit; The output of reset circuit links to each other with the control end of trigger.

2, a kind of anti-shake button according to claim 1, it is characterized in that: described trigger is the D latched flip flop; Described reset circuit is made up of NAND gate and resistance, electric capacity.

3, a kind of anti-shake button according to claim 2 is characterized in that: an end of described button links to each other with the input of D latched flip flop, and the other end links to each other with an input of NAND gate with the PR end of D latched flip flop; Another input of the output of D latched flip flop and NAND gate links to each other; The output of NAND gate links to each other with the CLR end of D latched flip flop by resistance; An electric capacity in parallel between the signal output part Q of D latched flip flop and CLR end.