CN2461238Y - 可堆叠式的积体电路装置 - Google Patents

可堆叠式的积体电路装置 Download PDF

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Publication number
CN2461238Y
CN2461238Y CN 00264804 CN00264804U CN2461238Y CN 2461238 Y CN2461238 Y CN 2461238Y CN 00264804 CN00264804 CN 00264804 CN 00264804 U CN00264804 U CN 00264804U CN 2461238 Y CN2461238 Y CN 2461238Y
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China
Prior art keywords
integrated circuit
electrically connected
basal layer
stackable
contacts
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Expired - Fee Related
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CN 00264804
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Inventor
叶乃华
杜修文
彭国峰
陈文铨
何孟南
邱咏盛
吴志成
范光宇
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Kingpak Technology Inc
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Kingpak Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Combinations Of Printed Boards (AREA)

Abstract

本实用新型涉及电路板,使制作方便省料。其包括:一积体电路本体、一个以上第一接点、一凸缘层及一个以上第二接点,其特征是:积体电路本体具有一第一表面及一第二表面;该等第一接点形成于与电路板电连接的积体电路本体的第一表面上;该等第二接点设于凸缘层上,以与第二积体电路形成电连接。用于电器。

Description

可堆叠式的积体电路装置
本实用新型涉及积体电路。
前已申请的中国实用新型专利第00257235.4号可堆叠式的积体电路，其可将多个积体电路予以堆叠，使每一电路板上可容置更多的积体电路，不但可增加产品功能，且可达到产品轻、薄、短小的要求，如图1所示：其上层的积体电路10与下层的积体电路12间以一较大的金属球14连接而该金属球14的制作较为不便，成品率较低，还浪费金属球14所用的材料。
本实用新型的目的是提供一种制作较为方便，成品率较高，节省材料，降低成本的可堆叠式的积体电路装置。
本实用新型的目的是这样实现的：可堆叠式的积体电路装置，其为电连接于一电路板上，并与第二积体电路形成堆叠的一种电路装置，其包括：一积体电路本体、一个以上第一接点、一凸缘层及一个以上第二接点，其特征是：积体电路本体具有一第一表面及一第二表面上；该等第一接点形成于与电路板电连接的积体电路本体的第一表面；该等第二接点设于凸缘层上，以与第二积体电路形成电连接。
上述设计主要由于采用金属球第一接点，从而达到了制作较方便，成品率较高，且节省材料和成本的效果。
下面以附图、实施例进一步说明。
图1为已有可难叠式的积体电路实施示意图；
图2为本实用新型实施示意图；
图3为本实用新型组合剖视示意图；
图4为本实用新型分解立体示意图。
如图2-4所示：本实用新型为电连接于一电路板20上，并与第二积体电路24形成堆叠的一种电路装置，其包括：一积体电路本体16、一个以上第一接点18、一凸缘层34及一个以上第二接点22，其特征是：积体电路本体1 6具有一第一表面26及一第二表面28；该等第一接点18形成于与电路板20电连接的积体电路本体16的第一表面26上；该等第二接点22设于凸缘层34上，以与第二积体电路24形成电连接。其中，该积体电路本体16包括有一基础层30、一晶片38及一条以上导线36，基础层30有一镂空槽32，晶片38藉由该等导线36穿过镂空槽32而与基础层30形成电连接；其中，该等第一接点1 8设有金属球，用以与电路板20形成电连接；其中，该等第二接点22设有金属球，用以与电路板20形成电连接；其中，该第二积体电路24本体包括有一基础层30、一晶片38及一条以上导线36，基础层30有一镂空槽32，使晶片38藉由该等导线36穿过镂空槽32与基础层30形成电连接。其中，凸缘层34为框形状，并粘着于积体电路本体16的第二表面28上。可使第一积体电路的金属球大小相同，可单颗积体电路封装后再行堆置，制作方便、省料。

Claims (5)

1、可堆叠式的积体电路装置，其为电连接于一电路板上，并与第二积体电路形成堆叠的一种电路装置，其包括：一积体电路本体、一个以上第一接点、一凸缘层及一个以上第二接点，其特征是：积体电路本体具有一第一表面及一第二表面；该等第一接点形成于与电路板电连接的积体电路本体的第一表面上；该等第二接点设于凸缘层上，以与第二积体电路形成电连接。
2、如权利要求1所述的可堆叠式的积体电路装置，其特征是：其中，该积体电路本体包括有一基础层、一晶片及一条以上导线，基础层有一镂空槽，晶片藉由该等导线穿过镂空槽而与基础层形成电连接
3、如权利要求1所述的可堆叠式的积体电路装置，其特征是：其中，该等第一接点设有金属球。
4、如权利要求1所述的可堆叠式的积体电路装置，其特征是：其中，该等第二接点设有金属球。
5、如权利要求1所述的可堆叠式的积体电路装置，其特征是：其中，该第二积体电路本体包括有一基础层、一晶片及一条以上导线，基础层有一镂空槽，使晶片藉由该等导线穿过镂空槽与基础层形成电连接。
CN 00264804 2000-12-13 2000-12-13 可堆叠式的积体电路装置 Expired - Fee Related CN2461238Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI573515B (zh) * 2015-06-01 2017-03-01 宜鼎國際股份有限公司 疊板構造

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI573515B (zh) * 2015-06-01 2017-03-01 宜鼎國際股份有限公司 疊板構造

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