CN2426993Y

CN2426993Y - The smallest system board for universal one-chip machine

Info

Publication number: CN2426993Y
Application number: CN 00229835
Authority: CN
Inventors: 张玉; 杨庆欣
Original assignee: Individual
Current assignee: Individual
Priority date: 2000-04-30
Filing date: 2000-04-30
Publication date: 2001-04-18
Anticipated expiration: 2010-04-30

Abstract

The utility model relates to a smallest system board for a universal single-chip microcomputer, which is mainly composed of the following parts: a single-chip microcomputer, a memory, analog-to-digital/digital-to-analog conversion, an I/O extender, a keyboard and display controller, an interruption expander circuit, a bus line driver, a power source monitoring circuit, an ALE signal restoration circuit, a main and auxiliary interface, etc. The interruption expander circuit is provided with a combinational logic circuit, which solves the compatibility problem of the work time sequence of an interruption expander controller and the single-chip microcomputer, and a watchdog, a power supply monitor and other antijamming measures for the power supply are added. The utility model restores the system address latch signal ALE signal so that the ALE signal can be used as a standard frequency scale clock signal, provides abundant interface functions, and has the characteristics of powerful function, stable performance, high universality, etc.

Description

General single chip minimum system plate

The utility model relates to a kind of single-chip microcomputer electronic product, particularly a kind of general single-chip minimum system plate.

The single-chip minimum system plate is the instrument that the user carries out the single-chip microcomputer product development, and it comprises: single-chip microcomputer, address latch, address decoder, program storage, data-carrier store, I/O expanded circuit, interruption expanded circuit, oscillatory circuit, reset circuit, power filter, keyboard, demonstration etc.At present the single-chip minimum system plate on the home market exists defective and the deficiency on a lot of functions, interrupts extending controller and single-chip microcomputer incompatible problem on work schedule as not solving, thereby can't interrupt expanding by it; Lack interference protection measures such as house dog, Power Supply Monitoring; The user directly the ALE of using system as standard frequency marking clock signal; The interface that offers user's use is single and complicated; Valuable product etc.

The purpose of this utility model is exactly the deficiency at the said goods, for the user provides a kind of cost performance higher Single Chip Microcomputer (SCM) system plate.

For achieving the above object, the utility model proposes following technical solution:

The native system plate mainly consists of the following components: single-chip microcomputer, program storage, data-carrier store, analog to digital conversion, digital-to-analog conversion, the I/O extender, keyboard, display controller and display keyboard, the RS232 serial line interface, general parallel mini-printer interface, interrupt expanded circuit, bus driver, power supply supervisory circuit, ale signal is repaired circuit, main interface, auxilliary interface/LPT etc., its connected mode is: the data of single-chip microcomputer, the address, control bus is connected to program storage after overdriving, data-carrier store, analog to digital conversion, digital-to-analog conversion, interrupt expander, the I/O extender, keyboard, display controller; The ale signal of data, address, control bus, interruption, I/O expansion and single-chip microcomputer is delivered to main interface and auxilliary interface/LPT after repairing; Keyboard, display controller are directly controlled and are shown and keyboard; The power supply of power monitoring chip control single chip computer and resetting; The serial communication chip connects single-chip microcomputer and serial line interface.

Simultaneously, the native system plate has adopted the combinational logic circuit scheme to solve to interrupt extending controller and single-chip microcomputer incompatible problem on work schedule, thereby has expanded the limited interrupt resources of single-chip microcomputer.Interrupt with the logic gate expansion than traditional, not only increased the quantity of interrupting expansion greatly, can also finish the functions such as priority queueing, interrupt nesting of interruption, improved the real-time that total system is handled greatly.

Its technical scheme is that the interruption application end INT with interrupt expander links to each other with the interruption receiving end INT0 or the INT1 of single-chip microcomputer through reverser A1, again with the read signal RD of single-chip microcomputer through reverser A2 generation/RD signal, / RD signal and INT signal produce interrupt acknowledge signal INTA signal through Sheffer stroke gate B1, deliver to the INTA end of interruptable controller, simultaneously, the new read signal RD ' that produces through Sheffer stroke gate B2 of this INTA signal and/RD signal delivers to the read signal RD end of interruptable controller.

Its principle of work is: when normal condition (no interrupt request), the INTA signal of interruptable controller is a high level, the RD signal of interruptable controller is followed the RD signal of single-chip microcomputer and is changed, but when interrupt request takes place, three MOVX A when single-chip microcomputer is carried out, @DPTR reads instruction, interruptable controller just can receive three INTA pulse signals, and the RD signal of interruptable controller is in high level all the time, interruptable controller divided the machine code of CALL instruction and delivered on the data bus for three times this moment, single-chip microcomputer reads back reservation interrupt vector address wherein just can carry out corresponding interrupt service routine, wherein the RD signal of the RD signal of single-chip microcomputer and interruptable controller, INTA has following logical relation:

INTA	1		2
Single-chip microcomputer RD	1		2		1	0	1	0
Interruptable controller RD	1	0	1	1
	Normal condition		Normal condition

For guaranteeing the stability of system, the native system plate utilizes power monitoring chip to increase Anti-Jamming Techniques such as house dog, Power Supply Monitoring on the hardware of system board.The going of this circuit feasible system shakes that electrification reset, hand-reset, supply voltage disturb the system reset that causes, program that software defect causes to run fast to reset and the functions such as supply voltage of surveillance.

Its technical scheme is: the Reset end of power monitoring chip links to each other with single-chip microcomputer Reset end, the WDI end of power monitoring chip links to each other with an I/O mouth of single-chip microcomputer, the WDO end of power monitoring chip links to each other with the MR end of power monitoring chip with a diode D1 through short circuit wire jumper J1, simultaneously, the MR end of power monitoring chip is through reset key P1 ground connection, the PFO end of power monitoring chip joins with the interruption application end INT0 or the INT1 of single-chip microcomputer, the PFI end of power monitoring chip joins by a big value pull-up resistor R1 and power supply VCC, and the PFI end is drawn for the user through the I/O expansion bus and monitored the use of external unit voltage simultaneously.

Its principle of work is: when power supply electrifying, when just having reached system works voltage threshold 4.65V as if supply voltage, power monitoring chip Reset end will continue to keep the reset signal of output 200ms, make system reset, wait for stablizing of power supply; When reset key P1 pressed, hand-reset MR end obtained low level, and power monitoring chip is held the output reset signal at Reset after 200ms goes the shake time-delay; When power supply is interfered, when making voltage vcc be lower than system works threshold voltage 4.65V, power monitoring chip is also in Reset end output reset signal (high level), after disturbing, it is normal that Vcc recovers, pass through 200ms again after, Reset just recovers invalid (low level), operate as normal is restarted by system, and this section period is about 350ms, disturbs so this technology can detect the moment low level of Millisecond; Single-chip microcomputer is exported square wave by an I/O mouth (as P1.7) to the WDI of power monitoring chip end, but the high level of square wave and low level width all can not surpass 1.6s, WatchDog Timer in the power monitoring chip just can not overflow like this, WDO also keeps high level, the MR end also keeps high level, system's operate as normal; When the defective owing to software makes system program walk to fly, or enter endless loop, this I/O mouth of single-chip microcomputer just no longer normally output pulse width less than the square wave of 1.6s, the power monitoring chip WatchDog Timer overflows, and the WD0 end becomes low level by high level, diode D1 conducting, MR obtains effective low level, power monitoring chip Reset end output reset signal resets single-chip microcomputer and restarts operate as normal, guarantees security of system.Certainly, the user also can whether need select this function by house dog wire jumper J1.The PFI end of power monitoring chip is left the user for and is monitored the use of external unit voltage, and when the voltage of this end was lower than 1.25V, the internal comparator output terminal PFO of power monitoring chip presented low level, to single-chip microcomputer application power fail interrupt, carries out respective handling.

Because the characteristics of the address latch signal ALE self of Single Chip Microcomputer (SCM) system (can lose a pulse during read-write external data), the user can't directly use it as standard frequency marking clock signal.This system board by the easy realization of combinational logic circuit the reparation of ale signal, make it reach frequency accuracy and degree of stability with the same order of magnitude of system's crystal oscillator, can directly use fully as standard frequency marking clock signal.

Its technical scheme is: the read signal RD of single-chip microcomputer and write signal WR respectively as with the input of door C1, and the input end of Sheffer stroke gate B3 is delivered in C1 output, single-chip microcomputer address latch signal ALE delivers to another input end of Sheffer stroke gate B3 behind reverser A3, like this, the output of Sheffer stroke gate B3 is the standard frequency marking clock signal that obtains through repairing.

Its principle of work is: when system carries out read-write operation to the outside, ale signal produces losing of a pulse, behind above-mentioned logical circuit, the relation of output frequency standard signal and read-write and input ale signal can be expressed as: ALE=/((WR*RD) (/ALE)), thereby utilize read-write to recover the pulse of losing, make the signal of output keep integrality.

In the Peripheral Interface design to the user, the utility model had both been considered the many as far as possible of interface function, took into account succinct and convenient use of interface again.We provide data bus, address bus, control bus, I/O expansion, have interrupted interface lines (totally 50 pins) such as expansion, A/D sampling, D/A sampling, power supply output and monitoring for the user, we also provide interface lines (totally 26 pins) such as mini-printer interface, auxiliary I/O expansion in addition, improve the utilization factor of interface greatly, saved cost.

Its technical scheme and principle are: the part I/O mouth (as P1.5, P1.6 etc.) of PB0-PB7, PC0-PC2 mouth and the single-chip microcomputer of I/O extender (as 8255) is received on the printing interface (auxiliary I/O interface), and wherein the I/O extender I/O mouth PCO delivers to of system through the short circuit wire jumper and interrupts the application end.Printing interface just both can be used as common I/O mouth use so at ordinary times, also can be used as the mini-printer interface and used.Can print wire jumper selection employing inquiry mode or interrupt mode by being provided with during printing.

Because the utility model adopted above technical scheme, thereby improve this system board system performance greatly, had characteristics such as powerful, stable performance, highly versatile.

Below in conjunction with accompanying drawing this practicality newly is further described:

Fig. 1 is a theory diagram of the present utility model;

Fig. 2 is the interruption Extended Principle Diagram of system in the utility model.

Fig. 3 is the anti-interference schematic diagram of system in the utility model.

Fig. 4 is that the ale signal of system in the utility model is repaired schematic diagram.

Fig. 1 is a theory diagram of the present utility model.Wherein, the 1st, single-chip microcomputer, the 2nd, system's immunity module, the 3rd, system's ale signal is repaired module, and the 4th, interrupt expansion module, the 5th, A/D, D/A modular converter, the 6th, I/O expansion module, the 7th, keyboard, display module; The 8th, program, data-carrier store module, the 9th, serial communication module, they all are that data, address, control three big buses by system link to each other with single-chip microcomputer 1; The 10th, the main Peripheral Interface of system is drawn interface lines such as the data bus of system, address bus, control bus, I/O expansion, interruption expansion, A/D sampling, D/A sampling, power supply output and monitoring by it; The 11st, mini-printer interface, auxiliary I/O expansion interface, the 12nd, serial communication interface.

Fig. 2 is the interruption Extended Principle Diagram of system in the utility model.It is single-chip microcomputer 1 and the catenation principle figure that interrupts expansion module 4, and wherein 13 for interrupting extending controller, and it expands to eight interruptions of IR0-IR7 to the interrupt INT 0 (or INT1) of single-chip microcomputer 1 by logic gates such as not gate A1, A2, Sheffer stroke gate B1, B2.Wherein: INTA is the interrupt acknowledge signal of interruptable controller, and RD ' is the read signal of interruptable controller, and RD is the read signal of single-chip microcomputer.

Fig. 3 is the anti-interference schematic diagram of system in the utility model.It is the catenation principle figure of single-chip microcomputer 1 and system's immunity module 2, wherein 14 is power monitoring chip, its diode D1, house dog wire jumper J1, reset key P1, resistance R 1 by system reset line Reset, system I/O line, interrupt application line PF0 and link to each other with single-chip microcomputer 1.Wherein: PFI is peripheral hardware supply voltage monitoring side, and WR is the hand-reset end, and WDO is the house dog output terminal.

Fig. 4 is that the ale signal of system in the utility model is repaired schematic diagram.Wherein WR, RD, the ale signal of single-chip microcomputer 1 carried out ALE ' standard frequency marking clock signal after logical combination has obtained repairing with door C1, not gate A3, Sheffer stroke gate B3.

Claims

1. general single-chip minimum system plate, mainly consist of the following components: single-chip microcomputer, program storage, data-carrier store, analog to digital conversion, digital-to-analog conversion, I/O extender, keyboard, display controller and display keyboard, RS232 serial line interface, general parallel mini-printer interface, interruption expanded circuit, bus driver, power supply supervisory circuit, ale signal are repaired circuit, major-minor interface, it is characterized in that: interruption expanded circuit wherein is at single-chip microcomputer and interrupts having increased by a combinational logic circuit between extending controller; Power supply supervisory circuit is to utilize power monitoring chip to increase the house dog Anti-Jamming Technique on the hardware of system board; It is to have connected a combinational logic circuit on ALE, WR, the RD pin at single-chip microcomputer that ale signal is repaired circuit; On the peripheral hardware Interface design, data bus, address bus, control bus, I/O expansion are provided, have interrupted interface line and interface lines such as mini-printer interface, auxiliary I/O expansion such as expansion, A/D sampling, D/A sampling, power supply output and monitoring.

2. system board according to claim 1, it is characterized in that: described interruption expanded circuit is that the interruption application end INT with interrupt expander links to each other with the interruption receiving end INT0 or the INT1 of single-chip microcomputer through reverser A1, again with the read signal RD of single-chip microcomputer through reverser A2 generation/RD signal, / RD signal and INT signal produce interrupt acknowledge signal INTA signal through Sheffer stroke gate B1, deliver to the INTA end of interruptable controller, simultaneously, the new read signal RD ' that produces through Sheffer stroke gate B2 of this INTA signal and/RD signal delivers to the read signal RD end of interruptable controller.

3. system board according to claim 1, it is characterized in that: the Reset of power monitoring chip end links to each other with single-chip microcomputer Reset end in the described power supply supervisory circuit, the WDI end of power monitoring chip links to each other with an I/O mouth of single-chip microcomputer, the WD0 end of power monitoring chip links to each other with the MR end of power monitoring chip with a diode D1 through short circuit wire jumper J1, simultaneously, the MR end of power monitoring chip is through reset key P1 ground connection, the PFO end of power monitoring chip joins with the interruption application end INT0 or the INT1 of single-chip microcomputer, the PFI end of power monitoring chip joins by a big value pull-up resistor R1 and power supply VCC, and the PFI end is drawn for the user through the I/O expansion bus and monitored the use of external unit voltage simultaneously.

4. system board according to claim 1, it is characterized in that: described ale signal repair the read signal RD of single-chip microcomputer in the circuit and write signal WR respectively as with the input of door C1, and the input end of Sheffer stroke gate B3 is delivered in C1 output, single-chip microcomputer address latch signal ALE delivers to another input end of Sheffer stroke gate B3 behind reverser A3, like this, the output of Sheffer stroke gate B3 is the standard frequency marking clock signal that obtains through repairing.

5. system board according to claim 1, it is characterized in that: described major-minor interface is that the part I/O mouth of the PB0-PB7 of I/O extender, PC0-PC2 mouth and single-chip microcomputer is received on the printing interface, and wherein the I/O extender I/O mouth PC0 delivers to of system through the short circuit wire jumper and interrupts the application end.