CN2366973Y - Electrostatic inductor for long lime closing type goove grating - Google Patents

Electrostatic inductor for long lime closing type goove grating Download PDF

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CN2366973Y
CN2366973Y CN 99208627 CN99208627U CN2366973Y CN 2366973 Y CN2366973 Y CN 2366973Y CN 99208627 CN99208627 CN 99208627 CN 99208627 U CN99208627 U CN 99208627U CN 2366973 Y CN2366973 Y CN 2366973Y
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silicon substrate
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substrate film
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李思敏
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Abstract

The utility model relates to an electrostatic inductor for long lime closing type groove-shaped grating, which comprises a silicon substrate sheet, a source region, a base region, gating regions and a drain region. The upper surface of the source area is connected with a phosphorus-mixing polycrystalline silicon layer which is connected with a metal layer of a source electrode, the bottom surface and the side surface of each groove are covered with insulating layers, and the insulating layer of the side surface is extended to the upper surface of the silicon substrate sheet. Between two contiguous P+ type gating regions, the insulating layer of the upper surface of the silicon substrate sheet and the lower surface of the N+ type source region of the upper surface of the silicon substrate sheet are provided with a P type base region, and the depth of the P type base region is shallower than the depth of the P+ type gating region. The utility model has the advantages that the forward conduction and the stop blocking capability can be realized simultaneously, the property of the forward conduction is uniform and coincident, and the current density is large.

Description

The closed type slotted-form grid electrostatic inductor
The utility model relates to the closed type slotted-form grid electrostatic inductor, belongs to technical field of manufacturing semiconductors.
Electrostatic induction device claims junction type power field effect device again, and it has the performance of a series of excellences such as high pressure, big electric current, high frequency, and wide application prospect and development prospect are arranged.
Electrostatic induction device comprises static induction transistor SIT (Static Induction Transistor), static induction thyristor SITH (Static Induction Thyristor), Property of Bipolar Static Induction Transistor BSIT (Bipolar Static Induction Transistor) or the like.Electrostatic induction device also comprises the multiple device that engages with bipolar device, as series connection bipolar electrostatic induction transistor SEBISIT (Seral BipolarStatic Induction Transistor), grid turn-off thyristor GTO (Gate Turn-OffThyristor) or the like.
Slotted-form grid electrostatic inductor is the new class electrostatic induction device that grew up in recent years, compare with the buried grid electrostatic induction device with old surperficial grid electrostatic inductor, slotted-form grid electrostatic inductor has that current capacity is strong, electrical quantity high conformity, the advantage that is easy to produce in batches.
The basic structure of slotted-form grid electrostatic inductor can be with reference to figure 3 (the flat 8-316494 of Japan Patent JP): in lower floor is that low resistivity layer 42, upper strata are that the upper surface of the silicon substrate film 4 of N-type resistive formation 41 has N+ type source region 3, have many grooves 5 on the upper surface of silicon substrate film 4, P+ type grid region 6 is arranged in the bottom of every groove 5, gate electrode 7 is arranged above the grid region 6, and lower floor's low resistivity layer 42 of silicon substrate film 4 is drain regions.Drain region 42 can be the N+ type, also can be the P+ type.Below the top active electrode 1 in source region 3, drain region 42 drain electrode 8 is arranged.
Application number is 98218523.5 Chinese utility model patent " slotted-form grid electrostatic inductor ", a kind of new slotted-form grid electrostatic inductor has been proposed, it has adopted the phosphorous doped polysilicon structure, connection phosphorous doped polysilicon layer on the source region, and the phosphorous doped polysilicon layer is connected with the source metal level.Its typical structure as shown in Figure 4, wherein 9 is the phosphorous doped polysilicon layer, 10 is insulating barrier, it is compared with the slotted-form grid electrostatic inductor that does not adopt the phosphorous doped polysilicon structure, have emission effciency height, forward current conducting density big, can avoid junction spiking, can adopt shallow slot technology, be easy to advantage such as processing.
Slotted-form grid electrostatic inductor divides open type and closed type two classes, and no matter the closed type electrostatic induction device with flute profile grid structure has the phosphorous doped polysilicon structure or do not have the phosphorous doped polysilicon structure, all exists some shortcoming:
The forward conduction characteristic that shortcoming is the closed type slotted-form grid electrostatic inductor is inhomogeneous.In slotted-form grid electrostatic inductor, form two PN junctions between two adjacent P+ flute profile grid and the silicon substrate film N-type resistive formation, the overlapping degree of the space charge region of these two adjacent PN junctions has a strong impact on the forward conduction characteristic of device.Because the inhomogeneous spacing of sheet inside groove that caused of exposure intensity is inhomogeneous in the photoetching process, thereby make the overlapping degree of space charge region of adjacent two PN junctions inhomogeneous, cause the forward conduction characteristic inhomogeneous.
Another shortcoming be the closed type slotted-form grid electrostatic inductor the forward conduction ability with by the time blocking ability be difficult to take into account simultaneously.In the closed type electrostatic induction device, the space charge region of two adjacent PN junctions overlaps dark more, and the blocking ability when ending is strong more, but the forward conduction ability is weak more.Otherwise the space charge region of two adjacent PN junctions overlaps shallowly more, and the blocking ability when ending is weak more, but the forward conduction ability is just strong more.And forward conduction and all very responsive to the overlapping degree of space charge region by this two specific character of blocking-up, be difficult to take into account simultaneously.
The forward conduction ability that the 3rd shortcoming is the closed type slotted-form grid electrostatic inductor is big not enough.The forward conduction ability of closed type electrostatic induction device is subjected to the restriction of the resistive formation thickness of silicon substrate film, and this thickness determines by blocking voltage, can not be too thin, so the current gain of closed type electrostatic induction device under big electric current can not be too big.
In view of above-mentioned, the purpose of this utility model just provide a kind of forward conduction characteristic uniformity, can take into account the forward conduction ability simultaneously and by closed type slotted-form grid electrostatic inductor blocking ability, that forward current is bigger.
The purpose of this utility model is achieved in that
A kind of closed type slotted-form grid electrostatic inductor, comprise that lower floor is that low resistivity layer, upper strata are silicon substrate film, source region and source electrode metal layer, base, grid region and gate electrode, drain region and the drain electrode metal level of N-type resistive formation, N+ type source region is at the upper surface of silicon substrate film, have groove on the upper surface of silicon substrate film more than one, the bottom of every groove is P+ type grid region, lower floor's low resistivity layer of silicon substrate film is the drain region, is the drain electrode metal level below the drain region, it is characterized in that:
The top connection phosphorous doped polysilicon layer in described source region, this phosphorous doped polysilicon layer is connected with the source electrode metal layer;
The bottom surface of described every groove and side cover insulating barrier, and the side insulation layer extends to the upper surface of silicon substrate film;
Between described two adjacent P+ type grid regions, below silicon substrate film upper surface insulating barrier and silicon substrate film upper surface N+ type source region, a P type base is arranged, the depth as shallow in the depth ratio P+ type grid region of P type base.
In implementing measure of the present utility model:
Be connected the phosphorous doped polysilicon layer on the insulating barrier of the bottom surface of described every groove, side and upper surface.
The upper strata N-resistive formation of described silicon substrate film is divided into two-layer, and the resistivity on upper strata is higher than lower floor.
Described silicon substrate film lower floor low resistivity layer drain region is P+ type drain region or N+ type drain region.
The degree of depth of described groove is the 2-5 micron, and the spacing of two adjacent slots is 4-20 microns.
Closed type slotted-form grid electrostatic inductor of the present utility model can obtain the forward conduction characteristic of uniformity, the current capacity that acquisition is bigger, higher blocking ability, easier control on the technology, thereby production cost is lower.
Below in conjunction with the utility model example the utility model is described in detail.
Fig. 1~2nd, structural representation of the present utility model;
Fig. 3~4 are the structural representation of prior art.
The utility model is as shown in Figure 1: polysilicon directly is deposited on above the source region, and polysilicon sees through polysilicon and expands phosphorus to the source region above insulating barrier is deposited on the flute profile grid region, and the source electrode metal layer is connected with the source region by polysilicon.It below the source region P type base.Do not have the grid metal level on the flute profile grid, gate electrode is the (not shown) of drawing from the side.New construction of the present utility model like this is: in lower floor is that low resistivity layer 42 upper stratas are that the upper surface of the silicon substrate film 4 of N-type resistive formation 41 has N+ type source region 3, P type base 11 is arranged below N+ type source region 3, the upper surface of silicon substrate film 4 has many grooves 5, P+ type grid region 6 is arranged in the bottom of groove 5, lower floor's low resistivity layer 42 of silicon substrate film 4 is drain regions, and drain electrode metal level 8 is arranged below drain region 42.It is characterized in that:
1. the top and phosphorous doped polysilicon layer 9 in source region 3 is connected, and phosphorous doped polysilicon layer 9 is connected with source electrode metal layer 1;
2. the bottom surface of every groove 5 and side cover insulating barrier 10, and side insulation layer 10 extends to the upper surface of silicon substrate film 4;
3. between two P+ type grid regions 6, below the upper surface insulating barrier 10 and silicon substrate film 4 upper surface N+ type source regions 3 of silicon substrate film 4, a P type base 11 is arranged, the depth as shallow in the depth ratio P+ type grid region 6 of P type base 11.
In the new construction of the present utility model, the forward conduction characteristic of device and the range-independence in adjacent two P+ grid regions 6 mainly are subjected to the degree of depth of P type base 11 and the influence of doping content, so the forward conduction characteristic of device and photoetching process are irrelevant.In the photoetching process, the inhomogeneous of exposure intensity can not cause the inhomogeneous of forward conduction characteristic.Can adopt ion implantation technique, the degree of depth and the doping content of P type base 11 is very even everywhere to make silicon chip, thereby makes the forward conduction characteristic between the tube core of silicon chip each point very consistent.
In the new construction of the present utility model, device be to control by the degree of depth in P+ grid region 6 and the degree of depth and the doping content of P type base 11 respectively by blocking characteristics and forward conduction characteristic, can improve the blocking ability that ends of device by the degree of depth of deepening P+ grid region 6, the forward conduction ability that the degree of depth by reducing P type base 11 and doping content improve device makes can well being taken into account simultaneously by blocking ability and forward conduction ability of device.
In the new construction of the present utility model, though the forward conduction ability of device under big electric current also is subjected to the thickness effect of the upper strata resistive formation 41 of silicon substrate film 4, mainly the degree of depth and the doping content by P type base 11 determines.By reducing the thickness of P type base 11, can obtain the forward conduction ability more much bigger than existing closed type electrostatic induction device.
Below for several embodiment.
Fig. 1 realizes the utility model embodiment preferably.The lower floor drain region 42 of silicon substrate film 4 is the N+ type silicon of thickness 420 μ m resistivity 0.01 Ω cm, and upper strata 41 is the N-type silicon of thickness 60 μ m resistivity 60 Ω cm.Upper surface at silicon substrate film 4 has many parallel strip grooves 5, groove 5 wide 3-6 μ m, and the spacing of two adjacent slots 5 is 4-20 μ m, groove 5 dark 2-5 μ m.Bottom land is by the P+ type that the diffuses to form flute profile grid region 6 of boron, and the surface concentration of boron is 1E19-5E20/cm 3, junction depth 3-6 μ m.The upper surface on silicon substrate upper strata 41 injects and diffusion by the boron ion, forms P type base 11, and the surface concentration of boron is 1E17-5E18/cm in the P type base 11 3, junction depth 1-3 μ m.The upper surface on silicon substrate upper strata 41 is covered with the phosphorous doped polysilicon 9 that a layer thickness is 0.4-0.5 μ m, the insulating barrier 10 that constitutes by silicon dioxide, phosphorosilicate glass, silicon nitride or their compound across one deck between the bottom of phosphorous doped polysilicon 9 and groove 5 and the side, insulating barrier 10 extends to the upper surface of silicon substrate film, the thickness of insulating barrier 10 is 0.3-1 μ m, the upper surface on the silicon substrate upper strata 41 between adjacent two grooves 5 is high phosphorus concentration N+ type source region 3, and the surface concentration of phosphorus is up to 1-3E21/cm 3, the thickness in N+ type source region 3 is less than 1 μ m.N+ type source region 3 is by insulating barrier 10 perforates, phosphorous doped polysilicon 9 is linked to each other with the upper surface on silicon substrate upper strata 41 and by phosphorous doped polysilicon 9 phosphorous diffusion is entered that the upper surface on silicon substrate upper strata 41 forms.Source electrode 1 is that thickness is the aluminium lamination of 2-3 μ m, and drain electrode 8 is that thickness is the titanium nickel gold three-layer metal of 1-2 μ m.To withstand voltage 600 volts device, can use current density up to 500A/cm 2, can use current density to exceed 200A/cm than prior art (shown in Figure 4) 2Owing to adopted the boron ion implantation technique, the junction depth and the doping content of P type base 11 are very even, the consistency of the common-emitter current gain HFE of forward conduction is fine, deviation<± 10% of each point in the sheet, and the deviation of forward conduction common-emitter current gain HFE in sheet of existing technology can be up to 30%.
Fig. 2 realizes another embodiment preferably of the present utility model.Its particular point is that the upper strata N-resistive formation 41 of silicon substrate film is divided into two-layer, and is high by the resistivity of top one deck 411, is 60 Ω cm, and thickness is 20 μ m, hang down from 412 resistivity by following one, and be 10 Ω cm, thickness is 40 μ m.This double-deck resistive formation, the PN junction potential barrier that can suppress effectively to drain improves the anti-second breakdown ability of device, thereby has improved the reliability of long term device work in the transfer blockage effect of big electric current.
In order to improve the forward conduction ability of closed type slotted-form grid electrostatic inductor, in the structure of the present utility model, the P+ type is got in silicon substrate lower floor low resistivity layer drain region 42, like this when conducting, a large amount of holes can be arranged, and 42 past N-type high resistance areas 41 inject from the drain region, produce electricity and lead modulation, have reduced conduction voltage drop greatly, further improved current density, this structure is suitable for making turn-off thyristor GTO.

Claims (7)

1. closed type slotted-form grid electrostatic inductor, comprise that lower floor is that low resistivity layer, upper strata are silicon substrate film, source region and source electrode metal layer, base, grid region and gate electrode, drain region and the drain electrode metal level of N-type resistive formation, N+ type source region is at the upper surface of silicon substrate film, have groove on the upper surface of silicon substrate film more than one, the bottom of every groove is P+ type grid region, lower floor's low resistivity layer of silicon substrate film is the drain region, is the drain electrode metal level below the drain region, it is characterized in that:
The top connection phosphorous doped polysilicon layer in described source region, this phosphorous doped polysilicon layer is connected with the source electrode metal layer;
The bottom surface of described every groove and side cover insulating barrier, and the side insulation layer extends to the upper surface of silicon substrate film;
Between described two adjacent P+ type grid regions, below silicon substrate film upper surface insulating barrier and silicon substrate film upper surface N+ type source region, a P type base is arranged, the depth as shallow in the depth ratio P+ type grid region of P type base.
2. closed type slotted-form grid electrostatic inductor as claimed in claim 1 is characterized in that: be connected the phosphorous doped polysilicon layer on the insulating barrier of the bottom surface of described every groove, side and upper surface.
3. closed type slotted-form grid electrostatic inductor as claimed in claim 1 is characterized in that: the upper strata N-resistive formation of described silicon substrate film is divided into two-layer, leans on the resistivity of top one deck to be higher than by following one deck.
4. closed type slotted-form grid electrostatic inductor as claimed in claim 1 is characterized in that: described silicon substrate film lower floor low resistivity layer drain region is P+ type drain region.
5. closed type slotted-form grid electrostatic inductor as claimed in claim 1 is characterized in that: described silicon substrate film lower floor low resistivity layer drain region is N+ type drain region.
6. closed type slotted-form grid electrostatic inductor as claimed in claim 1 is characterized in that: the degree of depth of described groove is 2~5 microns.
7. closed type slotted-form grid electrostatic inductor as claimed in claim 1 is characterized in that: the spacing of described two adjacent slots is 4~20 microns.
CN 99208627 1999-04-26 1999-04-26 Electrostatic inductor for long lime closing type goove grating Expired - Fee Related CN2366973Y (en)

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CN 99208627 CN2366973Y (en) 1999-04-26 1999-04-26 Electrostatic inductor for long lime closing type goove grating

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499487B (en) * 2008-01-31 2011-04-13 北京山贝电子技术有限公司 Wide groove shaped polysilicon gate associated transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499487B (en) * 2008-01-31 2011-04-13 北京山贝电子技术有限公司 Wide groove shaped polysilicon gate associated transistor

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