CN2269674Y - Digital multi-channel telephone terminal - Google Patents

Abstract

The utility model relates to a half-duplex wireless communication equipment's a digital telephone terminal device. It is composed of interface circuit, codec, multiplexing/demultiplexing circuit, control signal generator, synchronous extracting circuit and power supply, but it also has waveform shaping circuit, front-end processor, comparator, and multiplexing/demultiplexing circuit in which there are PCM/speech burst converter and speech burst/PCM converter corresponding to interface circuit and PCM codec. The two parties send two burst data packets in a frame period and receive and send the data packets at different times, and the method is suitable for half-duplex wireless communication equipment; not only realizing multipath communication and meeting the use requirement, but also simplifying the equipment and saving the equipment cost.

Description

The Ditital multichannel terminal set

The utility model relates to a kind of digital telephone terminal of half-duplex wireless communication equipment.

Half-duplex wireless communication equipment does not carry out simultaneously owing to send and receive, and need not duplexer, and equipment is simple; Insulated degree requirement to transmission and receive path is low; And send, receive and to adopt same frequency, save frequency resource, but the half-duplex wireless communication machine has only a speech channel, can not satisfy the use needs.Multi-way radio communication all adopts full-duplex communication device, and it has duplexer, equipment complexity, cost height; Usually connect and compose by the interface circuit of corresponding way, PCM coder, multiplexing/the demultiplexing circuit, control-signals generator, synchronous extraction circuit and several major parts of power circuit with its supporting multiplex telephony terminating machine, in multiplexing/demultiplexing circuit not and interface circuit, PCM coder corresponding PCM/ voice bursts transducer and voice bursts/PCM transducer.The deficiencies in the prior art part mainly is: with the terminal set of existing multi-way radio communication coordinative composition of equipments, can not with the supporting use of half-duplex wireless device, bad adaptability.

The purpose of this utility model is to avoid weak point of the prior art, and a kind of Ditital multichannel terminal set product that is applicable to half-duplex wireless communication equipment is provided.

Can take following technical scheme to realize purpose.The Ditital multichannel terminal set, still by interface circuit, the PCM coder of corresponding way, multiplexing/the demultiplexing circuit, control-signals generator, several major parts of synchronous extraction circuit and power circuit connect and compose, but it also is provided with wave forming circuit, front-end processor, comparator is provided with in multiplexing/demultiplexing circuit and interface circuit, PCM coder corresponding PCM/ voice bursts transducer and voice bursts/PCM transducer.Isolate line signal and voice signal from the signal interface circuit that subscribers feeder comes, the circuit burst that line signal is directly imported multiplexed/demultiplexing circuit forms circuit, become the circuit burst bag of 32blt, each road voice signal is transformed into digital signal behind PCM coder coding separately, after the corresponding PCM/ voice bursts transducer conversion of multiplexing/demultiplexing circuit, form each road voice bursts bag of length 176blt, circuit burst bag, the prefix that each road voice bursts bag and control-signals generator take place, frame alignment word is arranged in certain sequence, non-overlapping copies in time, they are by synthetic one road signal of signal synthesis circuit, again through wave forming circuit, front-end processor output sends data flow, is sent to channel device.Receiving data stream from channel device is through front-end processor, enter comparator, comparator will receive data shaping, it is exported one the road and delivers to multiplexing/demultiplexing circuit, again be separated into line signal and Ge Lu voice signal at this receiving data stream, wherein circuit burst via line signal recovery circuitry becomes each route road signal, be sent to each interface circuit respectively, the voice bursts signal packet converts the PCM signal to through each road voice bursts/PCM transducer, be reduced into voice signal through each PCM coder and be sent to each interface circuit, reach user or switch through subscribers feeder again; Another road is delivered to synchronous extraction circuit and is transported to control-signals generator in order to produce clock and frame synchronizing signal, and control-signals generator is mainly each PCM coder and multiplexing/demultiplexing circuit provides control signal.

This machine is with a period of time, promptly an interior voice signal of frame period forms digital signal through sample quantization, coding, improves the speed of digital signal, and each road signal is lined up successively, form total duration less than half burst bag of frame period, send to the other side; The other side beams back a signal packet with spline structure in time second half section of same frame after being subjected to packets of information, be loaded with the multi-path voice information of the other side's a image duration.So just realized the exchange of frame period internal information, both sides isolate each way word signal from the burst information bag that receives, and its rate recovery is arrived original speed; Through decoding, D/A conversion, filtering reverts to the voice in the frame period again, and this mode cycle carries out, and promptly can be used for the real time communication of half-duplex wireless communication equipment, realization multi-path voice.

The relative prior art of the technical program has following advantage and effect:

1, employing both sides in a frame period transmit multi-path voice in real time to sending out the circuit structure of two burst packet, do not carry out simultaneously because of transmitting-receiving again, thereby are applicable to half-duplex wireless communication equipment.

2, with half-duplex wireless communication equipment adapted, both realized multichannel communication, satisfy to have used needs, make again equipment simple, save equipment manufacturing cost.

In conjunction with the accompanying drawings, execution mode is described in further detail the content of the technical program.

Fig. 1 is the formation block diagram of Ditital multichannel terminal set;

Fig. 2 is the electrical schematic diagram of PCM coder, PCM/ voice bursts transducer, voice bursts/PCM transducer;

Fig. 3 is that the circuit burst forms circuit, line signal restore circuit electrical schematic diagram in multiplexing/demultiplexing circuit;

Fig. 4 sends out the control-signals generator electrical schematic diagram;

Fig. 5 receives the control-signals generator electrical schematic diagram;

Fig. 6 is the wave forming circuit electrical schematic diagram;

Fig. 7 is front-end processor, comparator electrical schematic diagram;

Fig. 8 is that bit synchronization is extracted the circuit electrical schematic diagram.

To the formation block diagram of the terminal set of Ditital multichannel shown in the accompanying drawing, describe with a kind of embodiment of digital 8 road terminal sets.

Among the embodiment, interface circuit divides nearly local side and two kinds local side interfaces far away, and they all can adopt existing techniques in realizing, and its function is same as the prior art.

The PCM coder can adopt any chip of using in the existing P CM multichannel equipment to constitute.This terminating machine is by integrated circuit U ₁Constitute U with level adjusting circuit ₁Adopt 29C ₁₄The coding and decoding chip, work in short frame synchronization mode, four control signal CLKX, CLKR, FSX and FSR that the chip operate as normal needs are provided by synchronous extraction circuit and control-signals generator, wherein, CLKX, CLXR are the square wave of 1.536MH2, and FSX, FSR are the pulse in a clock cycle for the repetition rate width.Signal TXI1+, TXI1-that interface comes are through resistance R ₁, R ₂, R ₃With potentiometer W ₁The level adjusting circuit of forming enters chip; The decoded output of this chip is through resistance R ₅, R ₆With potentiometer W ₂Another level adjusting circuit of forming exports interface to by RXO1+, RXOl-.

Multiplexing and demultiplexing circuit forms circuit, line signal restore circuit by the circuit burst, and each road PCM/ voice bursts transducer, voice bursts/PCM transducer and signal synthesis circuit are formed:

Its PCM/ voice bursts transducer is mainly by integrated circuit U ₅A, U ₂B, U ₃A and U ₄B connects and composes; U ₅A is 74HCO ₇Driver is realized level conversion; U ₂B, U ₃A, U ₄B is 4517 shift registers.By U ₁The signal of DX pin output is the serial data of PCM form, and output is corresponding to 8 bit data of 1 sampled value later in each FSX pulse, and data are through U ₅Import U into after the A level conversion ₂B, it only moves into data, corresponding U in 8 clock cycle after the FSX pulse arrives ₁The output valid period.The FSX pulse period is 125 μ S, it is the sampling period, corresponding 192 CLXX clock cycle in sampling period, 4517 move into 8 bit data after, to wait for that 184 CLKX week after dates move into 8 bit data of sampling next time again, like this corresponding to 22 sampled value centralized stores of frame period 2.75ms in 176 memory cell of 4517 chipsets, the data of storage shifted out from 4517 chips in the lump in the some time of a frame, formed one road voice bursts bag, the corresponding U of throughput time ₁Data ineffective time in 184 CLKX cycles of output, thereby 4517 data move in and out mutually and do not disturb.The immigration of each road speech data and shift out unifiedly by control-signals generator control, control signal is CX ₁-CX ₈, when shifting out voice bursts information, shift out 176 data of the first via earlier, and then shift out 176 data of the second tunnel ... a circuit-switched data to the last.

Voice bursts/PCM transducer is by integrated circuit U ₃B, U ₂A, U ₄A and U ₆A connects and composes, U ₃B, U ₂A, U ₄A is 4517 shift registers, U ₆A is 4050 level shifting circuits; When voice bursts is converted to the PCM signal, RO ₇Y is the multi-path voice data flow that comparator is sent into, at CR ₁-CR ₈Under the effect of control impuls, each road voice bursts bag is moved into the 4517 shift LD groups on each road successively, every road shift register once moves into 176 bit data, under same control impuls effect, divide then and shift out for 22 times, shift out 8 bit data at every turn, wait for 184 CLKR cycles, shift out next again and organize 8 bit data, the immigration of data and shift out equally and do not disturb is mutually shifted out data through U ₆Enter U after the A level conversion ₁The DR pin, U ₁The control signal FR1 control chip of FSR pin just read in data shifting out the data valid period, 8 bit data of reading in are through U ₁Revert to original voice signal after inner decoding circuit, D/A conversion and the filtering and output to interface circuit from the PWRO+ and the PWRO-pin of this chip.

The circuit burst forms the integrated circuit U of circuit by serial connection ₇-U ₁₀Constitute, they adopt 74HC165 to incorporate into to go here and there out shift register.From the line signal of interface from lLXj (l=1,2 ..., 8, j=1,2) and terminate to U ₇-U ₁₀Respective pins, be added on the signal CS of each chip SH/LD lead end ₄Adopt into shift register each road signal is parallel simultaneously, at CLKX and CS ₃Under the signal controlling, shift out successively and form the line signal burst packets, from U ₁₀QH end export signal synthesis circuit, control signal CS to ₃, CS ₄Provide by control-signals generator with CLKX.

The line signal restore circuit is by integrated circuit U ₁₁-U ₁₈Connect and compose, U wherein ₁₁-U ₁₄Be 74HC373 drive circuit, U ₁₅-U ₁₈SI PO shift register 74HC for serial connection ₁₆₄Data by comparator output enter through the DIN end, at the valid period of the line signal that receives U ₁₅-U ₁₈At control impuls CS ₂Effect moves into the line signal that send the opposite end down, from U ₁₅The 1st pin enters, and the height of the state corresponding line signal of each register shows U at the QA-QH of each chip end ₁₁-U ₁₄Be used for line signal is latched, by CS ₁Signal controlling.Line signal is from lLRj (l=1,2 ... 8, j=1,2) end is sent to corresponding interface, CS respectively ₁And CS ₂Control impuls is provided by control-signals generator.

Signal synthesis circuit is common multiselect one multi-way switch circuit, at control-signals generator CS ₅-CS ₉Work under the control signal.Prefix, frame alignment word circuit burst and Ge Lu voice bursts wrap on the time and do not overlap mutually, can each road signal is synthetic.

Control-signals generator is by integrated circuit U ₅D-F, U ₁₉C, U ₁₉D, U ₂₀A-D, U ₂₁-U ₂₅, U ₂₆A-E, U ₂₇-U ₂₉, U ₃₀A-B connects into sends out control-signals generator and by integrated circuit U ₁₉F, U ₂₆F, U ₃₁A-B, U ₃₂-U ₃₇, U ₃₈A, U ₃₉A-F, U ₄₀A, U ₄₁, U ₄₂The receipts control-signals generator that connects into, two cover circuit constitute, and shown in accompanying drawing 4,5, they produce respectively and transmit control signal and receive control signal.Two cover circuit are driven by bit synchronization clock CLKX and the XLKR that synchronous extraction circuit produces respectively, and another control signal is a frame synchronizing signal.Now its operation principle is described with the example that is produced as that transmits control signal.Under the driving of CLKX, by U ₂₁, U ₂₃-U ₂₅Four 74HC ₁₆₃Coincidence counter is formed 4224 frequency dividers, produces 4224 addresses periodically, and the repetition period is frame period 2.7mS, U ₂₈, U ₂₉Be EPROM ₂₇ C ₆4, they export control signal according to address signal from data wire.Control signal is the data message that writes on each address among the ROM, the corresponding height of the level of control signal constantly on corresponding each DOL Data Output Line of the content of each address of ROM, cycle correspondence 4224 CLX times, i.e. 2.75mS of control signal.U ₂₈And U ₂₉Multipotency goes out 16 control signals, behind the logical circuit that U20A-D NAND gate 74HCOO forms, can obtain more signals; U ₂₂And U ₂₇Be latch 74HC ₃₇₄, be used for the control signal shaping; U ₅D-F is driver 74HCO ₇, be used for the TTL/CMOS level conversion, output signal CS ₁₀Be prefix, frame synchronizing signal, signal TD ₇Be used to control front-end processor.

Wave forming circuit, as shown in Figure 6, it is by integrated circuit U ₄₆, U ₄₇, U ₄₈A, B, U ₄₉A, B, triode Q ₈, Q ₉And high frequency transformer T ₁And peripheral components connects and composes.Its effect is that the pulse signal that the hopping edge is precipitous becomes the IJF signal that the hopping edge changes by the raised cosine rule.U ₄₆, U ₄₇Be MC ₁₄₉₆Multiplier, U ₄₈A, B, U ₄₉A is 74LS ₇₄Trigger, Q ₈, Q ₉Be 2N ₃₉₀₄Transistor.By the next D-1N data-signal of signal synthesis circuit, through U ₄₉A and U ₄₈The serial to parallel conversion circuit that B constitutes becomes the digital signal that the two paths of data rate is 768Kb/s, respectively at U ₄₆And U ₄₇In two multipliers and frequency be that the cosine wave of 768KHz multiplies each other, again with two multiplier output signals at Q ₉Addition forms required IJF signal TOUT.The cosine wave of 768KHz is by U ₄₈A, Q ₈And T ₁The circuit of forming produces.

Front-end processor is by integrated circuit U ₄₃, U ₄₅, triode Q ₁-Q ₇, capacitor C ₄-C ₇, inductance L ₁And peripheral components connects and composes; Comparator is by U ₄₄Constitute with peripheral components, as shown in Figure 7.Front-end processor is mainly finished the balance of signal, uneven conversion.Q ₉Output signal TOUT, enter U ₄₃1 pin of analog switch 4053 outputs to U from 2 pin ₄₅Video amplifier NE ₅₉₂After become balanced signal and export channel device to by Tout+ and Tout-.Receive the balanced signal of coming by channel device and input to Q from TIN+ and TIN- ₃-Q ₇Transistor 2N ₃₉₀₆Two single change-over circuit of forming is via capacitor C ₄-C ₇And inductance L ₁Behind the filter network of forming, deliver to U ₄₃Another group switch, by 13 pin output, U ₄₃The control signal TD that produces by control-signals generator of action ₇Control.2N ₃₉₀₆Transistor Q ₁, Q ₂Be the control signal level shifting circuit.From U ₄₃The received signal of 12 pin output enter LM ₃₁₉Voltage comparator U ₄₄The comparison circuit that constitutes is shaped to the pulse signal of Transistor-Transistor Logic level, exports synchronous extraction circuit and multiplexing demultiplexing circuit to from the DATA end.

Synchronous extraction circuit comprises that bit synchronization is extracted circuit and frame synchronization is extracted circuit, and frame synchronization is extracted circuit can adopt prior art, and bit synchronization is extracted circuit as shown in Figure 8, and it is by integrated circuit U ₅₁A, U ₅₂, U ₅₃, U ₅₇, transistor Q ₁₀, Q ₁₂, high frequency transformer L ₃And first phase-locked loop that connects into of peripheral components and by integrated circuit U ₅₀, U ₅₆Second phase-locked loop two parts that A, B, C, peripheral components and voltage controlled oscillator connect into are formed.U ₅₁A is 74HC ₂₂₁Monostable flipflop, U ₅₂Be 4046 phase-locked loops, U ₅₃Be 4024 counters, U ₅₇Be 4068 NAND gate, Q ₁₀, Q ₁₂Be respectively 2N ₃₉₀₆, 2N ₃₉₀₄Transistor; U ₅₀Be MC ₁₄₉₆Multiplier, U ₅₆A, B, C are operational amplifier, and voltage controlled oscillator can adopt the existing conventional circuit to constitute.It is that 2.75mS, duty ratio are 1/32 window SYNWIN that first phase-locked loop produces one-period, this window in time with received signal in the prefix part correspondence.U ₅₂VCO cycle of oscillation be 2.75/32mS, from U ₅₂The VCO vibration of 4 pin output by U ₅₃Behind the 32 frequency divider frequency divisions of forming, through U ₅₇Logical combination obtains that duty ratio is 1/32, the cycle is the window signal of 2.75mS.Q ₁₂And L ₃Form high Q frequency-selective network, to the frequency frequency-selecting of 768KHz, because the 768KHz component that contains in the prefix is the strongest, the exportable strong signal of circuit when prefix is arrived is through Q ₁₀Amplify the back and trigger U ₅₁A, U ₅₁The Q end of A is output as U ₅₂Reference signal.The bit synchronization clock CLKR that produces by voltage controlled oscillator behind two divided-frequency, from PDIN input and the receiving data stream that enters from VIN at U ₅₀Carry out phase demodulation, window SYNWIN controls U ₅₀128 clock cycle phase demodulations during prefix only, phase demodulation is exported through U ₅₆A, U ₅₆B, U ₅₆After the active low-pass filter filtering that C forms, output VCO signal is to voltage controlled oscillator, voltage controlled oscillator is produced is locked in the position of received signal with clock signal CLKR.

Power supply provides ± 12V, ± 5V and+48V voltage uses for each several part.

Present embodiment adopts 4157 shift registers to finish the accumulation of speech data, distribution, storage, multiplexing or demultiplexing simultaneously; Adopt ROM accurately to produce control signal, circuit is simple and reliable, and antijamming capability is strong; Bit synchronization circuit adopts the twin-lock ring structure, and ring produces window, control bit synchronised clock phase demodulation, only works in 1/32 time corresponding to the frame of received signal prefix time; IJF signal forming circuit, the signal shaping that adopts 1496 multiplier d type flip flops and add circuit to form changed into terminating machine and realized; Terminating machine adopts balanced cable with being connected of channel device, improves antijamming capability.Best results.

Claims (5)

1, a kind of Ditital multichannel terminal set, interface circuit, PCM coder by corresponding way, multiplexing/the demultiplexing circuit, control-signals generator, synchronous extraction circuit and power circuit connect and compose, and it is characterized in that: it also is provided with wave forming circuit, front-end processor, comparator is provided with in multiplexing/demultiplexing circuit and interface circuit, PCM coder corresponding PCM/ voice bursts transducer and voice bursts/PCM transducer; The circuit burst that interface circuit is directly imported multiplexing/demultiplexing circuit with line signal forms circuit, voice are through being transformed into digital signal after the corresponding PCM/ voice bursts transducer conversion of multiplexing/demultiplexing circuit behind the PCM coder coding, they send data flow through wave forming circuit, front-end processor output again by synthetic one road signal of signal synthesis circuit; Receiving data stream is through front-end processor, enter comparator, multiplexing/demultiplexing circuit is delivered in the output one tunnel of comparator, wherein circuit burst via line signal recovery circuitry becomes each route road signal, be sent to each interface circuit respectively, the voice bursts signal packet converts the PCM signal to through each road voice bursts/PCM transducer, be reduced into voice signal through each PCM coder and be sent to each interface circuit, another road is transported to control-signals generator through synchronous extraction circuit with bit clock and frame synchronizing signal, and control-signals generator provides control signal for each PCM coder and multiplexing/demultiplexing circuit.

2, Ditital multichannel terminal set as claimed in claim 1 is characterized in that: wave forming circuit is mainly by integrated circuit multiplier U ₄₆, U ₄₇, trigger U ₄₈A, B, U ₄₉A, B; Triode Q ₈, Q ₉And high frequency transformer T ₁Connect and compose; The D-1N data-signal is through U ₄₉A, U ₄₈String and switched circuit that B constitutes become two ways of digital signals, respectively at U ₄₆, U ₄₇In with by U ₄₈A, Q ₈, T ₁The cosine wave that circuit produces multiplies each other, and output signal is at Q ₉Addition forms the IJF signal.

3, Ditital multichannel terminal set as claimed in claim 1 is characterized in that: front-end processor is mainly by simulation of integrated circuit switch U ₄₃, video amplifier U ₄₅, triode Q ₁-Q ₇And by capacitor C ₄-C ₇, inductance L ₁The filter network of forming connects and composes; The TOUT signal enters U ₄₃1 pin, output to U from 2 pin ₄₅, transport to channel device by TOUT+ and TOUT-; Signal TIN+ that channel device comes and TIN-input Q ₁-Q ₇Two single change-over circuit of forming is through C ₄-C ₇, L ₁Behind the filter network, deliver to U ₄₃, export by 13 pin.

4, Ditital multichannel terminal set as claimed in claim 1 is characterized in that: bit synchronization is extracted circuit mainly by integrated circuit monostable flipflop U ₅₁A, phase-locked loop U ₅₂, counter U ₅₃, NAND gate U ₅₇, transistor Q ₁₀, Q ₁₂And high frequency transformer L ₃First phase-locked loop that connects into and by integrated circuit multiplier U ₅₀, operational amplifier U ₅₆Second phase-locked loop that A, B, C and voltage controlled oscillator connect into constitutes; First phase-locked loop produces the SYNWIN window, from U ₅₂The VCO of 4 pin output by U ₅₃Frequency division is through U ₅₇Get window signal behind the logical combination, through Q ₁₀Amplify the back and trigger U ₅₁A, U ₅₁The Q end output U of A ₅₂Reference signal, bit synchronization clock CLKR behind two divided-frequency, from PDIN input and the receiving data stream that enters from VIN at U ₅₀Phase demodulation, SYNWIN controls U ₅0 phase demodulation, phase demodulation is exported through U ₅₆A, U ₅₆B, U ₅₆After the active low-pass filter filtering that C forms, output VCO signal is to voltage controlled oscillator.

5, Ditital multichannel terminal set as claimed in claim 1 is characterized in that: the PCM/ voice bursts transducer in multiplexing/demultiplexing circuit is mainly by driver ic U ₅A, shift register U _2B, U ₃A and U ₄B connects and composes, and input is through U ₅Import U into after the A level conversion ₂B, U ₃A, U ₄B, the immigration of each road speech data and shifting out by control signal CX ₁-CX ₈Control; Voice bursts/PCM transducer is by integrated circuit shift register U ₃B, U ₂A, U ₄A and level translator U ₆A connects and composes; ROPY multi-path voice data flow is at CR ₁-CR ₈Under the control, each road voice bursts bag is moved into U successively ₃B, U ₂A, U ₄The A group shifts out data through U ₆The A level conversion enters U ₁The DR pin.

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