CN221507740U

CN221507740U - Pixel driving circuit and display panel

Info

Publication number: CN221507740U
Application number: CN202323207340.5U
Authority: CN
Inventors: 贵炳强; 李泽亮; 高涛
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2023-11-27
Filing date: 2023-11-27
Publication date: 2024-08-09
Anticipated expiration: 2033-11-27

Abstract

The disclosure provides a pixel driving circuit and a display panel, and belongs to the technical field of display. The pixel driving circuit includes a driving transistor for generating a driving current, a channel region of the driving transistor being made of a metal oxide semiconductor material, the driving transistor having only one of a top gate and a bottom gate. The pixel driving circuit and the display panel can change the upper and lower double-gate structures of the driving transistor in the pixel driving circuit into only one of the top gate or the bottom gate, and reduce the electron mobility of the driving transistor, thereby increasing the subthreshold swing of the driving transistor and improving the low-gray-scale image quality of the display panel.

Description

Pixel driving circuit and display panel

Technical Field

The disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit and a display panel.

Background

AMOLED (active driving organic light emitting diode), especially flexible AMOLED, has become the preferred screen material for smartphones and smartwatches. As OLED display device manufacturing technologies are gradually matured and yields are continuously increasing, OLED costs are continuously decreasing so that OLEDs may begin to be applied in more fields, such as medium and large size IT fields. However, at medium and large sizes, LTPS (low temperature polysilicon) yield decreases, resulting in still higher costs, so that the industry is gradually researching a pure Oxide TFT (metal Oxide thin film transistor) back plate as a medium and large size OLED drive back plate.

The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and therefore it may include information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of utility model

The disclosure provides a pixel driving circuit and a display panel for improving the low gray-scale image quality of an OLED.

In order to achieve the above purpose, the present disclosure adopts the following technical scheme:

according to a first aspect of the present disclosure, there is provided a pixel driving circuit provided to a display panel to drive a light emitting element, the pixel driving circuit including a driving transistor for generating a driving current, a channel region of the driving transistor being made of a metal oxide semiconductor material, the driving transistor having only one of a top gate and a bottom gate.

In one exemplary embodiment of the present disclosure, the display panel has a substrate base plate, a light shielding metal layer, an inorganic buffer layer, a first gate insulating layer, and a semiconductor layer that are sequentially stacked;

The active layer of the driving transistor is positioned on the semiconductor layer; the driving transistor is provided with a bottom gate positioned on the first gate layer;

The pixel driving circuit further comprises a storage capacitor, a first electrode plate of the storage capacitor is located on the shading metal layer of the display panel, and a second electrode plate of the storage capacitor is a bottom gate of the driving transistor.

In one exemplary embodiment of the present disclosure, the pixel driving circuit further includes at least one switching transistor, and a channel region of the switching transistor is made of a metal oxide semiconductor material.

In one exemplary embodiment of the present disclosure, the switching transistor has a top gate and a bottom gate.

In one exemplary embodiment of the present disclosure, the display panel has a substrate base plate, a light shielding metal layer, an inorganic buffer layer, a first gate insulating layer, a semiconductor layer, a second gate insulating layer, a second gate layer, a planarization layer, and a source drain metal layer, which are sequentially stacked;

The driving transistor comprises a bottom gate positioned on the first gate layer and an active layer positioned on the semiconductor layer; the active layer of the driving transistor comprises a channel region, and a first conductive region and a second conductive region which are respectively positioned at two sides of the channel region; each of the switching transistors includes a bottom gate at the first gate layer, an active layer at the semiconductor layer, and a top gate at the second gate layer; the active layer of the switching transistor comprises a channel region, and a first conductive region and a second conductive region which are respectively positioned at two sides of the channel region.

In one exemplary embodiment of the present disclosure, the switching transistor includes a first light emitting control transistor;

The first light emitting control transistor includes a bottom gate at the first gate layer, an active layer at the semiconductor layer, and a top gate at the second gate layer;

The top gate and the bottom gate of the first light emitting control transistor are used for loading a first light emitting control signal;

the first conductive region of the first light emitting control transistor is used for loading a first driving power supply voltage;

The second conductive region of the first light emitting control transistor is electrically connected with the first conductive region of the driving transistor through a conductive structure.

In one exemplary embodiment of the present disclosure, the switching transistor includes a data writing transistor for loading a data voltage and a gate reset transistor for resetting a bottom gate of the driving transistor;

The data writing transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the top gate and the bottom gate of the data writing transistor are used for loading a first scanning signal; the first conductive area of the data writing transistor is used for loading data voltage;

The grid reset transistor comprises a bottom grid positioned on the first grid layer, an active layer positioned on the semiconductor layer and a top grid positioned on the second grid layer; the bottom gate and the top gate of the gate reset transistor are used for loading a second scanning signal; the first conductive region of the gate reset transistor is used for loading a first initialization voltage;

the second conductive region of the data writing transistor, the second conductive region of the grid reset transistor and the bottom grid of the driving transistor are electrically connected through a conductive structure;

the pixel driving circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is multiplexed to be a bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is positioned on the shading metal layer.

In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is multiplexed as a bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located on the light shielding metal layer;

The switching transistor includes an electrode reset transistor for resetting the pixel electrode; the electrode reset transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the top gate and the bottom gate of the electrode reset transistor are used for loading a third scanning signal; the first conductive region of the electrode reset transistor is used for loading a second initialization voltage;

The second conductive region of the electrode reset transistor, the second electrode plate of the storage capacitor, the second conductive region of the driving transistor and the pixel electrode are electrically connected through a conductive structure.

The switching transistor comprises a threshold compensation transistor and a grid reset transistor for resetting the bottom grid of the driving transistor;

the threshold compensation transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the top gate and the bottom gate of the threshold compensation transistor are used for loading a first scanning signal; the second conductive region of the threshold compensation transistor is electrically connected with the first conductive region of the drive transistor;

The grid reset transistor comprises a bottom grid positioned on the first grid layer, an active layer positioned on the semiconductor layer and a top grid positioned on the second grid layer; the bottom gate and the top gate of the gate reset transistor are used for loading a first reset control signal; the first conductive region of the gate reset transistor is used for loading a first initialization voltage;

the bottom gate of the driving transistor, the first conductive region of the threshold compensation transistor, and the second conductive region of the gate reset transistor are electrically connected to each other through a conductive structure.

In one exemplary embodiment of the present disclosure, the switching transistor includes a threshold compensation transistor and a first light emitting control transistor;

The threshold compensation transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the top gate and the bottom gate of the threshold compensation transistor are used for loading a first scanning signal; the first conductive region of the threshold compensation transistor is electrically connected with the bottom gate of the driving transistor;

The first light emitting control transistor includes a bottom gate at the first gate layer, an active layer at the semiconductor layer, and a top gate at the second gate layer; the bottom gate and the top gate of the first light emitting control transistor are used for loading a first light emitting control signal; the first conductive region of the first light emitting control transistor is used for loading a first driving power supply voltage;

The first conductive region of the driving transistor, the second conductive region of the first light emitting control transistor, and the second conductive region of the threshold compensation transistor are electrically connected to each other through a conductive structure.

In one exemplary embodiment of the present disclosure, the switching transistor includes a data writing transistor and a second light emission control transistor;

The data writing transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the bottom gate and the top gate of the data writing transistor are used for loading a second scanning signal; the first conductive area of the data writing transistor is used for loading data voltage;

The second light-emitting control transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the bottom gate and the top gate of the second light-emitting control transistor are used for loading a first light-emitting control signal; the second conductive region of the second light-emitting control transistor is electrically connected with the pixel electrode;

the second conductive region of the driving transistor, the second conductive region of the data writing transistor and the first conductive region of the second light-emitting control transistor are electrically connected through a conductive structure.

the switching transistor includes a second light emission control transistor and an electrode reset transistor that resets the pixel electrode;

The second light-emitting control transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the bottom gate and the top gate of the second light-emitting control transistor are used for loading a first light-emitting control signal; the first conductive region of the second light-emitting control transistor is electrically connected with the second conductive region of the driving transistor;

The electrode reset transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the top gate and the bottom gate of the electrode reset transistor are used for loading a second reset control signal; the first conductive region of the electrode reset transistor is used for loading a second initialization voltage;

The second conductive region of the electrode reset transistor, the second electrode plate of the storage capacitor, the second conductive region of the second light-emitting control transistor and the pixel electrode are electrically connected through a conductive structure.

In one exemplary embodiment of the present disclosure, the pixel driving circuit includes a storage capacitor; the storage capacitor comprises a first electrode plate positioned on the first grid electrode layer and a second electrode plate positioned on the shading metal layer;

The switching transistor comprises a second light-emitting control transistor, a grid reset transistor and a data writing transistor;

The second light-emitting control transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the bottom gate and the top gate of the second light-emitting control transistor are used for loading a second light-emitting control signal;

the grid reset transistor comprises a bottom grid positioned on the first grid layer, an active layer positioned on the semiconductor layer and a top grid positioned on the second grid layer; the bottom gate and the top gate of the gate reset transistor are used for loading a second reset control signal; the first conductive region of the gate reset transistor is used for loading a first initialization voltage;

The second conductive region of the second light-emitting control transistor, the second conductive region of the gate reset transistor and the bottom gate of the driving transistor are electrically connected through a conductive structure;

The data writing transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the bottom gate and the top gate of the data writing transistor are used for loading a first scanning signal, and the first conductive area of the data writing transistor is used for loading data voltage;

the second conductive region of the data writing transistor, the first conductive region of the second light-emitting control transistor and the first electrode plate of the storage capacitor are electrically connected with each other through a conductive structure.

In one exemplary embodiment of the present disclosure, the pixel driving circuit includes an auxiliary capacitor and a storage capacitor; the auxiliary capacitor comprises a first electrode plate positioned on the first grid electrode layer and a second electrode plate positioned on the shading metal layer; the storage capacitor comprises a first electrode plate positioned on the first grid electrode layer and a second electrode plate positioned on the shading metal layer;

the switching transistor comprises a voltage stabilizing transistor, a data writing transistor and an electrode reset transistor;

The voltage stabilizing transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the bottom gate and the top gate of the voltage stabilizing transistor are used for loading a second reset control signal; the first conductive area of the voltage stabilizing transistor is used for loading a first initialization voltage;

The data writing transistor is used for responding to a first scanning signal and loading a data voltage to a first electrode plate of the storage capacitor;

The electrode reset transistor comprises a bottom gate positioned on the first gate layer, an active layer positioned on the semiconductor layer and a top gate positioned on the second gate layer; the bottom gate and the top gate of the electrode reset transistor are used for loading a first reset control signal; the first conductive region of the electrode reset transistor is used for loading a second initialization voltage;

The second electrode plate of the auxiliary capacitor, the second electrode plate of the storage capacitor and the second conductive region of the voltage stabilizing transistor are electrically connected with each other through a conductive structure.

In one exemplary embodiment of the present disclosure, the conductive structure is located at one or more of the light shielding metal layer, the first gate layer, the second gate layer, the semiconductor layer, and the source drain metal layer.

According to a second aspect of the present disclosure, there is provided a display panel including the above-described pixel driving circuit.

According to the pixel driving circuit and the display panel, the upper and lower double-gate structures of the driving transistor in the pixel driving circuit are changed into only one of the top gate or the bottom gate, so that the electron mobility of the driving transistor is reduced, SS (subthreshold swing of the thin film transistor) of the driving transistor is increased, the capability of better matching with a driving IC (driving chip) can be achieved, and the low gray-scale image quality of the OLED display panel is improved.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure.

Fig. 2 is an equivalent circuit diagram of a 5T1C pixel driving circuit in one embodiment of the present disclosure.

Fig. 3-1 is a cross-sectional view of a 5T1C pixel drive circuit in one embodiment of the present disclosure.

Fig. 3-2 is a cross-sectional view of a 5T1C pixel drive circuit in one embodiment of the present disclosure.

Fig. 4 is an equivalent circuit diagram of a 7T1C pixel driving circuit in one embodiment of the present disclosure.

Fig. 5-1 is a cross-sectional view of a 7T1C pixel drive circuit in one embodiment of the present disclosure.

Fig. 5-2 is a cross-sectional view of a 7T1C pixel drive circuit in one embodiment of the present disclosure.

Fig. 6 is an equivalent circuit diagram of a 7T2C pixel driving circuit in one embodiment of the present disclosure.

Fig. 7-1 is a cross-sectional view of a 7T2C pixel drive circuit in one embodiment of the present disclosure.

Fig. 7-2 is a cross-sectional view of a 7T2C pixel drive circuit in one embodiment of the present disclosure.

Fig. 8-1 is a cross-sectional view of a 7T2C pixel drive circuit in one embodiment of the present disclosure.

Fig. 8-2 is a cross-sectional view of a 7T2C pixel drive circuit in one embodiment of the present disclosure.

Fig. 9 is an output graph of a single gate metal oxide transistor.

The main element reference numerals in the drawings are explained as follows:

T1, a grid reset transistor; t2, electrode reset transistor; t3, driving transistor; t4, a data writing transistor; t5, a first light emitting control transistor; t6, a second light emission control transistor; t7a, a threshold compensation transistor; t7b, a voltage stabilizing transistor; CST1, storage capacitor; CST2, auxiliary capacitor; n1, a first node; n2, a second node; n3, a third node; n4, a fourth node; n5, a fifth node; an OLED, a light emitting element; VDD, first driving power supply voltage; VSS, the second driving power supply; vdata, data voltage; gate1, a first scan signal; gate2, a second scan signal; gate3, a third scan signal; EM, first light emission control signal; EM2, a second emission control signal; RST1, a first reset control signal; RST2, a second reset control signal; vinit1, first initialization voltage; vinit2, the second initialization voltage; SUB, substrate base plate; LS, shading metal layer; BUF, inorganic buffer layer; GT1, a first gate layer; GI1, a first gate insulating layer; an SCL, semiconductor layer; GI2, a second gate insulating layer; GT2, a second gate layer; PLN, planarization layer; SD, source drain metal layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

The terms "a," "an," "the" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc. The terms "first" and "second" and the like are used merely as labels, and are not intended to limit the number of their objects.

In the embodiment of the present disclosure, a transistor refers to an element including at least three terminals of a gate, a source, and a drain. The transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and a current can flow through the source, channel region, and drain. The channel region refers to a region through which current mainly flows. In the embodiment of the present disclosure, in the case of using transistors of opposite polarities, the case of a change in current direction during circuit operation, or the like, the functions of the "source" and the "drain" may be exchanged with each other, that is, the "source" and the "drain" may be exchanged with each other. In the presently disclosed embodiments, for any one transistor, one of the "source" and "drain" is referred to as a first conductive region of the transistor, and the other is referred to as a second conductive region of the transistor.

The disclosure provides a pixel driving circuit and a display panel using the same. The pixel driving circuit is disposed on the display panel to drive the light emitting element OLED to emit light, as shown in fig. 1, and includes a driving transistor T3 for generating a driving current, at least one switching transistor, a storage capacitor CST1, and the light emitting element OLED; in the present disclosure, in order to reduce leakage current, the materials of the channel regions of the driving transistor T3 and the switching transistor are both metal oxide semiconductor materials, for example, IGZO (indium gallium zinc oxide) semiconductor materials may be used.

The driving transistors of the pixel driving circuits are all metal oxide transistors, so that the pixel driving circuits in different areas of the display panel can be guaranteed to have good uniformity; the display panel of the disclosed embodiments has lower manufacturing costs compared to a display panel employing low temperature polysilicon transistor + metal oxide transistor technology (LTPO).

In one example, each transistor of the display driving circuit is a metal oxide transistor.

In one embodiment of the present disclosure, the switching transistors are all double gate transistors, i.e. each have a top gate and a bottom gate. Therefore, the subthreshold swing of the switching transistor can be reduced, and the response speed of the switching transistor is further improved. In an embodiment of the present disclosure, if a gate of a transistor is located between a channel region of the transistor and a substrate, the gate is a bottom gate of the transistor; if the gate of a transistor is located on the channel region of the transistor and on the side remote from the substrate, the gate is the top gate of the transistor.

In one embodiment of the present disclosure, the driving transistor T3 has only one of a top gate and a bottom gate, and the switching transistor has a top gate and a bottom gate.

In this embodiment, the driving transistor T3 is configured to have a single gate structure, so that the electron mobility of the driving transistor T3 can be reduced, thereby increasing SS (subthreshold swing of the thin film transistor) of the driving transistor T3, better matching the capability of the driving IC, and improving the low gray-scale image quality of the OLED display panel; the switching transistor has a double-gate structure, so that the response speed of the switching transistor can be improved, and the accurate control of the switching transistor is realized.

In one example, the drive transistor T3 has a top gate and the switch transistor has a top gate and a bottom gate.

In another example, the driving transistor T3 has a bottom gate and the switching transistor has a top gate and a bottom gate.

In the present disclosure, the driving transistor T3 and each switching transistor may be either N-type or P-type, and the present disclosure will be described below by taking an N-type transistor as an example.

In one embodiment of the present disclosure, as shown in fig. 3-1, the display panel has a substrate SUB, a light shielding metal layer LS, an inorganic buffer layer BUF, a first gate layer GT1, a first gate insulating layer GI1, a semiconductor layer SCL, a second gate insulating layer GI2, a second gate layer GT2, a planarization layer PLN, and a source drain metal layer SD, which are sequentially stacked. The material of the semiconductor layer SCL is a metal oxide semiconductor material. It will be appreciated that at least part of the area of the semiconductor layer SCL may be conductive.

In one example, the material of the first gate insulating layer GI1 is silicon oxide, for example, a dense SiOx material.

In one example, the inorganic buffer layer BUF material is a SiNx (silicon nitride) material.

In one example, the material of the second gate insulating layer GI2 is silicon oxide, for example, a dense SiOx material.

In the above example, the materials of the first gate insulating layer GI1 and the second gate insulating layer GI2 are dense SiOx materials, which can reduce diffusion of hydrogen, thereby improving performance of the metal oxide thin film transistor.

In the example of fig. 3-1, the driving transistor T3 is a bottom gate transistor; the driving transistor T3 includes a bottom gate at the first gate layer GT1 and an active layer at the semiconductor layer SCL; the active layer of the driving transistor T3 includes a channel region, and first and second conductive regions respectively located at both sides of the channel region. Each switching transistor comprises a bottom gate positioned on the first gate layer GT1, an active layer positioned on the semiconductor layer SCL and a top gate positioned on the second gate layer GT2, wherein the active layer of the switching transistor comprises a channel region, and a first conductive region and a second conductive region which are positioned on two sides of the channel region respectively.

In the example of fig. 3-2, the drive transistor T3 is a top gate transistor; the driving transistor T3 includes a top gate at the second gate layer GT2 and an active layer at the semiconductor layer SCL; the active layer of the driving transistor T3 includes a channel region, and first and second conductive regions respectively located at both sides of the channel region.

An exemplary description will be made below of a pixel driving circuit of 5T1C (shown in fig. 2) as an example.

In the example of fig. 2, the pixel driving circuit includes a gate reset transistor T1, an electrode reset transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting control transistor T5, and a storage capacitor CST1. In the pixel driving circuit, the gate reset transistor T1, the electrode reset transistor T2, the data writing transistor T4, and the first light emitting control transistor T5 are all switching transistors. One end of the Gate reset transistor T1 is used for loading the first initialization voltage Vinit1, the other end is electrically connected to the first node N1, and the control end is used for loading the second scan signal Gate2. One end of the electrode reset transistor T2 is used for loading the second initialization voltage Vinit2, the other end is electrically connected with the third node N3, and the control end is used for loading the third scan signal Gate3. One end of the driving transistor T3 is electrically connected to the second node N2, the other end is electrically connected to the third node N3, and the control end is electrically connected to the first node N1. One end of the data writing transistor T4 is used for loading the data loading voltage Vdata, the other end is electrically connected to the first node N1, and the control end is used for loading the first scan signal Gate1. One end of the first light emitting control transistor T5 is used for loading the first driving power voltage VDD, the other end is electrically connected to the second node N2, and the control end is used for loading the first light emitting control signal EM. One end of the storage capacitor CST1 is electrically connected to the first node N1, and the other end is electrically connected to the third node N3.

In one example of the pixel driving circuit, as shown in fig. 2 and 3-1 (the driving transistor T3 is a bottom gate transistor), the switching transistor includes a first light emitting control transistor T5 for turning on the first driving power supply voltage VDD. The first light emitting control transistor T5 includes a bottom gate on the first gate layer GT1, an active layer on the semiconductor layer SCL, and a top gate on the second gate layer GT 2; the top gate and the bottom gate of the first light emitting control transistor T5 are used for loading a first light emitting control signal EM; the first conductive region of the first light emitting control transistor T5 is used for loading the first driving power voltage VDD. In this embodiment, the first driving power voltage VDD is at a high level; the second conductive region of the first light emitting control transistor T5 is electrically connected to the first conductive region of the driving transistor T3 through a conductive structure to form a second node N2.

In one example of the pixel driving circuit, as shown in fig. 2 and 3-1 (the driving transistor T3 is a bottom gate transistor), the switching transistor includes a gate reset transistor T1 for resetting the bottom gate of the driving transistor T3 and a data write transistor T4 for loading the data voltage Vdata; the data writing transistor T4 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top Gate and the bottom Gate of the data writing transistor T4 are both used for loading the first scan signal Gate1, and the first conductive region of the data writing transistor T4 is used for loading the data voltage Vdata. The gate reset transistor T1 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom Gate and the top Gate of the Gate reset transistor T1 are both used for loading the second scan signal Gate2, and the first conductive region of the Gate reset transistor T1 is used for loading the first initialization voltage Vinit1. The second conductive region of the data writing transistor T4, the second conductive region of the gate reset transistor T1, and the bottom gate of the driving transistor T3 are electrically connected to each other through a conductive structure to form a first node N1.

In one example of the pixel driving circuit, as shown in fig. 2 and 3-1 (the driving transistor T3 is a bottom gate transistor), the first electrode plate of the storage capacitor CST1 is multiplexed to the bottom gate of the driving transistor T3, and the second electrode plate of the storage capacitor CST1 is located in the light shielding metal layer LS, and the first electrode plate of the storage capacitor CST1 is electrically connected to the first node N1. Thus, the thickness of the display panel can be reduced to achieve light and thin thickness.

In one example of the pixel driving circuit, as shown in fig. 2 and 3-1 (the driving transistor T3 is a bottom gate transistor), the switching transistor further includes an electrode reset transistor T2 for resetting the pixel electrode. The electrode reset transistor T2 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top Gate and the bottom Gate of the electrode reset transistor T2 are both used for loading a third scan signal Gate3, the first conductive region of the electrode reset transistor T2 is used for loading a second initialization voltage Vinit2, the second conductive region of the electrode reset transistor T2, the second electrode plate of the storage capacitor CST1, the second conductive region of the driving transistor T3, and the pixel electrode are electrically connected through a conductive structure, so as to form a third node N3, so as to realize resetting of the pixel electrode of the light emitting element OLED, and eliminate the influence of residual voltage on the light emitting element OLED.

The anode of the light emitting element OLED is electrically connected to the first conductive region of the driving transistor T3, and the cathode is connected to the second driving power source VSS voltage, specifically, the second driving power source VSS voltage is at a low level.

In another example of the pixel driving circuit, as shown in fig. 2 and 3-2 (the driving transistor T3 is a top gate transistor), the switching transistor includes a first light emitting control transistor T5 for turning on the first driving power supply voltage VDD. The first light emitting control transistor T5 includes a bottom gate on the first gate layer GT1, an active layer on the semiconductor layer SCL, and a top gate on the second gate layer GT 2; the top gate and the bottom gate of the first light emitting control transistor T5 are used for loading a first light emitting control signal EM; the first conductive region of the first light emitting control transistor T5 is used for loading the first driving power voltage VDD. In this embodiment, the first driving power voltage VDD is at a high level; the second conductive region of the first light emitting control transistor T5 is electrically connected to the first conductive region of the driving transistor T3 through a conductive structure to form a second node N2.

In another example of the pixel driving circuit, as shown in fig. 2 and 3-2 (the driving transistor T3 is a top gate transistor), the switching transistor includes a gate reset transistor T1 for resetting the top gate of the driving transistor T3 and a data write transistor T4 for loading the data voltage Vdata; the data writing transistor T4 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top Gate and the bottom Gate of the data writing transistor T4 are both used for loading the first scan signal Gate1, and the first conductive region of the data writing transistor T4 is used for loading the data voltage Vdata. The gate reset transistor T1 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom Gate and the top Gate of the Gate reset transistor T1 are both used for loading the second scan signal Gate2, and the first conductive region of the Gate reset transistor T1 is used for loading the first initialization voltage Vinit1. The second conductive region of the data writing transistor T4, the second conductive region of the gate reset transistor T1, and the top gate of the driving transistor T3 are electrically connected to each other through a conductive structure to form a first node N1.

In another example of the pixel driving circuit, as shown in fig. 2 and 3-2 (the driving transistor T3 is a top gate transistor), the second electrode plate of the storage capacitor CST1 is located on the light shielding metal layer LS, and the first electrode plate of the storage capacitor CST1 is electrically connected to the first node N1. Thus, the thickness of the display panel can be reduced to achieve light and thin thickness.

In another example of the pixel driving circuit, as shown in fig. 2 and 3-2 (the driving transistor T3 is a top gate transistor), the switching transistor further includes an electrode reset transistor T2 for resetting the pixel electrode. The electrode reset transistor T2 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top Gate and the bottom Gate of the electrode reset transistor T2 are both used for loading a third scan signal Gate3, the first conductive region of the electrode reset transistor T2 is used for loading a second initialization voltage Vinit2, the second conductive region of the electrode reset transistor T2, the second electrode plate of the storage capacitor CST1, the second conductive region of the driving transistor T3, and the pixel electrode are electrically connected through a conductive structure, so as to form a third node N3, so as to realize resetting of the pixel electrode of the light emitting element OLED, and eliminate the influence of residual voltage on the light emitting element OLED.

In the example of fig. 5-1, the driving transistor T3 is a bottom gate transistor. It will be appreciated that in other examples of the present disclosure, the drive transistor T3 may also be a top gate transistor. For example, in the example of fig. 5-2, the driving transistor T3 is a top gate transistor.

Taking a pixel driving circuit of 7T1C (as shown in fig. 4) as an example, an exemplary description will be given of the pixel driving circuit.

In the example of fig. 4, the pixel driving circuit includes a gate reset transistor T1, an electrode reset transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a threshold compensation transistor T7a, and a storage capacitor CST1. In the pixel driving circuit, the gate reset transistor T1, the electrode reset transistor T2, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the threshold compensation transistor T7a are all switching transistors. One end of the gate reset transistor T1 is used for loading the first initialization voltage Vinit1, the other end is electrically connected to the first node N1, and the control end is used for loading the first reset control signal RST1. One end of the electrode reset transistor T2 is used for loading the second initialization voltage Vinit2, the other end is electrically connected with the fourth node N4, and the control end is used for loading the second reset control signal RST2. One end of the driving transistor T3 is electrically connected to the second node N2, the other end is electrically connected to the third node N3, and the control end is electrically connected to the first node N1. One end of the data writing transistor T4 is used for loading the data loading voltage Vdata, the other end is electrically connected to the third node N3, and the control end is used for loading the second scan signal Gate2. One end of the first light emitting control transistor T5 is used for loading the first driving power voltage VDD, the other end is electrically connected to the second node N2, and the control end is used for loading the first light emitting control signal EM. One end of the second light emitting control transistor T6 is electrically connected to the third node N3, the other end is electrically connected to the fourth node N4, and the control end is used for loading the first light emitting control signal EM. One end of the threshold compensation transistor T7a is electrically connected to the second node N2, the other end is electrically connected to the first node N1, and the control end is used for loading the first scan signal Gate1. One end of the storage capacitor CST1 is electrically connected to the first node N1, and the other end is electrically connected to the fourth node N4.

In one example of the pixel driving circuit, as shown in fig. 4 and 5-1 (the driving transistor T3 is a bottom gate transistor), the switching transistor includes a gate reset transistor T1 and a threshold compensation transistor T7a for resetting the bottom gate of the driving transistor T3; the threshold compensation transistor T7a includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top Gate and the bottom Gate of the threshold compensation transistor T7a are used for loading the first scan signal Gate1, and the second conductive region of the threshold compensation transistor T7a is electrically connected to the first conductive region of the driving transistor T3. The gate reset transistor T1 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the gate reset transistor T1 are both used for loading the first reset control signal RST1, and the first conductive region of the gate reset transistor T1 is used for loading the first initialization voltage Vinit1. The first electrode plate of the storage capacitor CST1 is multiplexed as the bottom gate of the driving transistor T3, and the second electrode plate of the storage capacitor CST1 is located in the light shielding metal layer LS. The bottom gate of the driving transistor T3, the first conductive region of the threshold compensation transistor T7a, the second conductive region of the gate reset transistor T1, and the first electrode plate of the storage capacitor CST1 are electrically connected to each other through a conductive structure, forming a first node N1. The threshold voltage of the driving transistor T3 is easily compensated by the threshold compensation transistor T7 a.

In one example of the pixel driving circuit, as shown in fig. 4 and 5-1 (the driving transistor T3 is a bottom gate transistor), the switching transistor includes a threshold compensation transistor T7a and a first light emission control transistor T5; the threshold compensation transistor T7a includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top Gate and the bottom Gate of the threshold compensation transistor T7a are used for loading the first scan signal Gate1, and the second conductive region of the threshold compensation transistor T7a is electrically connected to the first conductive region of the driving transistor T3. The first light emitting control transistor T5 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the first light emitting control transistor T5 are used for loading the first light emitting control signal EM, and the first conductive region of the first light emitting control transistor T5 is used for loading the first driving power supply voltage VDD, where the driving power supply voltage is at a high level; the first conductive region of the driving transistor T3, the second conductive region of the first light emitting control transistor T5, and the second conductive region of the threshold compensation transistor T7a are electrically connected to each other through a conductive structure to form a second node N2.

In one example of the pixel driving circuit, as shown in fig. 4 and 5-1 (the driving transistor T3 is a bottom gate transistor), the switching transistor includes a data writing transistor T4 and a second light emission control transistor T6; the data writing transistor T4 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom Gate and the top Gate of the data writing transistor T4 are used for loading the second scan signal Gate2, and the first conductive region of the data writing transistor T4 is used for loading the data voltage Vdata. The second light emission control transistor T6 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the second light-emitting control transistor T6 are used for loading the first light-emitting control signal EM, and the second conductive region of the second light-emitting control transistor T6 is electrically connected to the pixel electrode. The second conductive region of the driving transistor T3, the second conductive region of the data writing transistor T4, and the first conductive region of the second light emission control transistor T6 are electrically connected through a conductive structure to form a third node N3.

In one example of the pixel driving circuit, as shown in fig. 4 and 5-1 (the driving transistor T3 is a bottom gate transistor), the switching transistor includes a second light emission control transistor T6 and an electrode reset transistor T2 for resetting the pixel electrode; the second light emission control transistor T6 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the second light-emitting control transistor T6 are used for loading the first light-emitting control signal EM, and the second conductive region of the second light-emitting control transistor T6 is electrically connected to the pixel electrode. The electrode reset transistor T2 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top gate and the bottom gate of the electrode reset transistor T2 are both used for loading the second reset control signal RST2, and the first conductive region of the electrode reset transistor T2 is used for loading the second initialization voltage Vinit2.

The first electrode plate of the storage capacitor CST1 is multiplexed as the bottom gate of the driving transistor T3, and the second electrode plate of the storage capacitor CST1 is located in the light shielding metal layer LS. The second conductive region of the electrode reset transistor T2, the second electrode plate of the storage capacitor CST1, the second conductive region of the second light-emitting control transistor T6, and the pixel electrode are electrically connected through a conductive structure, so as to form a fourth node N4, so as to reset the pixel electrode of the light-emitting element OLED, and eliminate the influence of the residual voltage on the light-emitting element OLED.

The anode of the light emitting element OLED is electrically connected to the second conductive region of the second light emission control transistor T6, and the cathode is connected to the second driving power source VSS voltage, which is, specifically, low.

In another example of the pixel driving circuit, as shown in fig. 4 and 5-2 (the driving transistor T3 is a top gate transistor), the switching transistor includes a gate reset transistor T1 and a threshold compensation transistor T7a for resetting the top gate of the driving transistor T3; the threshold compensation transistor T7a includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top Gate and the bottom Gate of the threshold compensation transistor T7a are used for loading the first scan signal Gate1, and the second conductive region of the threshold compensation transistor T7a is electrically connected to the first conductive region of the driving transistor T3. The gate reset transistor T1 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the gate reset transistor T1 are both used for loading the first reset control signal RST1, and the first conductive region of the gate reset transistor T1 is used for loading the first initialization voltage Vinit1. The second electrode plate of the storage capacitor CST1 is located in the light shielding metal layer LS. The top gate of the driving transistor T3, the first conductive region of the threshold compensation transistor T7a, the second conductive region of the gate reset transistor T1, and the second electrode plate of the storage capacitor CST1 are electrically connected to each other through a conductive structure, forming a first node N1. The threshold voltage of the driving transistor T3 is easily compensated by the threshold compensation transistor T7 a.

In another example of the pixel driving circuit, as shown in fig. 4 and 5-2 (the driving transistor T3 is a top gate transistor), the switching transistor includes a threshold compensation transistor T7a and a first light emitting control transistor T5; the threshold compensation transistor T7a includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top Gate and the bottom Gate of the threshold compensation transistor T7a are used for loading the first scan signal Gate1, and the second conductive region of the threshold compensation transistor T7a is electrically connected to the first conductive region of the driving transistor T3. The first light emitting control transistor T5 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the first light emitting control transistor T5 are used for loading the first light emitting control signal EM, and the first conductive region of the first light emitting control transistor T5 is used for loading the first driving power supply voltage VDD, where the driving power supply voltage is at a high level; the first conductive region of the driving transistor T3, the second conductive region of the first light emitting control transistor T5, and the second conductive region of the threshold compensation transistor T7a are electrically connected to each other through a conductive structure to form a second node N2.

In another example of the pixel driving circuit, as shown in fig. 4 and 5-2 (the driving transistor T3 is a top gate transistor), the switching transistor includes a data writing transistor T4 and a second light emission control transistor T6; the data writing transistor T4 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom Gate and the top Gate of the data writing transistor T4 are used for loading the second scan signal Gate2, and the first conductive region of the data writing transistor T4 is used for loading the data voltage Vdata. The second light emission control transistor T6 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the second light-emitting control transistor T6 are used for loading the first light-emitting control signal EM, and the second conductive region of the second light-emitting control transistor T6 is electrically connected to the pixel electrode. The second conductive region of the driving transistor T3, the second conductive region of the data writing transistor T4, and the first conductive region of the second light emission control transistor T6 are electrically connected through a conductive structure to form a third node N3.

In another example of the pixel driving circuit, as shown in fig. 4 and 5-2 (the driving transistor T3 is a top gate transistor), the switching transistor includes a second light emission control transistor T6 and an electrode reset transistor T2 for resetting the pixel electrode; the second light emission control transistor T6 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the second light-emitting control transistor T6 are used for loading the first light-emitting control signal EM, and the second conductive region of the second light-emitting control transistor T6 is electrically connected to the pixel electrode. The electrode reset transistor T2 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top gate and the bottom gate of the electrode reset transistor T2 are both used for loading the second reset control signal RST2, and the first conductive region of the electrode reset transistor T2 is used for loading the second initialization voltage Vinit2.

The second electrode plate of the storage capacitor CST1 is located in the light shielding metal layer LS. The second conductive region of the electrode reset transistor T2, the first electrode plate of the storage capacitor CST1, the second conductive region of the second light emission control transistor T6, and the pixel electrode are electrically connected through a conductive structure, to form a fourth node N4. The pixel electrode of the light-emitting element OLED is reset, and the influence of residual voltage on the light-emitting element OLED is eliminated.

In the examples of fig. 7-1 and 8-1, the driving transistor T3 is a bottom gate transistor. It will be appreciated that in other examples of the present disclosure, the drive transistor T3 may also be a top gate transistor. For example, in the examples of fig. 7-2 and 8-2, the driving transistor T3 is a top gate transistor.

Taking a 7T2C (as shown in fig. 6) pixel driving circuit as an example, the pixel driving circuit will be described as an example.

In the example of fig. 6, the pixel driving circuit includes a gate reset transistor T1, an electrode reset transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a voltage stabilizing transistor T7b, a storage capacitor CST1, and an auxiliary capacitor CST2. In the pixel driving circuit, the gate reset transistor T1, the electrode reset transistor T2, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the voltage stabilizing transistor T7b are all switching transistors. One end of the gate reset transistor T1 is used for loading the first initialization voltage Vinit1, the other end is electrically connected to the first node N1, and the control end is used for loading the second reset control signal RST2. One end of the electrode reset transistor T2 is used for loading the second initialization voltage Vinit2, the other end is electrically connected with the third node N3, and the control end is used for loading the first reset control signal RST1. One end of the driving transistor T3 is electrically connected to the second node N2, the other end is electrically connected to the third node N3, and the control end is electrically connected to the first node N1. One end of the data writing transistor T4 is used for loading the data loading voltage Vdata, the other end is electrically connected to the fifth node N5, and the control end is used for loading the first scan signal Gate1. One end of the first light emitting control transistor T5 is used for loading the first driving power voltage VDD, the other end is electrically connected to the second node N2, and the control end is used for loading the first light emitting control signal EM. One end of the second light emitting control transistor T6 is electrically connected to the first node N1, the other end is electrically connected to the fifth node N5, and the control end is used for loading the second light emitting control signal EM2. One end of the voltage stabilizing transistor T7b is used for loading the first initialization voltage Vinit1, the other end is electrically connected with the fourth node N4, and the control end is used for loading the second reset control signal RST2. One end of the storage capacitor CST1 is electrically connected to the fifth node N5, and the other end is electrically connected to the fourth node N4. One end of the auxiliary capacitor CST2 is electrically connected to the third node N3, and the other end is electrically connected to the fourth node N4.

In one example of the pixel driving circuit, as shown in fig. 6, 7-1 (the driving transistor T3 is a bottom gate transistor) and 8-1 (the driving transistor T3 is a bottom gate transistor), the switching transistor includes a second light emission control transistor T6, a gate reset transistor T1, and a data writing transistor T4. The second light-emitting control transistor T6 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; wherein, the bottom gate and the top gate of the second light emission control transistor T6 are used for loading the second light emission control signal EM2. The gate reset transistor T1 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the gate reset transistor T1 are both used for loading the second reset control signal RST2, and the first conductive region of the gate reset transistor T1 is used for loading the first initialization voltage Vinit1; the second conductive region of the second light-emitting control transistor T6, the second conductive region of the gate reset transistor T1, and the bottom gate of the driving transistor T3 are all electrically connected through a conductive structure, forming a first node N1.

In one example of the pixel driving circuit, as shown in fig. 6 and 8-1 (the driving transistor T3 is a bottom gate transistor), the data writing transistor T4 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom Gate and the top Gate of the data writing transistor T4 are used for loading the first scan signal Gate1, and the first conductive region of the data writing transistor T4 is used for loading the data voltage Vdata. The storage capacitor CST1 includes a first electrode plate located at the first gate layer GT1 and a second electrode plate located at the light shielding metal layer LS. The second conductive region of the data writing transistor T4, the first conductive region of the second light emission control transistor T6, and the first electrode plate of the storage capacitor CST1 are electrically connected to each other through a conductive structure, forming a fifth node N5.

In one example of the pixel driving circuit, as shown in fig. 6 (the driving transistor T3 is a bottom gate transistor), the switching transistor includes a first light emitting control transistor T5, and the first light emitting control transistor T5 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top gate and the bottom gate of the first light emitting control transistor T5 are both used for loading the first light emitting control signal EM, and the first conductive region of the first light emitting control transistor T5 is used for loading the first driving power supply voltage VDD, which in this embodiment is a high level; the second conductive region of the first light emitting control transistor T5 is electrically connected to the first conductive region of the driving transistor T3 through a conductive structure to form a second node N2.

In one example of the pixel driving circuit, as shown in fig. 6, 7-1 and 8-1 (the driving transistor T3 is a bottom gate transistor), the pixel driving circuit further includes an auxiliary capacitor CST2, the auxiliary capacitor CST2 including a first electrode plate located at the first gate layer GT1 and a second electrode plate located at the light shielding metal layer LS. The switching transistors comprise a voltage stabilizing transistor T7b, a data writing transistor T4 and an electrode reset transistor T2; the voltage stabilizing transistor T7b includes a bottom gate located at the first gate layer GT1, an active layer located at the semiconductor layer SCL, and a top gate located at the second gate layer GT 2; the bottom gate and the top gate of the voltage stabilizing transistor T7b are both used for loading the second reset control signal RST2, and the first conductive region of the voltage stabilizing transistor T7b is used for loading the first initialization voltage Vinit1.

The data writing transistor T4 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom Gate and the top Gate of the data writing transistor T4 are used for loading the first scan signal Gate1, and the first conductive region of the data writing transistor T4 is used for loading the data voltage Vdata.

The second electrode plate of the auxiliary capacitor CST2, the second electrode plate of the storage capacitor CST1, and the second conductive region of the voltage stabilizing transistor T7b are electrically connected to each other through a conductive structure, forming a fourth node N4.

In one example of the pixel driving circuit, the electrode reset transistor T2 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top gate and the bottom gate of the electrode reset transistor T2 are both used for loading the second reset control signal RST2, and the first conductive region of the electrode reset transistor T2 is used for loading the second initialization voltage Vinit2.

In one example of the pixel driving circuit, as shown in fig. 6 and fig. 8-1 (the driving transistor T3 is a bottom gate transistor), the second conductive region of the electrode reset transistor T2, the second conductive region of the driving transistor T3, the first electrode plate of the auxiliary capacitor CST2, and the pixel electrode of the light emitting element OLED are all electrically connected through a conductive structure, so as to form a third node N3, so as to reset the pixel electrode of the light emitting element OLED, and eliminate the influence of the residual voltage on the light emitting element OLED.

Note that, since the driving transistor T3 and each switching transistor are described as N-type transistors, the first conductive regions of the driving transistor T3 and each switching transistor are both sources, and the second conductive regions are drains.

In another example of the pixel driving circuit, as shown in fig. 6, 7-2 (the driving transistor T3 is a top gate transistor) and 8-2 (the driving transistor T3 is a top gate transistor), the switching transistor includes a second light emission control transistor T6, a gate reset transistor T1, and a data writing transistor T4. The second light-emitting control transistor T6 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; wherein, the bottom gate and the top gate of the second light emission control transistor T6 are used for loading the second light emission control signal EM2. The gate reset transistor T1 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom gate and the top gate of the gate reset transistor T1 are both used for loading the second reset control signal RST2, and the first conductive region of the gate reset transistor T1 is used for loading the first initialization voltage Vinit1; the second conductive region of the second light-emitting control transistor T6, the second conductive region of the gate reset transistor T1, and the top gate of the driving transistor T3 are all electrically connected through a conductive structure, forming a first node N1.

In another example of the pixel driving circuit, as shown in fig. 6 and 8-2 (the driving transistor T3 is a top gate transistor), the data writing transistor T4 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the bottom Gate and the top Gate of the data writing transistor T4 are used for loading the first scan signal Gate1, and the first conductive region of the data writing transistor T4 is used for loading the data voltage Vdata. The storage capacitor CST1 includes a first electrode plate located at the first gate layer GT1 and a second electrode plate located at the light shielding metal layer LS. The second conductive region of the data writing transistor T4, the first conductive region of the second light emission control transistor T6, and the first electrode plate of the storage capacitor CST1 are electrically connected to each other through a conductive structure, forming a fifth node N5.

In another example of the pixel driving circuit, as shown in fig. 6 (the driving transistor T3 is a top gate transistor), the switching transistor includes a first light emitting control transistor T5, and the first light emitting control transistor T5 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top gate and the bottom gate of the first light emitting control transistor T5 are both used for loading the first light emitting control signal EM, and the first conductive region of the first light emitting control transistor T5 is used for loading the first driving power supply voltage VDD, which in this embodiment is a high level; the second conductive region of the first light emitting control transistor T5 is electrically connected to the first conductive region of the driving transistor T3 through a conductive structure to form a second node N2.

In another example of the pixel driving circuit, as shown in fig. 6, 7-2, and 8-2 (the driving transistor T3 is a top gate transistor), the pixel driving circuit further includes an auxiliary capacitor CST2, the auxiliary capacitor CST2 including a first electrode plate located at the first gate layer GT1 and a second electrode plate located at the light shielding metal layer LS. The switching transistors comprise a voltage stabilizing transistor T7b, a data writing transistor T4 and an electrode reset transistor T2; the voltage stabilizing transistor T7b includes a bottom gate located at the first gate layer GT1, an active layer located at the semiconductor layer SCL, and a top gate located at the second gate layer GT 2; the bottom gate and the top gate of the voltage stabilizing transistor T7b are both used for loading the second reset control signal RST2, and the first conductive region of the voltage stabilizing transistor T7b is used for loading the first initialization voltage Vinit1.

In another example of the pixel driving circuit (the driving transistor T3 is a top gate transistor), the electrode reset transistor T2 includes a bottom gate at the first gate layer GT1, an active layer at the semiconductor layer SCL, and a top gate at the second gate layer GT 2; the top gate and the bottom gate of the electrode reset transistor T2 are both used for loading the second reset control signal RST2, and the first conductive region of the electrode reset transistor T2 is used for loading the second initialization voltage Vinit2.

In another example of the pixel driving circuit, as shown in fig. 6 and fig. 8-2 (the driving transistor T3 is a top gate transistor), the second conductive region of the electrode reset transistor T2, the second conductive region of the driving transistor T3, the first electrode plate of the auxiliary capacitor CST2, and the pixel electrode of the light emitting element OLED are all electrically connected through a conductive structure, so as to form a third node N3, so as to reset the pixel electrode of the light emitting element OLED, and eliminate the influence of the residual voltage on the light emitting element OLED.

In one embodiment of the present disclosure, the conductive structure is located in one or more of the light shielding metal layer LS, the first gate layer GT1, the second gate layer GT2, the semiconductor layer SCL, and the source drain metal layer SD, so long as the transistors are electrically connected.

In one embodiment of the present disclosure, the driving transistor T3 and each switching transistor may employ a back channel etch process (BCE); preferably, the driving transistor T3 and each switching transistor preferably use an etch barrier layer fabrication process (ESL) in order to reduce the impact on the semiconductor layer SCL during etching.

In the embodiment of the disclosure, SS of the double-gate metal oxide transistor is smaller, as shown in fig. 9, SS of the single-gate metal oxide transistor is larger than SS of the double-gate metal oxide transistor, which indicates that the switching characteristic of the single-gate metal oxide transistor is lower than that of the double-gate metal oxide transistor, so that the development of low gray scale is facilitated. For example, when the drain current of the thin film transistor is changed by one order of magnitude (10 times), the gate voltage variation corresponding to the single gate metal oxide transistor is smaller than the gate voltage variation corresponding to the double gate metal oxide transistor.

As shown in fig. 9, the drain voltage of the single gate metal oxide transistor is divided into two states: the drain voltages were 0.1V and 1V, respectively. It can be seen that the drain current at a drain voltage of 1V is larger than the drain current at a drain voltage of 0.1V at the same gate voltage, but the change in drain current is smaller; for example, when the gate voltage is 0.4V, the drain current in both states is close to 10 ^-9 a, and the drain current of the driving transistor T3 varies very slightly although the magnitude of the drain voltage spans an order of magnitude.

The disclosure further provides a display panel including the pixel driving circuit. The display panel includes: a plurality of scan lines for providing scan signals; a plurality of data lines for providing data signals; a plurality of pixel driving circuits electrically connected to the scanning lines and the data lines; at least one of the pixel driving circuits includes any of the pixel driving circuits described above in the present exemplary embodiment. The pixel driving circuit reduces the electron mobility of the driving transistor T3, so that the SS of the driving transistor T3 is increased, the capability of matching with a driving IC can be better achieved, and the low-gray-scale image quality of the OLED display panel is improved.

The display device using the display panel may include, for example, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and any other product or component having a display function.

It should be noted that although the steps of the methods of the present disclosure are illustrated in a particular order in the figures, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps must be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc., all are considered part of the present disclosure.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the disclosure. The disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined herein extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. Embodiments of the present disclosure describe the best mode known for carrying out the disclosure and will enable one skilled in the art to utilize the disclosure.

Claims

1. The pixel driving circuit is arranged on the display panel to drive the light-emitting element, and is characterized by comprising a driving transistor for generating driving current, wherein the material of a channel region of the driving transistor is a metal oxide semiconductor material, and the driving transistor only has one of a top gate and a bottom gate.

2. The pixel driving circuit according to claim 1, wherein the display panel has a substrate board, a light-shielding metal layer, an inorganic buffer layer, a first gate insulating layer, and a semiconductor layer which are stacked in this order;

3. The pixel driving circuit according to claim 1, further comprising at least one switching transistor, wherein a channel region of the switching transistor is of a metal oxide semiconductor material.

4. A pixel driving circuit according to claim 3, wherein the switching transistor has a top gate and a bottom gate.

5. The pixel driving circuit according to claim 4, wherein the display panel has a substrate, a light shielding metal layer, an inorganic buffer layer, a first gate insulating layer, a semiconductor layer, a second gate insulating layer, a second gate layer, a planarizing layer, and a source drain metal layer, which are stacked in this order;

6. The pixel driving circuit according to claim 5, wherein the switching transistor includes a first light emitting control transistor;

7. The pixel driving circuit according to claim 5, wherein the switching transistor includes a data writing transistor for loading a data voltage and a gate reset transistor for resetting a bottom gate of the driving transistor;

8. The pixel driving circuit according to claim 5, further comprising a storage capacitor, wherein a first electrode plate of the storage capacitor is multiplexed as a bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is positioned on the light shielding metal layer;

9. The pixel driving circuit according to claim 5, further comprising a storage capacitor, wherein a first electrode plate of the storage capacitor is multiplexed as a bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is positioned on the light shielding metal layer;

10. The pixel driving circuit according to claim 5, wherein the switching transistor includes a threshold compensation transistor and a first light emission control transistor;

11. The pixel driving circuit according to claim 5, wherein the switching transistor includes a data writing transistor and a second light emission control transistor;

12. The pixel driving circuit according to claim 5, further comprising a storage capacitor, wherein a first electrode plate of the storage capacitor is multiplexed as a bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is positioned on the light shielding metal layer;

13. The pixel driving circuit according to claim 5, wherein the pixel driving circuit comprises a storage capacitor; the storage capacitor comprises a first electrode plate positioned on the first grid electrode layer and a second electrode plate positioned on the shading metal layer;

14. The pixel driving circuit according to claim 5, wherein the pixel driving circuit includes an auxiliary capacitor and a storage capacitor; the auxiliary capacitor comprises a first electrode plate positioned on the first grid electrode layer and a second electrode plate positioned on the shading metal layer; the storage capacitor comprises a first electrode plate positioned on the first grid electrode layer and a second electrode plate positioned on the shading metal layer;

15. The pixel driving circuit according to any one of claims 6 to 14, wherein the conductive structure is located in one or more of the light shielding metal layer, the first gate layer, the second gate layer, the semiconductor layer, and the source drain metal layer.

16. A display panel comprising the pixel driving circuit according to any one of claims 1 to 15.