CN221379373U - Semiconductor device structure - Google Patents
Semiconductor device structure Download PDFInfo
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- CN221379373U CN221379373U CN202323090822.7U CN202323090822U CN221379373U CN 221379373 U CN221379373 U CN 221379373U CN 202323090822 U CN202323090822 U CN 202323090822U CN 221379373 U CN221379373 U CN 221379373U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229920000642 polymer Polymers 0.000 claims description 13
- 239000011810 insulating material Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000006185 dispersion Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 92
- 239000000463 material Substances 0.000 description 31
- 239000010936 titanium Substances 0.000 description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 13
- 229910052719 titanium Inorganic materials 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 238000009413 insulation Methods 0.000 description 8
- 239000010931 gold Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002077 nanosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000013047 polymeric layer Substances 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
The utility model discloses a semiconductor device structure, which comprises a substrate, a first semiconductor layer, a channel layer and a second semiconductor layer, wherein the first semiconductor layer, the channel layer and the second semiconductor layer are arranged on the substrate; the source electrode structure comprises a first electrode connected with the first semiconductor layer and at least one first arc-shaped extension part connected with the first electrode and arranged far away from the gate electrode structure, and a source electrode pad is also connected to the first arc-shaped extension part; the drain electrode structure comprises a second electrode connected with the first semiconductor layer and at least one second arc-shaped extension part connected with the second electrode and arranged far away from the gate electrode structure, and a drain electrode bonding pad is also connected on the second arc-shaped extension part. The utility model designs the source electrode structure and the drain electrode structure to comprise the first arc-shaped extension part and the second arc-shaped extension part respectively, so that the line distance between the source electrode structure and the drain electrode structure can be longer, and the current dispersion is reduced to increase the voltage resistance.
Description
Technical Field
The present utility model relates to the field of semiconductor integrated circuits, and more particularly, to a semiconductor device structure.
Background
Semiconductor devices are electronic devices that have electrical conductivity between good electrical conductors and insulators, and that utilize the specific electrical characteristics of semiconductor materials to perform specific functions, and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. The current semiconductor device mainly includes: diodes, triodes, field effect transistors, thyristors, darlington tubes, LEDs, and integrated blocks, chips, etc. containing semiconductor tubes.
For the existing semiconductor devices, such as high electron mobility transistors (High electron mobility transistor, HEMT), the three-generation half gallium nitride high electron mobility transistors developed in recent years attract a lot of attention by virtue of their good high frequency characteristics, and the high electron mobility transistors can operate at extremely high frequencies, so that they are widely used in mobile phones, satellite televisions and radars. In order to achieve better power, the requirements of high current bearing, high withstand voltage and performance improvement are met, and the important research direction is changed.
Disclosure of Invention
The utility model aims to provide a semiconductor device structure capable of bearing a large current and improving voltage resistance.
In order to achieve the above object, the present utility model provides a semiconductor device structure, comprising a substrate, a first semiconductor layer, a channel layer and a second semiconductor layer stacked on the substrate in sequence, wherein a source structure and a drain structure are arranged on the first semiconductor layer, the source structure and the drain structure are respectively arranged on two sides of the channel layer and the second semiconductor layer, and a gate structure is arranged on the second semiconductor layer; the source electrode structure comprises a first electrode connected with the first semiconductor layer and at least one first arc-shaped extension part connected with the first electrode and arranged far away from the gate electrode structure, and a source electrode pad is also connected to the first arc-shaped extension part; the drain electrode structure comprises a second electrode connected with the first semiconductor layer and at least one second arc-shaped extension part connected with the second electrode and arranged far away from the gate electrode structure, and a drain electrode bonding pad is also connected on the second arc-shaped extension part; the grid structure comprises a third electrode and a current expansion strip arranged on the third electrode, and a grid bonding pad is connected to the current expansion strip.
Preferably, the current expansion strip is in a groove shape, comprises a groove bottom and a groove wall connected with the groove bottom, the groove wall is far away from the third electrode, the groove bottom is connected with the gate pad, the gate pad is located in the middle of the groove bottom, and the upper surfaces of the source pad, the gate pad and the drain pad are located on the same plane.
Preferably, a first notch formed by the first arc-shaped extension part is arranged towards the first semiconductor layer, a first insulation supporting block is arranged in the first notch, a second notch formed by the second arc-shaped extension part is arranged towards the first semiconductor layer, a second insulation supporting block is arranged in the second notch, the first arc-shaped extension part is coated on the first insulation supporting block, and the second arc-shaped extension part is coated on the second insulation supporting block.
Preferably, the first insulating support block is circular or elliptical or semicircular, and the second insulating support block is circular or elliptical or semicircular.
Preferably, the first arc-shaped extension part is a plurality of and a plurality of the first arc-shaped extension parts are sequentially connected and are in wave-shaped arrangement, and the second arc-shaped extension part is a plurality of and a plurality of the second arc-shaped extension parts are sequentially connected and are in wave-shaped arrangement.
Preferably, the source pad is disposed on top of the first arc-shaped extension portion farthest from the gate structure, and the drain pad is disposed on top of the second arc-shaped extension portion farthest from the gate structure.
Preferably, the first insulating support block and the second insulating support block are both made of insulating materials, and the insulating materials are silicon oxide, silicon nitride or aluminum oxide.
Preferably, a buffer layer and a polymer layer are further disposed on the substrate, the first semiconductor layer is disposed on the polymer layer, an insulating protection layer is disposed on the substrate, the buffer layer, the polymer layer and the peripheral side of the first semiconductor layer, and the insulating protection layer covers the upper surface of the first semiconductor layer.
Preferably, two alignment parts are symmetrically arranged on the polymer layer, the two alignment parts are respectively positioned at two sides of the first semiconductor layer, and the upper surface of each alignment part protrudes out of the insulating protection layer.
Preferably, a waterproof layer is further disposed on the insulating protection layer, the waterproof layer is disposed above the insulating protection layer, the upper surface of the insulating protection layer exceeds the upper surfaces of the first arc-shaped extension portion and the second arc-shaped extension portion, and the upper surfaces of the source electrode bonding pad, the gate electrode bonding pad and the drain electrode bonding pad protrude out of the waterproof layer to be electrically connected with the outside.
Compared with the prior art, the source electrode structure and the drain electrode structure are respectively designed to comprise the first arc-shaped extension part and the second arc-shaped extension part, so that the line distance between the source electrode structure and the drain electrode structure can be longer, the scattered current is reduced to increase the voltage resistance, the distance from the gate electrode bonding pad to the drain electrode bonding pad can be increased to increase the reverse voltage resistance, the distance from the source electrode bonding pad to the gate electrode bonding pad can be reduced, the wire bonding distance can be kept unchanged, the tunneling resistance can be reduced, the heating is reduced, and the current is increased. In addition, the first arc-shaped extension part and the second arc-shaped extension part of the arc shape are opposite to the square structure, so that the right-angle broken line of straight line turning is avoided; the design of the current expansion strip can avoid excessive concentration of current of the grid structure, and the current on the grid bonding pad can be uniformly injected into the third electrode at the lower end through the current expansion strip, so that the switch is smooth, and the problem of electric leakage is avoided.
Drawings
Fig. 1 is a schematic view of a semiconductor device structure of the present utility model.
Fig. 2 is a schematic view of a source structure of a semiconductor device structure of the present utility model.
Fig. 3 is a schematic view of a drain structure of a semiconductor device structure of the present utility model.
Fig. 4 is a schematic diagram of a gate structure of a semiconductor device structure of the present utility model.
Fig. 5 is a schematic view of another structure of the semiconductor device according to the present utility model, in which the first insulating support block and the second insulating support block are semicircular.
Detailed Description
In order to describe the technical content, the constructional features and the effects achieved by the present utility model in detail, the following description is made with reference to the embodiments in conjunction with the accompanying drawings.
As shown in fig. 1 to 5, the present utility model provides a semiconductor device structure, which is a high electron mobility transistor (HEMT for short), but not limited thereto, the semiconductor device structure includes a substrate 1, a first semiconductor layer 4, a channel layer 5 and a second semiconductor layer 6 stacked on the substrate 1 in sequence, wherein the first semiconductor layer 4 is provided with a source structure 7 and a drain structure 8, the source structure 7 and the drain structure 8 are respectively disposed on two sides of the channel layer 5 and the second semiconductor layer 6, and the second semiconductor layer 6 is provided with a gate structure 9; the source structure 7 includes a first electrode 71, 701 connected to the first semiconductor layer 4, and at least one first arc-shaped extension 73, 703 connected to the first electrode 71, 701 and disposed away from the gate structure 9, the first arc-shaped extension 73, 703 further having a source pad 74, 704 connected thereto; the drain structure 8 comprises a second electrode 81, 801 connected to the first semiconductor layer 4 and at least one second arc-shaped extension 83, 803 connected to the second electrode 81, 801 and arranged away from the gate structure 9, the second arc-shaped extension 83, 803 being further connected to a drain pad 84, 804; the gate structure 9 includes third electrodes 91, 901, and current spreading bars 92, 902 provided on the third electrodes 91, 901, and gate pads 93, 903 are connected to the current spreading bars 92, 902.
Specifically, the material of the first semiconductor layer 4 is gallium nitride, the channel layer 5 is an Al XGa1-x N lamination, x is larger than or equal to 0.2, the material of the second semiconductor layer 6 can be gallium nitride, corresponding to a depletion type (E-mode) device, the material of the second semiconductor layer 6 can also be a high-resistance oxidation material, such as alumina (Al 2O3), corresponding to an enhancement type (D-mode) device, The first electrodes 71, 701, the second electrodes 81, 801, and the third electrodes 91, 901 are respectively a multilayer film structure based on a stack of titanium (Ti), aluminum (Al), nickel (Ni), or titanium (Ti), gold (Au), or aluminum (Al) materials in this order, wherein the film thickness of the titanium material layer is 10 nm or more and 100 nm or less, the film thickness of the aluminum material layer on the titanium material layer is 50 nm or more and 300 nm or less, the film thickness of the nickel material layer or the titanium material layer on the aluminum material layer is 10 nm or more and 50 nm or less, and the film thickness of the gold material layer or the aluminum material layer on the nickel material layer or the titanium material layer is 100 nm or more and 1000 nm or less. The first electrodes 71, 701, the second electrodes 81, 801, and the third electrodes 91, 901 are each formed by an evaporation or sputtering process. The source pad 74, 704, the drain pad 84, 804, and the gate pad 93, 903 are respectively a multilayer film structure based on a stack of titanium (Ti), aluminum (Al), nickel (Ni), or titanium (Ti), gold (Au), or aluminum (Al) materials in this order, wherein the film thickness of the titanium material layer is 10 nm or more and 100 nm or less, the film thickness of the aluminum material layer on the titanium material layer is 50 nm or more and 300 nm or less, the film thickness of the nickel material layer or the titanium material layer is 10 nm or more and 50 nm or less, and the film thickness of the gold material layer or the aluminum material layer on the nickel material layer or the titanium material layer is 0.5 μm or more and 50 μm or less. the source structure 7 and the drain structure 8 are respectively designed to include the first arc-shaped extension parts 73 and 703 and the second arc-shaped extension parts 83 and 803, so that the line distance between the source structure 7 and the drain structure 8 can be longer, the scattered current can be reduced to increase the withstand voltage, the distance between the gate pads 93 and 903 and the drain pads 84 and 804 can be increased to increase the reverse withstand voltage, the distance between the source pads 74 and 704 and the gate pads 93 and 903 can be reduced, the wire bonding distance can be kept unchanged, the tunneling resistance can be reduced, the heating can be reduced, and the current can be increased. In addition, the first arc-shaped extension parts 73, 703 and the second arc-shaped extension parts 83, 803 of the arc shape are opposite to the square structure, so that the right-angle broken line of straight line turning is avoided; The design of the current expansion strips 92 and 902 can avoid excessive concentration of the current of the gate structure 9, and the current on the gate pads 93 and 903 can be uniformly injected into the third electrodes 91 and 901 at the lower ends through the current expansion strips 92 and 902, so that the switch is smooth, and the problem of electric leakage is avoided.
In the embodiment of the present utility model, as shown in fig. 1 and 5, the current spreading bars 92, 902 are shaped like grooves, including groove bottoms 921, 9021 and groove walls 922, 9022 connected to the groove bottoms 921, 9021, the groove walls 922, 9022 being provided away from the third electrodes 91, 901, the groove bottoms 921, 9021 being connected with gate pads 93, 903, the gate pads 93, 903 being located in the middle of the groove bottoms 921, 9021, and the upper surfaces of the source pads 74, 704, the gate pads 93, 903, and the drain pads 84, 804 being on the same plane. Specifically, as shown in fig. 4, the thickness g of the groove bottom 921, 9021 is greater than or equal to 100 nm and less than or equal to 5000 nm, the width h of the groove bottom 921, 9021 is greater than or equal to 100 μm and less than or equal to 2000 μm, and the arrangement of the groove wall 922, 9022 makes the current passing through the current expansion strips 92, 902 more uniform and less prone to concentration.
In the embodiment of the present utility model, the first recess formed by the first arc-shaped extension portions 73 and 703 is disposed towards the first semiconductor layer 4, the first insulation support blocks 72 and 702 are disposed in the first recess, the second recess formed by the second arc-shaped extension portions 83 and 803 is disposed towards the first semiconductor layer 4, the second insulation support blocks 82 and 802 are disposed in the second recess, the first arc-shaped extension portions 73 and 703 are coated on the first insulation support blocks 72 and 702, and the second arc-shaped extension portions 83 and 803 are coated on the second insulation support blocks 82 and 802. Specifically, the first insulating support blocks 72, 702 are circular or elliptical or semicircular, the second insulating support blocks 82, 802 are circular or elliptical or semicircular, and the first insulating support blocks 72, 702 and the second insulating support blocks 82, 802 are made of insulating materials, and the insulating materials are silicon oxide or silicon nitride or aluminum oxide. The first insulating support blocks 72, 702 and the second insulating support blocks 82, 802 may be a plurality of uniformly spaced apart segments, for example, three first insulating support blocks 72, 702 to reduce the distance from the source pad 74, 704 to the gate pad 93, 903 and four second insulating support blocks 82, 802 to increase the distance from the gate pad 93, 903 to the drain pad 84, 804, the specific number of first insulating support blocks 72, 702 and second insulating support blocks 82, 802 being not limited and selected as desired. The width a of the first insulating support blocks 72, 702 in the horizontal direction is greater than or equal to 0.5 micron or less than or equal to 50 microns, the width d of the second insulating support blocks 82, 802 in the horizontal direction is greater than or equal to 0.5 micron or less than or equal to 50 microns, the first arc-shaped extension portions 73, 703 and the second arc-shaped extension portions 83, 803 can be formed by sputtering or vapor deposition of a desired metal on the first insulating support blocks 72, 702 and the second insulating support blocks 82, 802, and the first arc-shaped extension portions 73, 703 and the second arc-shaped extension portions 83, 803 are made of titanium, aluminum, tungsten, The thickness b of any one of the copper is 100nm or more and 5000 nm or less, the total width c of the plurality of first arc-shaped extensions 73, 703 in the horizontal direction is 100 μm or more and 2000 μm or less, the thickness e of the second arc-shaped extensions 83, 803 is 100nm or more and 5000 nm or less, and the total width f of the plurality of second arc-shaped extensions 83, 803 in the horizontal direction is 100 μm or more and 2000 μm or less. As shown in fig. 1 and 2, the first insulating support block 72 and the second insulating support block 82 may be oval, the first insulating support block 72 and the second insulating support block 82 may be nanospheres directly selected to be oval, or an insulating layer of a desired material and a desired thickness may be first deposited by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and then etched by photolithography and Inductively Coupled Plasma (ICP), as shown in fig. 5, the first insulating support block 702 and the second insulating support block 802 may be semicircular, an insulating layer of a desired material and a desired thickness may be first deposited by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, And is formed by photolithography and Inductively Coupled Plasma (ICP) etching.
In the embodiment of the present utility model, the first arc-shaped extension portions 73 and 703 are plural and the first arc-shaped extension portions 73 and 703 are sequentially connected and are arranged in a wave shape, and the second arc-shaped extension portions 83 and 803 are plural and the second arc-shaped extension portions 83 and 803 are sequentially connected and are arranged in a wave shape. Specifically, as shown in fig. 1 to 3, by providing the plurality of first arc-shaped extensions 73 and 703 and the plurality of second arc-shaped extensions 83 and 803, the line length of the source structure 7 and the drain structure 8 can be increased, and the generation of a current dispersion can be reduced, thereby increasing the withstand voltage.
In the embodiment of the present utility model, the source pads 74, 704 are disposed on top of the first arc-shaped extension portions 73, 703 farthest from the gate structure 9, and the drain pads 84, 804 are disposed on top of the second arc-shaped extension portions 83, 803 farthest from the gate structure 9. Specifically, as shown in fig. 1-3, by disposing the source pad 74, 704 on top of the first arcuate extension 73, 703 and disposing the drain pad 84, 804 on top of the second arcuate extension 83, 803 to facilitate sputtering or vapor deposition of the source pad 74, 704 and the drain pad 84, 804, implementation and material savings may be facilitated.
In the embodiment of the present utility model, as shown in fig. 1, a buffer layer 2 and a polymer layer 3 are further disposed on a substrate 1, a first semiconductor layer 4 is disposed on the polymer layer 3, an insulating protection layer 10 is disposed on the peripheral sides of the substrate 1, the buffer layer 2, the polymer layer 3 and the first semiconductor layer 4, and the insulating protection layer 10 covers the upper surface of the first semiconductor layer 4. The structure and material of the buffer layer 2 and the polymer layer 3 are common knowledge of those skilled in the art, and the insulating protection layer 10 is a composite material based on silicon oxide (SiOx), silicon nitride (SiNx), and aluminum oxide (Al 2O3) to protect the semiconductor device.
In the embodiment of the present utility model, as shown in fig. 1, two alignment parts 11 are symmetrically disposed on the polymer layer 3, the two alignment parts 11 are respectively located at two sides of the first semiconductor layer 4, and the upper surface of the alignment part 11 is protruded from the insulating protection layer 10. Specifically, the cross section of the alignment portion 11 in the vertical direction is in a trapezoid shape with a small upper part and a large lower part, the thickness of the alignment portion 11 in the vertical direction is greater than or equal to 3 micrometers and less than or equal to 100 micrometers, and the width of the alignment portion 11 in the horizontal direction is greater than or equal to 3 micrometers and less than or equal to 100 micrometers, so that the alignment portion 11 is more firmly connected with the polymeric layer 3, and the accuracy of alignment yellow light in a photolithography process is higher.
In this embodiment of the present utility model, as shown in fig. 1, a waterproof layer 12 is further disposed on the insulating protection layer 10, the waterproof layer 12 is disposed above the insulating protection layer 10, and the upper surfaces of the insulating protection layer 10 are disposed beyond the upper surfaces of the first arc-shaped extension portions 73, 703 and the second arc-shaped extension portions 83, 803, and the upper surfaces of the source pads 74, 704, the gate pads 93, 903 and the drain pads 84, 804 protrude beyond the waterproof layer 12 to be electrically connected with the outside. The waterproof layer 12 is used for preventing water vapor from invading and the cleavage defect from extending, the waterproof layer 12 can be formed by first depositing an insulating material layer with a required material and a required thickness through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and then forming the waterproof layer 12 through photoetching and Inductively Coupled Plasma (ICP) etching.
The foregoing disclosure is merely illustrative of the principles of the present utility model, and thus, it is intended that the scope of the utility model be limited thereto and not by this disclosure, but by the claims appended hereto.
Claims (10)
1. The semiconductor device structure is characterized by comprising a substrate, a first semiconductor layer, a channel layer and a second semiconductor layer which are sequentially stacked on the substrate, wherein a source electrode structure and a drain electrode structure are arranged on the first semiconductor layer, the source electrode structure and the drain electrode structure are respectively arranged on two sides of the channel layer and the second semiconductor layer, and a grid electrode structure is arranged on the second semiconductor layer;
The source electrode structure comprises a first electrode connected with the first semiconductor layer and at least one first arc-shaped extension part connected with the first electrode and arranged far away from the gate electrode structure, and a source electrode pad is also connected to the first arc-shaped extension part; the drain electrode structure comprises a second electrode connected with the first semiconductor layer and at least one second arc-shaped extension part connected with the second electrode and arranged far away from the gate electrode structure, and a drain electrode bonding pad is also connected on the second arc-shaped extension part; the grid structure comprises a third electrode and a current expansion strip arranged on the third electrode, and a grid bonding pad is connected to the current expansion strip.
2. The semiconductor device structure of claim 1, wherein the current spreading bar is in a groove shape, comprising a groove bottom and a groove wall connected with the groove bottom, the groove wall is arranged away from the third electrode, the groove bottom is connected with the gate pad, the gate pad is positioned in the middle of the groove bottom, and the upper surfaces of the source pad, the gate pad and the drain pad are positioned on the same plane.
3. The semiconductor device structure of claim 1, wherein a first recess formed by the first arcuate extension is disposed toward the first semiconductor layer, a first insulating support block is disposed within the first recess, a second recess formed by the second arcuate extension is disposed toward the first semiconductor layer, a second insulating support block is disposed within the second recess, the first arcuate extension is coated on the first insulating support block, and the second arcuate extension is coated on the second insulating support block.
4. The semiconductor device structure of claim 3, wherein the first insulating support block is circular or elliptical or semicircular and the second insulating support block is circular or elliptical or semicircular.
5. The semiconductor device structure of claim 3, wherein the first arcuate extension is a plurality of first arcuate extensions connected in sequence and arranged in a wave shape, and the second arcuate extension is a plurality of second arcuate extensions connected in sequence and arranged in a wave shape.
6. The semiconductor device structure of claim 5, wherein the source pad is disposed on top of the first arcuate extension furthest from the gate structure and the drain pad is disposed on top of the second arcuate extension furthest from the gate structure.
7. The semiconductor device structure of claim 3, wherein the first insulating support block and the second insulating support block are both made of an insulating material, and the insulating material is silicon oxide or silicon nitride or aluminum oxide.
8. The semiconductor device structure according to claim 1, wherein a buffer layer and a polymer layer are further provided on the substrate, the first semiconductor layer is provided on the polymer layer, an insulating protection layer is provided on a peripheral side of the substrate, the buffer layer, the polymer layer and the first semiconductor layer, and the insulating protection layer covers an upper surface of the first semiconductor layer.
9. The semiconductor device structure of claim 8, wherein two alignment portions are symmetrically disposed on the polymer layer, the two alignment portions are respectively disposed on two sides of the first semiconductor layer, and an upper surface of the alignment portion protrudes out of the insulating protection layer.
10. The semiconductor device structure according to claim 8, wherein a waterproof layer is further provided on the insulating protection layer, the waterproof layer is provided above the insulating protection layer, and an upper surface of the insulating protection layer is provided beyond upper surfaces of the first and second arc-shaped extensions, and upper surfaces of the source pad, the gate pad, and the drain pad protrude beyond the waterproof layer to be electrically connected with the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323090822.7U CN221379373U (en) | 2023-11-15 | 2023-11-15 | Semiconductor device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323090822.7U CN221379373U (en) | 2023-11-15 | 2023-11-15 | Semiconductor device structure |
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| Publication Number | Publication Date |
|---|---|
| CN221379373U true CN221379373U (en) | 2024-07-19 |
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| CN202323090822.7U Active CN221379373U (en) | 2023-11-15 | 2023-11-15 | Semiconductor device structure |
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| CN (1) | CN221379373U (en) |
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