CN221352767U - Display panel and display device - Google Patents

Abstract

The utility model provides a display panel and a display device. The semiconductor device comprises a substrate, a dielectric layer and a driving chip, wherein a plurality of through holes are formed in the dielectric layer, binding terminals are arranged in the through holes, and each binding terminal comprises a blocking layer, a first metal layer, an insulating layer, a passivation layer, a planarization layer and a conductive layer. The barrier layer is arranged on one side close to the substrate, and the conductive layer is arranged on one side, far away from the barrier layer, of the first metal layer. And the width of the barrier layer is larger than that of the through hole, and the barrier layer is arranged at the bottom of the signal wiring, so that the barrier layer can effectively prevent the substrate from being etched during etching, thereby better protecting the substrate and improving the quality and the comprehensive performance of the display panel.

Description

Display panel and display device

Technical Field

The present utility model relates to the field of manufacturing technologies of display panels and display devices, and in particular, to a display panel and a display device.

Background

At present, when different components in the display device are electrically connected, a plurality of different binding structures are generally adopted for binding so as to ensure the normal operation of the device.

For example, the relatively wide COG bonding process is currently used. The COG (Chip On Glass) binding process is a binding structure for directly fixing the driving chip on the substrate, thereby effectively simplifying the manufacturing process and improving the performance of the device. With the continuous improvement of the quality requirements of users, such as the common display panels and the increasingly popular electronic papers with marking function. The product can be bound and connected by adopting a COG binding process. For electronic paper products, the electronic paper products have ultra-low energy consumption and are widely applied to the display fields of electronic tags, electronic signboards, electronic readers and the like. In the prior art, the COG binding process is adopted, so that the space is saved, and the performance is improved. However, when the binding structure of the electronic paper product is formed, a plurality of binding terminals are usually arranged in the binding region, and in the process of forming the binding terminals, corresponding via hole structures are formed, when the gap for forming the binding terminals of the driving chip which is smaller and smaller is prepared through a 4mask process, glass at the bottom is easily etched when the via hole is etched, so that glass is broken, or in the subsequent process, external water vapor easily enters the display panel along the etched glass, so that the quality and performance of the product are reduced, and the further improvement of the comprehensive performance of the product is not facilitated.

In summary, in the prior art, when a display product is formed, the via hole is easily etched to the bottom of the other film layer during the preparation of the product, thereby reducing the quality and performance of the product.

Disclosure of utility model

The embodiment of the utility model provides a display panel and a display device, which are used for effectively solving the problem that the display panel is easy to be carved when being prepared and formed in the prior art, thereby reducing the quality and performance of products.

To solve the above technical problem, a first aspect of an embodiment of the present utility model provides a display panel, including a binding area, further including:

The device comprises a substrate and a dielectric layer positioned on the substrate, wherein a via hole is formed in the dielectric layer, and at least a binding terminal is arranged in the via hole; and

The driving chip is arranged on the substrate and is electrically connected with the binding terminal;

The binding terminal comprises a blocking layer arranged on one side close to the substrate, a first metal layer arranged on one side, far away from the substrate, of the blocking layer, and a conductive layer arranged on one side, far away from the blocking layer, of the first metal layer, wherein the conductive layer is electrically connected with the first metal layer through the through hole, and the width of the blocking layer is larger than that of the through hole.

According to an embodiment of the present utility model, the substrate further comprises a substrate;

The insulating layer is arranged on the substrate, the barrier layer is arranged on the substrate, and the insulating layer at least covers part of the barrier layer;

A semiconductor layer arranged on the insulating layer, wherein the semiconductor layer is correspondingly arranged in the via hole, the first metal layer is arranged on the semiconductor layer,

The passivation layer is arranged on the insulating layer;

A planarization layer disposed on the passivation layer; and

The conductive layer is disposed on the planarization layer and electrically connected to the first metal layer through the via hole.

According to an embodiment of the utility model, the thickness of the planarization layer is greater than the thickness of the passivation layer, and the height between the planarization layer and the substrate in the non-via region is greater than the height between the conductive layer and the substrate in the via region.

According to an embodiment of the present utility model, in the via region, a width of the first metal layer is smaller than or equal to a width of the semiconductor layer.

According to an embodiment of the present utility model, the via hole is configured as any one of a strip shape, a square hole, and a circular hole, and the caliber of the via hole is greater than or equal to the width of the first metal layer.

According to an embodiment of the present utility model, the binding terminal further includes a plurality of conductive particles disposed on the conductive layer.

According to an embodiment of the utility model, the conductive particles are uniformly distributed on the binding terminals.

According to an embodiment of the present utility model, the width of the barrier layer is greater than or equal to the width of the first metal layer.

According to an embodiment of the present utility model, the first metal layer is further disposed between two adjacent vias, and the two adjacent first metal layers are disposed at equal intervals.

According to a second aspect of an embodiment of the present utility model, there is also provided a display device including:

The display panel is provided in the embodiment of the utility model.

The embodiment of the utility model has the beneficial effects that: compared with the prior art, the embodiment of the utility model provides a display panel and a display device. The display panel comprises a substrate, a dielectric layer and a driving chip, wherein a via hole is formed in the dielectric layer, at least a binding terminal is arranged in the via hole, and the driving chip is electrically connected with the binding terminal. Meanwhile, the binding terminal further comprises a blocking layer, a passivation layer, a planarization layer, an insulating layer, a first metal layer and a conductive layer. The barrier layer is arranged on one side close to the substrate, and the conductive layer is arranged on one side, far away from the barrier layer, of the first metal layer. In the embodiment of the utility model, the width of the barrier layer is larger than that of the via hole, and the barrier layer is arranged at the bottom of the binding terminal, so that the barrier layer can effectively prevent the substrate from being etched when the via hole structure is formed by etching, thereby better protecting the substrate, and simultaneously, the binding effect of the binding terminal can be effectively improved, and further, the quality and the comprehensive performance of the display panel are improved.

Drawings

In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a simplified schematic diagram of a display device according to an embodiment of the present utility model;

fig. 2 is a schematic structural diagram of the binding terminal in the corresponding area provided in the embodiment of the present utility model;

FIG. 3A is a schematic diagram of a film structure of the binding structure according to an embodiment of the present utility model;

FIG. 3B is a diagram illustrating another binding structure provided in an embodiment of the present application;

Fig. 4 is a schematic diagram of another binding structure according to an embodiment of the present utility model.

Detailed Description

In the following detailed description, certain embodiments of the utility model are shown and described, simply by way of illustration. As will be appreciated by those skilled in the art, the embodiments described herein may be modified in numerous ways without departing from the spirit or scope of the present utility model.

In the drawings, the thickness of layers, films, plates, regions, etc. may be exaggerated for clarity and for better understanding and ease of description. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

In addition, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of other elements. Further, in the specification, the word "on … …" means placed above or below the subject portion, and does not necessarily mean placed on the upper side of the subject portion based on the direction of gravity.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

It will be understood that when a layer, region or element is referred to as being "formed on" another layer, region or element, it can be directly or indirectly formed on the other layer, region or element. For example, intervening layers, regions, or components may be present.

In the following examples, the x-axis, y-axis, and z-axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

When forming a binding structure inside an electronic product, such as a COG binding structure for forming a product such as a display panel or electronic paper, a plurality of binding terminals are usually disposed in a binding area, and a via hole is etched at a corresponding position, so as to form a specific binding connection structure. However, in the prior art, during etching, the problem of over-etching easily occurs, and then the substrate at the bottom is etched, so that the problems of water vapor invasion and other film cracking easily occur, the product quality is reduced, and the further improvement of the comprehensive performance of the device is not facilitated.

In the embodiment of the utility model, a display panel and a corresponding display device are provided so as to effectively improve the binding effect of products and effectively improve the comprehensive performance of devices. In the following embodiments, the display panel is illustrated by taking a display panel with a COG binding structure as an example, and optionally, in an actual product, the binding structure may be applied to other types of panels according to requirements, which is not described herein again.

As shown in fig. 1, fig. 1 is a simplified schematic structure of a display device according to an embodiment of the utility model. In an embodiment of the present utility model, when the device is configured as a displayable product, the display device may include a display panel 101, and a printed circuit board 103. In which it includes a display area 10 and a binding area 11 provided at one side of the display area. The binding area 11 may be disposed near an edge side of the display panel.

Meanwhile, in the binding region 11, a COG binding structure is also provided. Specifically, the COG binding structure includes a driving circuit and a plurality of driving chips 104. The driving chip 104 is directly arranged on the substrate corresponding to the binding structure, and the driving chip 104 is electrically connected with the driving circuit, so that the transmission of control signals is realized. In the embodiment of the present utility model, since the driving circuit is disposed in the substrate, the driving circuit is not specifically illustrated in fig. 1. The driving circuit realizes signal transmission through a plurality of signal wires.

Further, the driving circuit further includes a plurality of signal traces, and in particular, the signal traces may be a plurality of bonding terminals 102. Binding and electrical connection between the display panel and the printed circuit board 103 are realized through the binding terminal 102, and transmission of control signals is realized. See the binding structure in fig. 1 for details.

In the embodiment of the utility model, when the binding structure is arranged, the problem that overetching is easy to occur in the process of etching to form the binding terminal is effectively avoided in order to improve the binding effect. Fig. 2 is a schematic structural diagram of the binding terminal corresponding area according to the embodiment of the present utility model, as shown in fig. 2.

In connection with the structure in fig. 1, in the embodiment of the present utility model, when describing the above binding structure, it may correspond to an electronic paper product prepared in the prior art. And the electronic paper product is prepared by adopting a 4-photomask (mask) etching process.

In the bonding structure, the signal traces in the bonding region are illustrated as bonding terminals 102. Specifically, the plurality of spaced binding terminals 102 are arranged at intervals, each binding terminal 102 may be parallel to each other, the gaps between two adjacent binding terminals are the same, and meanwhile, the width and the length of each binding terminal 102 may be the same.

Furthermore, the binding structure further comprises a dielectric layer positioned on the substrate, wherein the dielectric layer mainly plays a role of an insulating layer, and meanwhile, a via 203 is correspondingly arranged on the dielectric layer, and at least a signal wiring, namely a binding terminal in the embodiment of the utility model is arranged in the via 203. And a barrier layer 205, a first metal layer 204, a conductive layer 202, a via 203, and a semiconductor layer 201, which are respectively disposed on different layers. Specifically, when the binding structure is formed, the barrier layer, the first metal layer, the conductive layer, the semiconductor layer and the via hole are correspondingly arranged, the conductive layer 202 is arranged at the outermost side, the barrier layer 205 is arranged at the bottom of the binding terminal, and the conductive layer 202 is electrically connected with the first metal layer 204 through the via hole, so that the different metal layers form the signal routing in the region in the embodiment of the utility model, and the binding effect of the binding terminal in the binding region is ensured. In the embodiment of the present utility model, when the plurality of binding terminals 102 are disposed, the via holes 203 may be disposed at intervals, for example, no via hole is disposed on one first metal layer 204 between two via holes 203, that is, the first metal layer 204 is disposed between two adjacent via holes 203, and the two adjacent first metal layers 204 are disposed at equal intervals, so as to form the binding structure provided in the embodiment of the present utility model. Alternatively, the via 203 may be correspondingly disposed on each first metal layer 204 according to needs, which will not be described herein. In the embodiment of the present utility model, when the above-mentioned different film structures are provided, by providing the barrier layer 205 at the bottom of the film layer binding the terminal, and the width of the barrier layer 205 is greater than the width of the via 203, optionally, the barrier layer 205 is made of a metal material, so that when the via 203 is formed by etching, the barrier layer 205 at the bottom can protect the underlying film layer, thereby avoiding the over etching problem and ensuring the quality thereof.

As shown in fig. 3A-3B, fig. 3A is a schematic diagram of a film layer structure of the binding structure provided in the embodiment of the present utility model, and fig. 3B is a schematic diagram of another binding structure provided in the embodiment of the present utility model. In connection with the binding plan view of fig. 2.

In the embodiment of the utility model, when the binding structure is set, the binding structure further comprises a substrate. The substrate 200 may be a glass substrate, so that the substrate 200 has better flatness and supporting effect. Meanwhile, the substrate further includes an insulating layer 207, a passivation layer 208, and a planarization layer 206.

Specifically, in providing the different film layers, the insulating layer 207 is disposed on the substrate 200, and at the same time, the barrier layer 205 is disposed on the substrate 200, and the insulating layer 207 may cover a portion of the barrier layer 205. As in the region of the via 203, the insulating layer 207 covers a portion of the barrier layer 205, thereby preventing the barrier layer 205 in that region from interfering with other layers.

Further, the passivation layer 208 is disposed on the insulating layer 207, and the semiconductor layer 201 is disposed on the passivation layer 208 in the region of the via 203, and in the embodiment of the present utility model, the material of the semiconductor layer 201 may be a-si material, so as to realize signal transmission.

Further, the planarization layer 206 is disposed on the passivation layer 208, and the thickness of the planarization layer 206 is greater than the thickness of the passivation layer 208, while the height between the planarization layer and the substrate in the non-via region is greater than the height between the conductive layer and the substrate in the via region. In order to ensure the leveling effect of the planarization layer 206, it is configured as a copolymer of tetrafluoroethylene, an optical adhesive layer or other resin material with leveling effect, specifically, may be selected according to different products, and will not be described herein.

Referring to fig. 3B in detail, in this embodiment, in the region of the via 203, the first metal layer 204 is disposed directly on the semiconductor layer 201. The conductive layer 202 is disposed on the planarization layer 206, and when the via 203 is etched, the insulating layer over the blocking layer 205 can be directly etched away in the region when the via is etched deeper, and at this time, the conductive layer 202 is electrically connected to the first metal layer 204 or a portion of the blocking layer 205 in the region of the via 203. Meanwhile, in the corresponding etched grooves 209 on both sides of the via 203, the barrier layer 205 is partially exposed and electrically connected to the conductive layer 202.

Referring to fig. 3A, in the embodiment of the present utility model, in the region of the via 203, the passivation layer 208 and the planarization layer 206 are completely etched away by the via 203, and during etching, only a portion of the insulating layer 207 may be etched away by the via 203, and an etched recess 209 is formed above the insulating layer 207, wherein the bottom of the etched recess 209 is not in contact with the surface of the barrier layer 205.

In the embodiment of the present utility model, since the barrier layer 205 is disposed on the substrate 200 corresponding to the bonding structure in the region of the via 203, when etching is performed, a portion of the insulating layer 207 will be etched, and when etching is performed downwards, even if the etching amount is large, the etching is still blocked by the barrier layer 205 at the bottom, thereby preventing etching of the glass substrate 200 during etching.

Further, in preparing the bonding terminal in forming the above bonding structure, the width of the first metal layer 204 may be smaller than or equal to the width of the semiconductor layer 201 in the region of the via 203, so as to ensure the contact effect between two different film layers.

Meanwhile, in combination with the structure of fig. 2, in an embodiment of the present utility model, the via 203 may be configured as a strip structure. Optionally, when the binding structure is applied to other structures, the binding structure may be further configured to have other shapes, for example, the via 203 may be further configured to have a square shape, a round shape, or other shapes, and the specific configuration may be set according to the requirements of different products, which will not be described herein.

The caliber or width of the via 203 is greater than or equal to the width of the first metal layer 204, and when the via 203 is arranged in a strip shape, the length of the via 203 is smaller than the length of the first metal layer 204, so as to ensure the electrical connection effect of the binding terminal. In order to simplify the manufacturing process, the film layer in the region of the via 203 may be symmetrically disposed with respect to the central axis of the via 203 during the arrangement, so as to ensure the consistency of different regions.

Further, to prevent the via 203 from being etched onto the bottom glass substrate 200, the width of the barrier layer 205 may be greater than or equal to the width of the via 203, and at the same time, the width of the barrier layer 205 may be greater than the width of the first metal layer 204, and the width of the barrier layer 205 may be greater than the width of the semiconductor layer 201, so as to effectively protect the underlying substrate.

Further, each of the metal layers may be made of a metal material with good electrical conductivity, such as the barrier layer 205, the first metal layer 204 may be made of any one of Cu, al, mo, or other metal materials.

Meanwhile, the thicknesses of the barrier layer and the first metal layer can be set to be the same, or the thickness of the barrier layer is larger than that of the first metal layer, so that the binding structure still has good binding quality and effect under the condition of ensuring that the binding structure is as light and thin as possible. In the embodiment of the present utility model, the conductive layer 202 may be an indium tin oxide film layer, so as to ensure the transmission effect.

In the embodiment of the present utility model, the conductive layer 202 is further electrically connected to the first metal layer 204, a portion of the barrier layer 205, and a portion of the semiconductor layer 201 in the region of the via 203. Meanwhile, in order to ensure the connection effect, the width of the first metal layer 204 may be smaller than the width of the semiconductor layer 201, so that the first metal layer and the semiconductor layer 201 form a step, which is shown in detail in the structure of the left side of the first metal layer in the via 203 in fig. 3, and the step can effectively increase the bonding area of the conductive layer 202, thereby further increasing the connection effect.

As shown in fig. 4, fig. 4 is a schematic diagram of another binding structure according to an embodiment of the present utility model. In connection with the structure in fig. 3, in an embodiment of the present utility model, the binding terminal further includes a plurality of conductive particles 301. When the conductive particles 301 are disposed, the distribution density of the conductive particles 301 in the region of the via 203 may be greater than the distribution density at the non-via region. Meanwhile, the conductive particles 301 may be any particles having a conductive effect. Optionally, the conductive particles may also be anisotropic conductive films.

By arranging the conductive particles 301 and embossing them, a part of the conductive particles 301 penetrate through the conductive layer 202 of the binding terminal, and optionally, the conductive particles 301 are uniformly distributed on the binding terminal, so that the effect of electrical connection between the conductive layer 202 and other film layers is increased by arranging the conductive particles 301.

Further, the conductive particles 301 may be disposed according to the requirement, and optionally, the conductive particles 301 are uniformly disposed above the first metal layer 204, so as to effectively ensure the connection effect between the first metal layer 204 and the conductive layer 202.

In the embodiment of the utility model, the at least one barrier layer is arranged at the position corresponding to the via hole, and the width of the barrier layer is larger than the width of the via hole and the width of the first metal, so that when etching is performed, the barrier layer can effectively protect other film layers and etch the substrate in a mode, thereby preventing external water vapor from entering the device, and effectively improving the binding quality and effect of the binding structure.

In the embodiment of the utility model, the display panel and the corresponding display device can be any product or component with display function or touch function, such as a mobile phone, a computer, electronic paper, a display, a wearable device, and the like, and the specific type of the product or component is not particularly limited.

In summary, the display panel and the display device provided by the embodiments of the present utility model have been described in detail, and specific examples are applied to illustrate the principles and the embodiments of the present utility model, and the description of the above embodiments is only for helping to understand the technical solution and the core idea of the present utility model; although the present utility model has been described with reference to the preferred embodiments, it should be understood that the utility model is not limited to the particular embodiments described, but can be modified and altered by persons skilled in the art without departing from the spirit and scope of the utility model.

Claims (10)

1. A display panel comprising a binding area, comprising:

The device comprises a substrate and a dielectric layer positioned on the substrate, wherein a via hole is formed in the dielectric layer, and a binding terminal is arranged in the via hole; and

The driving chip is arranged on the substrate and is electrically connected with the binding terminal;

The binding terminal comprises a blocking layer arranged on one side close to the substrate, a first metal layer arranged on one side, far away from the substrate, of the blocking layer, and a conductive layer arranged on one side, far away from the blocking layer, of the first metal layer, wherein the conductive layer is electrically connected with the first metal layer through the through hole, and the width of the blocking layer is larger than that of the through hole.

2. The display panel of claim 1, wherein the substrate further comprises a substrate;

The insulating layer is arranged on the substrate, the barrier layer is arranged on the substrate, and the insulating layer at least covers part of the barrier layer;

A semiconductor layer arranged on the insulating layer, wherein the semiconductor layer is correspondingly arranged in the via hole, the first metal layer is arranged on the semiconductor layer,

The passivation layer is arranged on the insulating layer;

A planarization layer disposed on the passivation layer; and

The conductive layer is disposed on the planarization layer and electrically connected to the first metal layer through the via hole.

3. The display panel of claim 2, wherein a thickness of the planarization layer is greater than a thickness of the passivation layer, and a height between the planarization layer and the substrate in a non-via region is greater than a height between the conductive layer and the substrate in the via region.

4. The display panel of claim 2, wherein a width of the first metal layer is less than or equal to a width of the semiconductor layer within the via.

5. The display panel according to claim 1, wherein the via hole is formed in any one of a long-strip shape, a square hole, and a circular hole, and the aperture of the via hole is greater than or equal to the width of the first metal layer.

6. The display panel of claim 1, wherein the bonding terminal further comprises a plurality of conductive particles disposed on the conductive layer.

7. The display panel of claim 6, wherein the conductive particles are uniformly distributed on the bonding terminals.

8. The display panel according to claim 1, wherein the first metal layer is further disposed between two adjacent vias, and the two adjacent first metal layers are disposed at equal intervals.

9. The display panel of claim 1, wherein a width of the barrier layer is greater than or equal to a width of the first metal layer.

10. A display device, comprising:

A display panel as claimed in any one of claims 1 to 9.