CN221202531U - Pulse signal edge selection circuit and control circuit - Google Patents

Abstract

The application discloses a pulse signal edge selection circuit and a control circuit, comprising: a metal oxide semiconductor field effect transistor MOS, a first resistor, a second resistor and a third resistor; the first end of the second resistor is used for being connected with a pulse signal source; the second end of the second resistor is grounded through a third resistor; the second end of the second resistor is connected with the grid electrode of the MOS tube; the source electrode of the MOS tube is used for grounding; the drain electrode of the MOS tube is connected with the first end of the first resistor; the second end of the first resistor is used for being connected with a pulse signal source; the drain electrode of the MOS tube is used for being connected with a receiving pin of the control chip. And the parasitic capacitance is charged due to the fact that the gate-source voltage of the MOS tube rises to the conduction threshold value. Before the MOS tube is conducted, the pulse signal edge selection circuit outputs a high level, and after the MOS tube is conducted, the pulse signal edge selection circuit outputs a low level; edge selection is achieved and pulse time can be controlled.

Description

Pulse signal edge selection circuit and control circuit

Technical Field

The application relates to the technical field of electronics, in particular to a pulse signal edge selection circuit and a control circuit.

Background

In the control circuit, an external pulse signal is usually input to a pin of the control chip to trigger a corresponding function of the control chip, for example, the input of the pulse signal to an enable end of the control chip can wake up the control chip. The detection of the pulse signal is generally realized by adopting the rising edge or the falling edge of the pulse signal, and some control chips can even adopt the function of triggering both the rising edge and the falling edge of the pulse signal, namely that both the double edges are effective.

In practical circuit designs, it is sometimes desirable to only activate the rising or falling edge single trigger mode of the pulse signal for a control chip that is active on both edges of the pulse, i.e., either the rising or falling edge trigger is selected. But there is no way to make the settings in terms of software; nor does the related art in hardware implement a circuit for pulse edge selection.

Disclosure of utility model

In view of the above, the present application provides a pulse signal edge selection circuit and a control circuit, which can implement single edge triggering of a pulse signal.

The application provides a pulse signal edge selection circuit, which comprises: a metal oxide semiconductor field effect transistor MOS, a first resistor, a second resistor and a third resistor;

the first end of the second resistor is used for being connected with a pulse signal source; the second end of the second resistor is grounded through the third resistor;

The second end of the second resistor is connected with the grid electrode of the MOS tube;

The source electrode of the MOS tube is used for grounding; the drain electrode of the MOS tube is connected with the first end of the first resistor; the second end of the first resistor is used for being connected with the pulse signal source;

and the drain electrode of the MOS tube is used for being connected with a receiving pin of the control chip.

Preferably, the method further comprises: a charging capacitor;

The charging capacitor is connected in parallel between the grid electrode of the MOS tube and the source electrode of the MOS tube.

Preferably, the method further comprises: a digital processing circuit;

The input end of the digital processing circuit is connected with the drain electrode of the MOS tube; and the output end of the digital processing circuit is used for being connected with a receiving pin of the control chip.

Preferably, the digital processing circuit is specifically an and logic chip;

The first input end of the AND logic chip is used for being connected with a power supply;

The second input end of the AND logic chip is connected with the drain electrode of the MOS tube;

and the output end of the AND logic chip is used for being connected with a receiving pin of the control chip.

Preferably, the method further comprises: a fourth resistor;

and two ends of the fourth resistor are respectively connected with a source electrode and a drain electrode of the MOS tube.

Preferably, the method further comprises: a filter capacitor;

The filter capacitor is connected in parallel with two ends of the fourth resistor.

Preferably, the method further comprises: an inverting converter;

The first input end of the inverting converter is used for being connected with the pulse signal source; the output end of the inverting converter is connected with the second end of the first resistor.

Preferably, the inverting converter is specifically a nand logic chip;

The first input end of the NAND logic chip is used for being connected with the pulse signal source;

the second input end of the NAND logic chip is used for connecting a power supply;

And the output end of the NAND logic chip is connected with the second end of the first resistor.

Preferably, the resistance value of the second resistor is equal to the resistance value of the third resistor.

The present application also provides a control circuit comprising: the pulse signal source, the control chip and the pulse signal edge selection circuit are described above;

The pulse signal source is connected with a receiving pin of the control chip through the pulse signal edge selection circuit.

From this, the application has the following beneficial effects:

The pulse signal edge selection circuit provided by the application comprises: the MOS transistor, the first resistor, the second resistor and the third resistor; the first end of the second resistor is used for being connected with a pulse signal source; the second end of the second resistor is grounded through a third resistor; the second end of the second resistor is connected with the grid electrode of the MOS tube; the source electrode of the MOS tube is used for grounding; the drain electrode of the MOS tube is connected with the first end of the first resistor; the second end of the first resistor is used for being connected with a pulse signal source; the drain electrode of the MOS tube is used for being connected with a receiving pin of the control chip. The process of raising the gate-source voltage of the MOS tube to the conduction threshold is a process of charging the parasitic capacitance, so that the MOS tube has a certain conduction time. Before the MOS tube is conducted, the pulse signal edge selection circuit outputs a high level, and after the MOS tube is conducted, the pulse signal edge selection circuit outputs a low level; the on time of the MOS tube is determined by the second resistor, the third resistor and the parasitic capacitance, so that edge selection can be realized, and pulse time can be controlled.

Drawings

Fig. 1 is a schematic diagram of a pulse signal edge selection circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another pulse signal edge selection circuit according to an embodiment of the present application;

fig. 3 is a circuit diagram corresponding to simulation of a pulse signal edge selection circuit according to an embodiment of the present application;

Fig. 4 is a simulation effect diagram of a pulse signal edge selection circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of an edge selection circuit of a pulse signal according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an analog pulse signal source of a pulse signal edge selection circuit according to another embodiment of the present application;

Fig. 7 is a circuit diagram corresponding to simulation of a pulse signal edge selection circuit according to an embodiment of the present application;

FIG. 8 is a diagram showing the simulation effect of the falling edge of the pulse signal edge selection circuit according to the embodiment of the present application;

fig. 9 is a schematic diagram of a control circuit according to an embodiment of the present application.

Detailed Description

In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of embodiments of the application will be rendered by reference to the appended drawings and appended drawings.

The application realizes the edge selection of pulse signals by utilizing the on time of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and a circuit formed by a resistor and an MOS tube.

Referring to fig. 1, a schematic diagram of a pulse signal edge selection circuit according to an embodiment of the application is shown.

The pulse signal edge selection circuit provided by the embodiment of the application comprises: MOS pipe Q1, first resistance R1, second resistance R2 and third resistance R3.

The embodiment of the application is not particularly limited to the type of the MOS transistor Q1, and for convenience of understanding, the embodiment of the application is described by taking the N-channel MOS transistor Q1 as an example, namely Q1 described below is an NMOS transistor.

The first end of the second resistor R2 is used for connecting the pulse signal source 200; the second end of the second resistor R2 is grounded through a third resistor R3; the second end of the second resistor R2 is connected with the grid electrode of the MOS tube Q1.

The source electrode of the MOS tube Q1 is used for grounding; the drain electrode of the MOS tube Q1 is connected with the first end of the first resistor R1. The second end of the first resistor R1 is connected to the pulse signal source 200.

The drain electrode of the MOS transistor Q1 is used for connecting with a receiving pin of the control chip 100.

Under the connection relationship, when the pulse signal source 200 inputs a high-level signal, before the MOS transistor Q1 is turned on, the drain electrode of the MOS transistor Q1 is directly connected with the pulse signal source 200, and the drain electrode of the MOS transistor Q1 is at a high level; the high level is output to the control chip 100 pin.

When the voltage divided by the second resistor R2 and the third resistor R3 enables the grid voltage of the MOS tube Q1 to reach a conducting threshold value, the drain electrode and the source electrode of the MOS tube Q1 are conducted, and the voltage of the drain electrode of the MOS tube Q1 is pulled down to the ground to be in a low level; the low level is output to the control chip 100 pin.

The time of the pulse signal edge selection circuit outputting the high level, that is, the time before the MOS transistor Q1 is turned on, is the time required for the gate-source voltage of the MOS transistor Q1 to rise to the turn-on threshold. When a high voltage is input to the gate, the voltage between the gate and the source does not rise immediately to the high voltage, but a charging process for the parasitic capacitance C _GS exists, and the voltage gradually rises.

The charging duration depends on the voltage division between the second resistor R2 and the third resistor R3, the resistance value of the third resistor R3, and the parasitic capacitance C _GS.

The pulse signal edge selection circuit provided by the embodiment of the application comprises: the MOS transistor, the first resistor, the second resistor and the third resistor; the first end of the second resistor is used for being connected with a pulse signal source; the second end of the second resistor is grounded through a third resistor; the second end of the second resistor is connected with the grid electrode of the MOS tube; the source electrode of the MOS tube is used for grounding; the drain electrode of the MOS tube is connected with the first end of the first resistor; the second end of the first resistor is used for being connected with a pulse signal source; the drain electrode of the MOS tube is used for being connected with a receiving pin of the control chip. The process of raising the gate-source voltage of the MOS tube to the conduction threshold is a process of charging the parasitic capacitance, so that the MOS tube has a certain conduction time. Before the MOS tube is conducted, the pulse signal edge selection circuit outputs a high level, and after the MOS tube is conducted, the pulse signal edge selection circuit outputs a low level; the on time of the MOS tube is determined by the second resistor, the third resistor and the parasitic capacitance, so that edge selection can be realized, and pulse time can be controlled.

In one possible implementation, the pulse signal edge selection circuit may further include a charging capacitor for more convenient adjustment of the rise pulse time. Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Referring to fig. 2, a schematic diagram of another pulse signal edge selection circuit according to an embodiment of the application is shown.

The pulse signal edge selection circuit provided by the embodiment of the application, similar to the above embodiment, comprises: the MOS tube Q1, the first resistor R1, the second resistor R2 and the third resistor R3; in addition, the embodiment of the application further comprises the following steps: the charge capacitor C1, the digital processing circuit U1, the fourth resistor R4 and the filter capacitor C2. The same devices and connection relationships as those of fig. 1 are not described again here, and only the connection relationships of the added devices are described.

The source electrode and the drain electrode of the MOS tube Q1 are respectively connected to the both ends of the fourth resistor R4.

The charging capacitor C1 is connected in parallel between the grid electrode and the source electrode of the MOS tube Q1.

The filter capacitor C2 is connected in parallel to both ends of the fourth resistor R4.

The input end of the digital processing circuit U1 is connected with the drain electrode of the MOS tube Q1; the output end of the digital processing circuit U1 is connected to the receiving pin of the control chip 100.

As a possible implementation manner, the digital processing circuit U1 of the present application specifically employs an and logic chip U1; the first input end of the AND logic chip U1 is used for connecting a power supply VDD through a fifth resistor R5, for example, the voltage of the VDD is 5V; the second input end of the logic chip U1 is connected with the drain electrode of the MOS transistor Q1; the output terminal of the AND logic chip U1 is used for connecting with the receiving pin of the control chip 100.

The digital processing circuit U1 can convert the analog signal into a digital signal, so as to ensure that the digital signal is input into the receiving pin of the control chip 100, and improve the stability of the control chip 100.

Considering that the parasitic capacitance C _GS is a fixed value and the capacitance is small, the embodiment connects a charging capacitor C1 in parallel outside the gate source of the MOS transistor Q1.

In this embodiment, when the pulse signal source 200 inputs a pulse with a high level V1, V1 is divided into two paths, one path passes through the first resistor R1 and the other path passes through the second resistor R2.

Before the MOS tube Q1 is conducted, one path through the first resistor R1 can obtain a voltage through the voltage division of the first resistor R1 and the fourth resistor R4, and the voltage is input to the second input end of the AND logic chip U1, so that the voltage meets the judgment threshold value of the input high level of the AND logic chip U1. Since the first input terminal of the AND logic chip U1 is connected to the power supply VDD through the fifth resistor R5, the AND logic chip U1 will output a high level.

One path of the high-level pulse passing through the second resistor R2 is divided by the second resistor R2 and the third resistor R3 to obtain a voltage V3, the voltage value of the voltage V3 is larger than the conduction threshold V _GSth of the MOS tube Q1, then the drain electrode and the source electrode of the MOS tube Q1 are conducted, the voltage of the voltage V2 is pulled down to the ground, namely 0V, and the voltage output by the logic chip U1 is changed into 0V at the moment.

The calculation formula of capacitor charging in the RC circuit is as follows: vt=v0+ (Vu-V0) [1-exp (-t/RC) ], where V0 is the initial voltage value on the capacitor, vu is the end voltage value of the capacitor filled, and Vt is the voltage value on the capacitor at any time t. Corresponding to the embodiment of the present application, v0=0, so vt=vu [1-exp (-t/RC) ], and the charging period t=rc ] Ln [ Vu/(Vu-Vt) ].

In the present embodiment, R corresponds to a third resistor R3; c corresponds to (C _GS +C1). Therefore, when a voltage V3 is instantaneously added to the gate of the MOS transistor Q1, the voltage rise between the gate and the source is actually a charging process of the capacitor (C _GS +c1), and when the voltage between the gate and the source reaches the threshold voltage V _GSth where the MOS transistor Q1 is turned on, the time t=r3 (C _GS+C1)*Ln[V3/(V3-V_GSth) ], where t is the time when the U1 outputs the high level pulse.

The above formula shows that: c _GS and V _GSth are fixed values, R3, C1 and V3 are adjustable variables, and the time at which U1 outputs the rising pulse can be changed by adjusting the values of R3, C1 and V3. Under the condition that other parameters are unchanged, the larger the C1 is, the larger the value of t is, the longer the rising edge pulse time of the U1 output is, and conversely, the shorter the rising edge pulse time of the U1 output is.

In the circuit provided in this embodiment, according to ohm's law, v3=v1×r3/(r2+r3) ], the formula is taken into the above formula to obtain t=r3 (cgs+c1) ×ln {1/[1- (V _GSth/V1×1+r2/R3) ] } in this formula, if C1, R3 and V1 are unchanged, the resistance value of R2 is increased, the amplitude of the decrease in Ln {1/[1- (V _GSth/V1×1+r2/R3) ] is smaller than the amplitude of the increase in R3, and therefore the value of t becomes larger, the longer the rising edge pulse time of the U1 output is, and conversely the shorter the rising edge pulse time of the U1 output is, but if the voltage value of R3 is larger than the value of V _GSth after the partial voltage is divided by R2 and R3 is ensured, otherwise the MOS transistor Q1 has no possibility of being turned on.

Because V2 is 0V at low level when the MOS transistor Q1 is in the on state, the level output after the and logic chip U1 is also 0V. When the pulse signal source sends out a falling edge, the voltage between the gate and the source of the MOS transistor Q1 becomes 0V, the drain and source electrodes of the MOS transistor Q1 become disconnected, the voltage V2 is still 0V, and the level output after passing through the AND logic chip U1 is 0V, namely, the level of the receiving pin of the input control chip does not change any, which is equivalent to that the falling edge pulse sent out by the pulse signal source is shielded before entering the control chip through the pulse signal edge selection circuit.

In order to verify the function of the input control chip provided by the application, refer to fig. 3, which is a circuit diagram corresponding to simulation of the pulse signal edge selection circuit provided by the embodiment of the application.

Q1 is chosen from 2N7002BK, and R1, R2 and R3 have equal resistance values, for example, equal to 100kΩ. For example, R4 has a resistance of 51kΩ, R5 has a resistance of 4.7kΩ, C1 has a capacitance of 0.1uF, C2 has a capacitance of 1nF, and U1 may be NC7S08. The pulse signal source may be implemented by a power supply VCC, for example, VCC is 12V, the switch S1 is for simulating rising and falling edges of the pulse signal, the high level is 12V when S1 is closed, the low level is 0V when S1 is open, the input voltage of U1 is 5V, and U1 is removed during simulation. The pulse signal source in the actual circuit outputs a PWM pulse signal.

The rising edge selection circuit is subjected to actual functional simulation by using Multisim circuit simulation software. And firstly constructing a simulation circuit in Multisim circuit simulation software according to the designed circuit. U1 is not added in the simulation circuit. The output end of the circuit is connected with a virtual oscilloscope for observing waveforms in the process of closing and opening the switch S1.

Referring to fig. 4, the simulation effect diagram of the pulse signal edge selection circuit provided by the embodiment of the application is shown.

Firstly, the switch S1 is in an off state, a virtual oscilloscope is opened, voltage sampling of the oscilloscope is set to be 2V/Div, time sampling is set to be 100ms/Div, and then a circuit is operated to observe the oscilloscope. When the switch S1 is not closed, the voltage of the output end is constantly kept at 0V; closing switch S1, rapidly suspending operation of the circuit, and observing that the oscilloscope captures a transient rising pulse. Continuing to operate the circuit, opening switch S1, rapidly suspending operation of the circuit, and observing that the oscilloscope captures an instantaneous rising pulse. The rising pulse generated when switch S1 is closed can be maintained at 1.970ms, the peak voltage of a is 4.053V, and the rising pulse generated when switch S1 is opened can be maintained at 25.284 ms, the peak voltage of b is 0.336V.

As can be seen from the simulation results, the rising pulse generated when the switch S1 is turned off has a very low voltage, and is defined as a low level for most of the input levels of the chip, and this pulse causes no enabling of the wake-up function by pulse edge detection inside the chip, regardless of the pulse hold time. The pulse is the falling edge state of the simulated external pulse, i.e. the new pulse peak voltage generated after the falling edge of the external pulse passes through the pulse rising edge selection circuit is lower than the high level threshold of the majority of the internal pulses of the chip. From this point of view, the pulse rising edge selection circuit shields the falling edge of the external pulse signal, only keeps the rising edge signal valid, and realizes the function of selecting the rising edge of the external pulse signal.

The pulse signal rising edge selection circuit still generates a new rising pulse with a very low peak value when simulating the falling edge, and most chips cannot be triggered by mistake to wake up a specific function. At this time, when the switch S1 is turned off, the pulse signal rising edge selection circuit does not generate a new pulse with a small peak value before U1 is added, and generates a new pulse only when the switch S1 is turned on, and is a standard square wave.

In the pulse signal rising edge selection circuit, the R2 resistance value in the circuit is properly adjusted, so that the holding time of a new pulse signal generated at the output end of the rising edge selection circuit can be changed. When the resistance value of R2 gradually becomes larger, the waveform of the output pulse is checked through simulation, so that the holding time of the output pulse is prolonged, and when the resistance value of R2 gradually becomes smaller, the holding time of the output pulse is shortened. This adjustment can meet the different requirements of different chips employed in different projects on the effective hold time of the input pulse. However, the resistance values of R2 and R3 must be kept in a proper ratio, V _GS≥V_GSth of Q1 is ensured, and the source electrode and the drain electrode of Q1 can be normally conducted.

In the pulse signal rising edge selection circuit, if the output end has no logic circuit related to U1, the proportion of R1 and R4 resistance values in the circuit can be adjusted according to the peak voltage of the PWM at the input end, and the peak voltage of the pulse signal generated at the output end of the rising edge selection circuit can be changed, wherein the peak voltage is necessarily smaller than the peak voltage of the PWM pulse at the input end. The waveform of the output pulse is found through simulation and inspection that the resistance ratio of R1 to R4 is gradually reduced, the peak voltage of the output pulse is increased, the resistance ratio of R1 to R4 is gradually increased, and the peak voltage of the output pulse is reduced. The adjustment can meet different requirements of different chips adopted in different projects on the peak voltage of the input pulse.

In the pulse signal rising edge selection circuit, the holding time of a new pulse signal generated at the output end of the rising edge selection circuit can be changed by adjusting the capacitance value of C1 in the circuit. When the capacitance of C1 gradually increases from 0.1uF, the waveform of the output pulse is checked by simulation, and the holding time of the output pulse becomes longer, and as the capacitance of C1 gradually decreases, the holding time of the output pulse becomes shorter. This adjustment can meet the different requirements of different chips employed in different projects on the effective hold time of the input pulse.

It can be seen that the pulse signal edge selection circuit provided in the above embodiment selects the rising edge as the control signal, and in other embodiments, the falling edge may also be selected as the control signal.

Referring to fig. 5, a schematic diagram of another pulse signal edge selection circuit according to an embodiment of the application is shown.

The difference between the falling edge selection circuit provided by the embodiment of the application and the rising edge selection circuit provided above is that an inverting converter U2 is added on the basis of the rising edge circuit; other parts may be referred to the description of the above embodiments, and are not described here again.

A first input terminal of the inverter U2 is connected to the pulse signal source 200; the output end of the inverter U2 is connected with the second end of the first resistor, namely the second end of the R1. The inverter U2 inverts the output signal of the pulse signal source 200, for example, to a low level at a high level and to a high level at a low level.

In a specific implementation manner, the inverter U2 is specifically a nand logic chip U2;

The first input end of the NAND logic chip U2 is used for connecting with the pulse signal source 200;

The second input end of the NAND logic chip U2 is used for connecting a power supply VCC, for example, the voltage of VCC is 12V;

The output end of the NAND logic chip U2 is connected with the second end of the first resistor, namely the second end of the R1.

The following describes in detail the operation principle of the falling edge trigger of the circuit according to the embodiment of the present application with reference to fig. 6.

The basic principle is as follows:

a) Simulating rising edge pulse: one input end of U2 is connected with VCC through a switch S1, the other input end of U2 is connected with VCC through a sixth resistor R6, V1 is divided into two paths after passing through U2, the voltage of the output end of U2 is V2, one path of V2 passes through R1, and the other path passes through R2. The U2 output level is mainly determined by the switching state of S1. The partial pressures of R2 and R3 are V3, and the partial pressures of R1 and R4 are V4.

When the S1 is disconnected, one input end of the U2 is low level, the switch S1 is closed instantaneously, rising edge pulse with high level is input in an analog mode, the low level is output after the rising edge pulse passes through the U2, the gate source voltage of the MOS tube Q1 is low level after the low level is divided by the resistor, the drain source electrode of the MOS tube Q1 is disconnected, one input end of the U1 is low level, the rising edge pulse is output after the rising edge pulse passes through the circuit and is shielded, and the next circuit cannot be affected.

B) Simulating a falling edge pulse: when S1 is closed, both input terminals of U2 are high. The momentary switch S1 is turned off and a low level pulse of 0V is analog input. Since one input terminal of U2 is low in the state where the switch S1 is instantaneously turned off, a transient high level is output after passing through U2. One path of the high level passing through R1 can pass through the voltage dividing circuits of R1 and R4 to obtain a voltage, the voltage is input to the input end of U1, and the other input end of U1 is connected with the high level through a pull-up resistor R5, so that U1 can output the high level.

One path of high level output by U2 passes through R2 and is divided by R2 and R3 to obtain a voltage, the conducting threshold V _GSth of the voltage MOS tube Q1 is conducted, then the drain electrode and the source electrode of the MOS tube Q1 are conducted, the voltage of V4 is pulled down to the ground, namely 0V, and then the voltage output by U1 is changed into low level 0V.

According to the above circuit analysis, U1 outputs both high and low levels at the same time, which is contradictory. According to the actual circuit simulation result, U1 will output a high level pulse, i.e. a high level is output first, and then a low level is output after a period of time, i.e. the circuit is equivalent to transmitting the falling edge pulse of the input end to the output end.

The period of time for U1 to output high level is the time for the gate-source voltage of MOS transistor Q1 to rise to V _GSth. As is well known, a parasitic capacitance C _GS exists between the gate and the source in the MOS transistor Q1, and when a high voltage V3 is externally input to the gate, the voltage between the gate and the source does not immediately rise to V3, but charges the internal parasitic capacitance CGS.

The calculation formula of capacitor charging in the RC circuit is as follows: vt=v0+ (Vu-V0) [1-exp (-t/RC) ], where V0 is the initial voltage value on the capacitor, vu is the end voltage value of the capacitor filled, and Vt is the voltage value on the capacitor at any time t. In this circuit v0=0, so vt=vu [1-exp (-t/RC) ], and the charging period t=rc ] Ln [ Vu/(Vu-Vt) ]. R corresponds to a resistor R3. Because C _GS is a fixed value and the capacitance is very small, a capacitor C1 is connected in parallel between the gate and the source of the MOS transistor Q1, and R corresponds to (C _GS +C1). Therefore, when a voltage V3 is instantaneously added to the gate of the MOS transistor Q1, the voltage between the gate and the source is actually a charging process of the capacitor (C _GS +c1), and when the voltage between the gate and the source reaches the threshold voltage V _GSth where the MOS transistor Q1 is turned on, the time t=r3 (C _GS+C1)*Ln[V3/(V3-V_GSth) ], where t is the time when the U2 outputs the high-level pulse.

The above formula shows that: c _GS and V _GSth are fixed values, R3, C1 and V3 are adjustable variables, and the time at which U1 outputs the rising pulse can be changed by adjusting the values of R3, C1 and V3. Under the condition that other parameters are unchanged, the larger the C1 is, the larger the value of t is, the longer the rising edge pulse time of the U1 output is, and conversely, the shorter the rising edge pulse time of the U1 output is. According to ohm's law, v3=v1×r 3/(r2+r3) ], the formula is taken into the above formula and converted to obtain t=r3 (C _GS+C1)*Ln{1/[1-(V_GSth/V1×1+r2/R3) ].

The specific values and types of the parameters in the circuit have been described above, and are not described here again. The switch S1 is added in the simulation software for simulating the rising edge and the falling edge of the pulse signal, and is absent in the actual pulse signal rising edge selection circuit, and is a real PWM pulse signal in the actual circuit.

The rising edge selection circuit is actually simulated by Multisim circuit simulation software. In Multisim circuit simulation software, a simulation circuit is built according to a design circuit, U1 is not added in the simulation circuit, a switch S1 is added, one end of the switch S1 is connected with a 5V direct current power supply, and rising edges and falling edges of external pulse signals are simulated through closing and opening of the switch S1 respectively. The output end of the circuit is connected with a virtual oscilloscope, which is used for observing waveforms in the process of closing and opening the switch S1, and the simulation circuit is shown in fig. 7.

Referring to fig. 8, the falling edge simulation effect diagram of the pulse signal edge selection circuit provided by the embodiment of the application is shown.

Firstly, the switch S1 is in a closed state, a virtual oscilloscope is opened, voltage sampling of the oscilloscope is set to be 2V/Div, time sampling is set to be 100ms/Div, and then a circuit is operated to observe the oscilloscope. When the switch S1 is not turned off, the voltage of the output end is constantly kept at 0V; the switch S1 is turned off, the operation of the circuit is rapidly suspended, and the oscilloscope is observed to drop to 0V after capturing an instantaneous rising pulse. Continuing the circuit, switch S1 was closed, and no change in oscilloscope voltage was observed, still being 0V.

The rising pulse generated when switch S1 is momentarily turned off can be maintained at a peak voltage of 4.180V for 7.4478 ms. When the circuit is simulated, the switch S1 is instantaneously closed to simulate the rising edge of the pulse signal, and the switch S1 is instantaneously opened to simulate the falling edge of the pulse signal. From the simulation results, the output will only generate a new pulse when the switch S1 is momentarily opened. That is, after the pulse signal inputted from the outside passes through the pulse signal falling edge selection circuit, a new pulse signal is generated only at the falling edge of the external pulse signal, and the rising edge of the pulse signal inputted from the outside cannot generate a new pulse signal.

In order to make the pulse signal rising edge selection circuit more reliable, the invention adds a AND logic chip U1 at the output end of the circuit to convert the new pulse signal generated by the external pulse signal falling edge into a standard square wave, thereby improving the stability of the pulse signal rising edge selection circuit.

In the pulse signal falling edge selection circuit, the R2 resistance value in the circuit is properly adjusted, so that the holding time of a new pulse signal generated at the output end of the falling edge selection circuit can be changed. When the resistance value of R2 gradually becomes larger, the waveform of the output pulse is checked through simulation, so that the holding time of the output pulse is prolonged, and when the resistance value of R2 gradually becomes smaller, the holding time of the output pulse is shortened. This adjustment can meet the different requirements of different chips employed in different projects on the effective hold time of the input pulse. However, the resistance values of R2 and R3 must be kept in a proper ratio, V _GS≥V_GSth of Q1 is ensured, and the source electrode and the drain electrode of Q1 can be normally conducted.

In the pulse signal falling edge selection circuit, if the output end has no logic circuit related to U1, the proportion of R1 and R4 resistance values in the circuit can be adjusted according to the peak voltage of the PWM at the input end, and the peak voltage of the pulse signal generated at the output end of the falling edge selection circuit can be changed, wherein the peak voltage is necessarily smaller than the peak voltage of the PWM pulse at the input end. The waveform of the output pulse is found through simulation and inspection that the resistance ratio of R1 to R4 is gradually reduced, the peak voltage of the output pulse is increased, the resistance ratio of R1 to R4 is gradually increased, and the peak voltage of the output pulse is reduced. The adjustment can meet different requirements of different chips adopted in different projects on the peak voltage of the input pulse.

In the pulse signal falling edge selection circuit, the holding time of a new pulse signal generated at the output end of the falling edge selection circuit can be changed by adjusting the capacitance value of C1 in the circuit. When the capacitance of C1 gradually increases from 0.1uF, the waveform of the output pulse is checked by simulation, and the holding time of the output pulse becomes longer, and as the capacitance of C1 gradually decreases, the holding time of the output pulse becomes shorter. This adjustment can meet the different requirements of different chips employed in different projects on the effective hold time of the input pulse.

The embodiment of the application is not particularly limited to the type of Q1, and Q1 can select N-channel metal oxide semiconductor field effect transistors with different performances of different manufacturers according to actual design requirements. The replacement of Q1 in different projects only affects the duration of the pulse at the output end of the output edge selection circuit and the magnitude of the peak voltage, and the manufacturing method of the pulse signal edge selection circuit is not changed.

The embodiment of the application is not particularly limited to the specific types of U1 and U2, and ensures that the peak voltage of an external input pulse signal is matched with the input voltage of U1, and the peak voltage of the input pulse signal cannot be larger than the maximum value of the input voltages of the selected U1 and U2.

The circuit provided by the embodiment of the application mainly utilizes the switching characteristic of the N-channel metal oxide semiconductor field effect transistor, and completes a pulse signal rising edge or falling edge selection circuit of a specific control chip or unit through the field effect transistor, the logic gate chip, the resistor and the capacitor.

Based on the pulse signal edge selection circuit provided in the above embodiment, the embodiment of the application further provides a control circuit, which is described in detail below with reference to the accompanying drawings.

Referring to fig. 9, a schematic diagram of a control circuit according to an embodiment of the present application is shown.

The control circuit provided by the embodiment of the application comprises: the pulse signal source 200, the control chip 100 and the pulse signal edge selection circuit 300 described in the above embodiments;

The pulse signal source 200 is connected to a receiving pin of the control chip 100 through a pulse signal edge selection circuit 300.

The control circuit provided by the embodiment of the application can realize single-edge triggering on the control chip 100, for example, rising edge triggering can be realized by using the rising edge selection circuit provided by fig. 2. The falling edge triggering can be achieved with the falling edge selection circuit provided in fig. 5.

It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A pulse signal edge selection circuit, comprising: a metal oxide semiconductor field effect transistor MOS, a first resistor, a second resistor and a third resistor;

the first end of the second resistor is used for being connected with a pulse signal source; the second end of the second resistor is grounded through the third resistor;

The second end of the second resistor is connected with the grid electrode of the MOS tube;

The source electrode of the MOS tube is used for grounding; the drain electrode of the MOS tube is connected with the first end of the first resistor; the second end of the first resistor is used for being connected with the pulse signal source;

and the drain electrode of the MOS tube is used for being connected with a receiving pin of the control chip.

2. The circuit of claim 1, further comprising: a charging capacitor;

The charging capacitor is connected in parallel between the grid electrode of the MOS tube and the source electrode of the MOS tube.

3. The circuit of claim 1, further comprising: a digital processing circuit;

The input end of the digital processing circuit is connected with the drain electrode of the MOS tube; and the output end of the digital processing circuit is used for being connected with a receiving pin of the control chip.

4. A circuit according to claim 3, wherein the digital processing circuit is embodied as an and logic chip;

The first input end of the AND logic chip is used for being connected with a power supply;

The second input end of the AND logic chip is connected with the drain electrode of the MOS tube;

and the output end of the AND logic chip is used for being connected with a receiving pin of the control chip.

5. The circuit of claim 1, further comprising: a fourth resistor;

and two ends of the fourth resistor are respectively connected with a source electrode and a drain electrode of the MOS tube.

6. The circuit of claim 5, further comprising: a filter capacitor;

The filter capacitor is connected in parallel with two ends of the fourth resistor.

7. The circuit of any one of claims 1-6, further comprising: an inverting converter;

The first input end of the inverting converter is used for being connected with the pulse signal source; the output end of the inverting converter is connected with the second end of the first resistor.

8. The circuit of claim 7, wherein the inverting converter is embodied as a nand logic chip;

The first input end of the NAND logic chip is used for being connected with the pulse signal source;

the second input end of the NAND logic chip is used for connecting a power supply;

And the output end of the NAND logic chip is connected with the second end of the first resistor.

9. The circuit of any of claims 1-6, wherein a resistance of the second resistor and a resistance of the third resistor are equal.

10. A control circuit, comprising: a pulse signal source, a control chip and the pulse signal edge selection circuit of any one of claims 1-9;

The pulse signal source is connected with a receiving pin of the control chip through the pulse signal edge selection circuit.