CN221127828U

CN221127828U - Display substrate and display device

Info

Publication number: CN221127828U
Application number: CN202322643651.XU
Authority: CN
Inventors: 罗宁; 齐超; 游建辉; 桑金龙; 孙亚萌; 殷摇进; 杨映帆
Original assignee: BOE Technology Group Co Ltd; Mianyang BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Mianyang BOE Optoelectronics Technology Co Ltd
Priority date: 2023-09-27
Filing date: 2023-09-27
Publication date: 2024-06-11
Anticipated expiration: 2033-09-27

Abstract

A display substrate and a display device are provided. The display substrate comprises a substrate, the substrate comprises a display area, a first frame area and a plurality of sub-pixels, the substrate is positioned in the display area, a plurality of data lines and a plurality of sub-pixels are electrically connected, a plurality of data line leads are positioned in the first frame area, the plurality of data line leads are electrically connected with the plurality of data lines, a plurality of driving chip pins are positioned in the first frame area, one driving chip pin is electrically connected with one data line lead, and the plurality of driving chip pins are positioned at one side of the plurality of data line leads far away from the substrate; the surface of one side of the pin of the driving chip far away from the substrate is provided with at least one groove structure, the at least one groove structure comprises a groove bottom and a groove wall connected with the groove bottom, the at least one groove structure is provided with a groove depth along the thickness direction of the display substrate, and the range of the groove depth is 0.40-0.65 microns. The display substrate can solve the problems of poor dark line and the like in the first frame area of the existing display substrate.

Description

Display substrate and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate and a display device.

Background

With the continuous development of display technology, the structural form of the display substrate also shows diversification. The low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO) display substrate integrates a low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor on the same display substrate, and the LTPO display substrate can realize high-resolution (Pixel Per Inch, PPI) and low-frequency driving, so that the power consumption of the display device can be reduced, and the display quality of the display device can be improved.

Currently, LTPO display substrates have problems such as poor dark lines in the first frame region.

Disclosure of utility model

The embodiment of the utility model provides a display substrate and a display device, which can solve the problems of poor dark line and the like in a first frame area of the existing display substrate.

In one aspect, an embodiment of the present utility model provides a display substrate, including:

a substrate including a display region and a first frame region located at one side of the display region;

A plurality of sub-pixels located in the display area;

The data lines are positioned in the display area and are electrically connected with the sub-pixels;

A plurality of data line leads located in the first frame region, and electrically connected to the plurality of data lines;

The driving chip pins are positioned in the first frame area, one driving chip pin is electrically connected with one data line lead, and the driving chip pins are positioned at one side of the data line leads far away from the substrate;

The driving chip pin is provided with at least one groove structure on one side surface far away from the substrate, the at least one groove structure comprises a groove bottom and a groove wall connected with the groove bottom, the at least one groove structure is provided with a groove depth along the thickness direction of the display substrate, and the range of the groove depth is 0.40-0.65 microns.

In an exemplary embodiment, in a plane perpendicular to the display substrate, the first frame region includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer that are disposed on one side of the substrate and are sequentially stacked; the first metal layer comprises the plurality of data line leads, and the fourth metal layer comprises the plurality of driving chip pins.

In an exemplary embodiment, in a plane perpendicular to the display substrate, the first frame region further includes at least one insulating layer between the first metal layer and the second metal layer; the second metal layer comprises at least one connecting electrode, and part of the connecting electrode is positioned in the through hole of the at least one insulating layer and is in contact connection with the surface of the data line lead far away from one side of the substrate.

In an exemplary embodiment, the at least one insulating layer includes a first inorganic layer and a second inorganic layer, and the second inorganic layer is farther from the substrate than the first inorganic layer; in the line width direction of the data line lead, the orthographic projection of the via hole arranged on the first inorganic layer on the display substrate is positioned in the orthographic projection of the data line lead on the display substrate, the orthographic projection of the via hole arranged on the second inorganic layer on the display substrate comprises the orthographic projection of the data line lead on the display substrate, and the orthographic projection of the via hole arranged on the second inorganic layer on the display substrate is larger than the orthographic projection of the data line lead on the display substrate.

In an exemplary embodiment, the insulating layer is disposed between the first metal layer and the second metal layer, and in a line width direction of the data line lead, a front projection of the via hole disposed on the insulating layer on the display substrate is located within a front projection of the data line lead on the display substrate.

In an exemplary embodiment, in a plane perpendicular to the display substrate, the display area includes a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer, which are disposed on one side of the substrate and are sequentially stacked; the first metal layer and the first gate metal layer are of the same layer structure, the second metal layer and the first source drain metal layer are of the same layer structure, and the third metal layer and the second source drain metal layer are of the same layer structure.

In an exemplary embodiment, in a plane perpendicular to the display substrate, the display area includes a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer, which are disposed on one side of the substrate and are sequentially stacked; the first metal layer and the second gate metal layer are of the same layer structure, the second metal layer and the first source drain metal layer are of the same layer structure, and the third metal layer and the second source drain metal layer are of the same layer structure.

In an exemplary embodiment, the second metal layer includes at least one first connection electrode, and the third metal layer includes at least one second connection electrode; at least part of the surface of the second connecting electrode far away from one side of the substrate is in contact connection with the groove structure of the driving chip pin, and part of the surface of the first connecting electrode near one side of the substrate is in contact connection with the data line lead.

In an exemplary embodiment, the first connection electrode has a first sub-slot, the second connection electrode has a second sub-slot, the front projection of the groove structure of the driving chip pin on the display substrate is located within the front projection of the second sub-slot on the display substrate, and the front projection of the second sub-slot on the display substrate is located within the front projection of the first sub-slot on the display substrate.

In an exemplary embodiment, in a plane perpendicular to the display substrate, the first frame region further includes a fill-in layer, the fill-in layer being located between the substrate and the first metal layer; the compensation layer comprises at least one compensation block; and in the line width direction of the data line lead, the orthographic projection of the data line lead on the display substrate comprises the orthographic projection of the compensation block on the display substrate.

In an exemplary embodiment, in a plane perpendicular to the display substrate, the first frame region further includes a fill-in layer between the first metal layer and the second metal layer, the fill-in layer including at least one fill-in block; and in the line width direction of the data line lead, the orthographic projection of the compensation block on the display substrate comprises orthographic projection of the data line lead on the display substrate, and the data line lead is electrically connected with the groove structure of the driving chip pin through the compensation block.

In an exemplary embodiment, in a plane perpendicular to the display substrate, the first frame region further includes at least one insulating layer, the at least one insulating layer is located between the first metal layer and the second metal layer, and a surface of the at least one insulating layer on a side away from the substrate is flush with a surface of the data line lead and the complementary flat block on a side away from the substrate.

In an exemplary embodiment, the second metal layer includes at least one first connection electrode, and the third metal layer includes at least one second connection electrode; the data line lead is connected with the groove structure of the driving chip pin through the first connecting electrode and the second connecting electrode;

Wherein, the surface of the first connecting electrode far away from one side of the substrate is a plane.

In an exemplary embodiment, a surface of the second connection electrode on a side away from the substrate is a plane.

In an exemplary embodiment, in a plane perpendicular to the display substrate, the display area includes a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer, which are disposed on one side of the substrate and are sequentially stacked; the second metal layer and the first source drain metal layer are of the same layer structure, and the third metal layer and the second source drain metal layer are of the same layer structure;

The filling layer and one of the first gate metal layer and the second gate metal layer are of a same layer structure, and the first metal layer and the other of the first gate metal layer and the second gate metal layer are of a same layer structure.

In another aspect, an embodiment of the present utility model provides a display device, where the display device includes the display substrate according to any one of the foregoing embodiments.

According to the display substrate provided by the embodiment of the utility model, the groove depth of the groove structure in the first frame area is limited, so that after the display substrate is assembled into the display device, the electric element waiting installation part is reliably connected with the first frame area through the groove structure, the problems of dark lines and the like can be avoided, and the yield of the display device can be improved.

Additional features and advantages of the utility model will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model. Other advantages of the utility model may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the principles of the utility model, and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain, without limitation, the principles of the utility model.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the utility model;

FIG. 2 is a schematic plan view of a display substrate according to an embodiment of the utility model;

FIG. 3 is a schematic partial cross-sectional view of a display area of a display substrate according to an embodiment of the utility model;

FIG. 4 is a schematic diagram showing a partial cross-section of a driving chip pin of a display substrate according to an embodiment of the utility model;

FIG. 5 is a schematic diagram showing a partial cross-section of a driving chip pin of a display substrate according to an embodiment of the utility model;

FIG. 6 is a schematic diagram of a driving chip pin of a display substrate according to an embodiment of the utility model;

FIG. 7 is a schematic diagram showing a partial cross-section of a driving chip pin of a display substrate according to an embodiment of the utility model;

FIG. 8 is a schematic diagram showing a partial cross section of a driving chip pin of a display substrate according to an embodiment of the utility model;

fig. 9A to 9G are schematic views illustrating a process of manufacturing a driving chip pin of a display substrate according to an embodiment of the utility model;

FIG. 10 is a schematic partial cross-sectional view of a driving chip pin of a display substrate according to another embodiment of the utility model;

FIG. 11 is a schematic diagram showing a partial cross-section of a driving chip pin of a display substrate according to another embodiment of the utility model;

FIG. 12 is a schematic diagram showing a partial cross-section of a driving chip pin of a display substrate according to another embodiment of the utility model;

fig. 13A to 13H are schematic views illustrating a process of manufacturing a driving chip pin of a display substrate according to another embodiment of the utility model;

fig. 14 is a schematic partial cross-sectional view of a display device according to an embodiment of the utility model.

Reference numerals:

A 21-timing controller, a 22-data driver, a 23-scan driving circuit, a 24-light emission driving circuit, and a 25-subpixel array;

10-substrate, 11-first insulating layer, 12-second insulating layer, 13-third insulating layer, 14-fourth insulating layer, 15-fifth insulating layer, 16-active layer, 17-gate, 18-first capacitor electrode, 19-second capacitor electrode, 110-source electrode, 111-drain electrode, 112-pixel connection electrode, 113-anode, 20-circuit structure layer, 30-light emitting structure layer, 40-encapsulation layer, 50-data line lead, 51-first connection electrode, 511-first trench bottom, 512-first trench top, 513-first trench wall, 52-second connection electrode, 521-second trench bottom, 522-second trench top, 523-second trench wall, 53-driving chip pin, 60-trench structure, 61-trench bottom, 62-trench top, 63-trench wall, 70-supplementary flat block, 80-conductive paste, 90-driving chip, 131-driving chip area, 100-touch structure layer, 101-protective layer.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present utility model more apparent, embodiments of the present utility model will be described in detail hereinafter with reference to the accompanying drawings. Embodiments may be implemented in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the present utility model may be embodied in one or more forms and with the aid of a method and apparatus for performing the present utility model without departing from the spirit or essential scope thereof. Therefore, the present utility model should not be construed as being limited to the following embodiments. Embodiments of the utility model and features of the embodiments may be combined with one another arbitrarily without conflict.

In the drawings, the size of one or more constituent elements, thicknesses of layers or regions may be exaggerated for clarity. Accordingly, one embodiment of the present utility model is not necessarily limited to this size, and the shapes and sizes of the respective components in the drawings do not reflect the actual scale. Further, the drawings schematically show ideal examples, and one embodiment of the present utility model is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers of "first", "second", "third", etc. in the present utility model are provided to avoid mixing of constituent elements, and are not limited in number. The term "plurality" in the present utility model includes two as well as more than two numbers.

In the present utility model, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which designate orientations or positional relationships, are used to describe positional relationships of constituent elements with reference to the drawings, are merely for convenience in describing the present specification and simplifying the description, and do not designate or imply that the apparatus or elements being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus are not to be construed as limiting the present utility model. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, the present utility model is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In the present utility model, the terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to circumstances.

In the present utility model, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present utility model, a channel region refers to a region through which current mainly flows.

In the present utility model, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in the present utility model, "source electrode" and "drain electrode" may be exchanged with each other.

In the present utility model, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having one or more functions, and the like.

In the present utility model, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and thus, may include a state in which the angle is-5 ° or more and 5 ° or less. Further, "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus may include a state in which an angle is 85 ° or more and 95 ° or less.

In the present utility model, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The term "about" in the present utility model means not strictly limited to numerical values within the limits of permissible process and measurement errors.

The embodiment of the utility model provides a display substrate. The display substrate includes: the display device comprises a substrate, a first frame area, a plurality of sub-pixels, a plurality of driving chip pins and a plurality of data line leads, wherein the first frame area and the plurality of sub-pixels are positioned at one side of the display area, the plurality of data lines and the plurality of sub-pixels are electrically connected and the plurality of data line leads are positioned at the first frame area, the plurality of data line leads and the plurality of data line leads are electrically connected and the plurality of driving chip pins are positioned at the first frame area, one driving chip pin is electrically connected with one data line lead, and the plurality of driving chip pins are positioned at one side of the plurality of data line leads far away from the substrate; the driving chip pin is provided with at least one groove structure on one side surface far away from the substrate, the at least one groove structure comprises a groove bottom and a groove wall connected with the groove bottom, the at least one groove structure is provided with a groove depth along the thickness direction of the display substrate, and the range of the groove depth is 0.40-0.65 microns.

According to the display substrate provided by the embodiment of the utility model, the groove depth of the groove structure of the driving chip pin in the first frame region is limited, so that after the display substrate is assembled into the display device, the electric element waiting installation part is reliably connected with the first frame region through the groove structure, the problems of dark lines and the like can be avoided, and the yield of the display device can be improved.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the utility model. As shown in fig. 1, the display device may include a timing controller 21, a data driver 22, a scan driving circuit 23, a light emitting driving circuit 24, and a sub-pixel array 25. In some examples, the sub-pixel array 25 may include a plurality of sub-pixels PX arranged in a regular arrangement. The scan driving circuit 23 may be configured to supply a scan signal to the sub-pixels PX along a scan line. The data driver 22 may be configured to supply a data voltage to the sub-pixels PX along the data lines. The light emission driving circuit 24 may be configured to supply a light emission control signal to the sub-pixels PX along the light emission control lines. The timing controller 21 may be configured to control the scan driving circuit 23, the light emission driving circuit 24, and the data driver 22.

In an exemplary embodiment, as shown in fig. 1, the timing controller 21 may provide gray values and control signals suitable for the specification of the data driver 22 to the data driver 22. The timing controller 21 may supply a scan clock signal, a scan start signal, or the like, which are suitable for the specification of the scan driving circuit 23, to the scan driving circuit 23. The timing controller 21 may supply a light emission clock signal, a light emission start signal, or the like, which are suitable for the specification of the light emission driving circuit 24, to the light emission driving circuit 24. The data driver 22 may generate data voltages to be supplied to a plurality of data lines, which may include the data lines DL1 to DLi, using the gray values and control signals received from the timing controller 21. For example, the data driver 22 may sample the gray value with a clock signal and apply the data voltage corresponding to the gray value to the data lines DL1 to DLi in units of sub-pixel rows. The scan driving circuit 23 may generate a scan signal to be supplied to a plurality of scan lines, which may include the scan lines GL1 to GLj, by a scan clock signal, a scan start signal, etc., received from the timing controller 21. For example, the scan driving circuit 23 may sequentially supply a scan signal having an on-level pulse to the scan lines. In some examples, the scan driving circuit 23 may include a shift register, and may generate the scan signal in such a manner that the scan start signal provided in the form of the on-level pulse is sequentially transmitted to the next stage circuit under the control of the scan clock signal. The light emission driving circuit 24 may generate light emission control signals to be supplied to the light emission control lines E1 to Eo by a light emission clock signal, a light emission start signal, or the like received from the timing controller 21. For example, the light emission driving circuit 24 may sequentially supply the light emission control signals having the off-level pulses to the light emission control lines. The light emission driving circuit 24 may include a shift register to generate a light emission control signal in such a manner that a light emission start signal supplied in the form of a cut-off level pulse is sequentially transmitted to a next stage circuit under control of a clock signal. Wherein i, j and o are natural numbers.

In an exemplary embodiment, a display device may include a display substrate. The scan driving circuit and the light emitting driving circuit may be directly disposed on the display substrate. For example, the scan driving circuit may be disposed at a left frame of the display substrate, and the light emitting driving circuit may be disposed at a right frame of the display substrate. Or the left frame and the right frame of the display substrate can be provided with a scanning driving circuit and a light-emitting driving circuit. In some examples, the scan driving circuit and the light emission driving circuit may be formed together with the sub-pixels in a process of forming the sub-pixels.

In an exemplary embodiment, the data driver may be provided on a separate chip or a printed circuit board to be connected to the sub-pixels through signal access pins on the display substrate. For example, the data driver may form a first frame provided at the display substrate using a chip on glass, a chip on plastic, a chip on film, etc. to be connected to the signal access pin. The timing controller may be provided separately from the data driver or integrally with the data driver. However, the embodiment of the present utility model is not limited thereto. In some examples, the data driver may be disposed directly on the display substrate.

Fig. 2 is a schematic plan view of a display substrate according to an embodiment of the utility model. As shown in fig. 2, the display substrate may include a display area AA and a peripheral area surrounding the display area AA. The peripheral area may include a first frame area B1 located at one side of the display area AA and a second frame area B2 located at the other side of the display area AA. In the embodiment of the present utility model, the first frame area B1 may also be referred to as a binding area. The second frame region B2 may be located at least at both sides of the first frame region B1. For example, the first frame region B1 may be a lower frame of the display substrate, and the second frame region B2 may include an upper frame, a left frame, and a right frame of the display substrate. In some examples, the display area AA may be a flat area including a plurality of sub-pixels PX constituting a sub-pixel array, the plurality of sub-pixels PX being configured to display a moving picture or a still image. The display area may also be referred to as an active area. In some examples, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, e.g., curled, bent, folded, or rolled.

In an exemplary embodiment, the second bezel area B2 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially disposed along the direction of the display area AA. The circuit region may be connected to the display region AA, and the circuit region may include at least a gate driving circuit (e.g., including a plurality of cascaded shift registers) and the plurality of shift registers may be electrically connected to a plurality of scan lines in the display region AA. The power line region is connected to the circuit region, and may include at least a low-level power line, which may extend in a direction parallel to an edge of the display region, and may be connected to a cathode of the display region AA. The crack dam region may be connected to the power line region, and the crack dam region may include at least a plurality of cracks provided on the composite insulating layer. The cutting region may be connected to the crack dam region, and the cutting region may include at least a cutting groove provided on the composite insulating layer, and the cutting groove may be configured such that the cutting device may cut along the cutting groove after all film layers of the display substrate are prepared.

In an exemplary embodiment, as shown in fig. 2, the display area AA may include a plurality of sub-pixels PX, a plurality of scan lines GL, and a plurality of data lines DL. The plurality of scan lines GL may extend in the first direction X, and the plurality of data lines DL may extend in the second direction Y. The orthographic projections of the plurality of scanning lines GL and the plurality of data lines DL on the display substrate are intersected to form a plurality of sub-pixel areas, and one sub-pixel PX is arranged in each sub-pixel area. The plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, and, for example, one data line DL is electrically connected to one column of sub-pixels PX, the plurality of data lines DL may be configured to supply data signals to the plurality of sub-pixels PX. The plurality of data lines DL may extend to the first frame region B1. The plurality of scan lines GL are electrically connected to the plurality of sub-pixels PX, and the plurality of scan lines GL may be configured to supply gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signal may include a scan signal and a light emission control signal.

In an exemplary embodiment, as shown in fig. 2, the first direction X may be an extending direction (row direction) of the scan lines GL in the display area AA, and the second direction Y may be an extending direction (column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect. For example, the first direction X and the second direction Y may be perpendicular to each other. In the embodiment of the present utility model, the first direction X is also the line width direction of the data line DL.

In an exemplary embodiment, as shown in fig. 2, the first frame region B1 may include a first sub-region B11, a bent region B12, and a second sub-region B13 in a direction away from the display region AA. Both ends of the first sub-region B11 in the first direction X may communicate with the second frame regions B2 on both left and right sides. In the embodiment of the present utility model, the first sub-area B11 may also be referred to as a first fan-out area, and the first sub-area B11 may be connected to the display area AA.

In an exemplary embodiment, as shown in fig. 2, the bending region B12 may be connected between the first and second sub-regions B11 and B13. For example, the bending region B12 may include a composite insulating layer provided with a groove, and the groove may be configured to bend a portion of the first frame region B1 to the rear surface of the display region AA.

In an exemplary embodiment, the width of the bending region B12 in the second direction Y may range from 0.5 mm to 1.0 mm. For example, the width of the bending region B12 in the second direction Y may be 1.0 mm.

In an exemplary embodiment, as shown in fig. 2, the second sub-region B13 may include a plurality of pins. The second sub-region B13 may include a circuit arrangement region, a driving chip region 131, and a bonding pin region sequentially disposed in a direction away from the display region AA. The circuit arrangement region may include at least an electrostatic discharge circuit, and the electrostatic discharge circuit may be configured to prevent electrostatic damage of the display substrate by eliminating static electricity. The driving chip region 131 may be provided for disposing driving chips (INTEGRATED CIRCUIT, ICs), and the driving chip region 131 may include a plurality of driving chip pins 53, and the driving chips may be electrically connected with the data lines DL of the display area AA through the driving chip pins 53, the data line leads 50. The first frame region B1 may include a plurality of data line leads 50, the plurality of data line leads 50 being electrically connected to the plurality of data lines DL, and the data line leads 50 being connected to the data lines DL in one-to-one correspondence, for example. The driving chip may be configured to generate signals required for driving the sub-pixels and supply the driving signals to the data lines of the display area. For example, the driving signal may be a data signal driving the light emission luminance of the sub-pixel. The bonding pin region may include a plurality of bonding pins, which may be configured to bond with a corresponding at least one circuit board (e.g., flexible circuit board (Flexible Printed Circuit, FPC)). The driver chip pins 53 in the driver chip region 131 may be electrically connected with the bonding pins in the bonding pin region through pin connection lines. In an exemplary embodiment, one pixel unit of the display area AA may include a plurality of sub-pixels. For example, one pixel unit may include three sub-pixels, which may be red, green, and blue sub-pixels, respectively. However, the embodiment of the present utility model is not limited thereto. In some examples, one pixel unit may include four sub-pixels, which are red, green, blue, and white sub-pixels, respectively.

In an exemplary embodiment, the shape of the sub-pixels may be rectangular, diamond-shaped, pentagonal, or hexagonal. When a pixel unit comprises three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or delta mode; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel or square manner. However, the embodiment of the present utility model is not limited thereto.

In an exemplary embodiment, one subpixel may include: and a pixel circuit and a light emitting element electrically connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Wherein, T in the circuit structure refers to a thin film transistor, C refers to a capacitor, the number in front of T represents the number of the thin film transistors in the circuit, and the number in front of C represents the number of the capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit may be P-type transistors or may be N-type transistors. The same type of transistor is adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty of the display substrate is reduced, and the yield of products is improved. In other examples, the plurality of transistors in the pixel circuit may include a P-type transistor and an N-type transistor.

In an exemplary embodiment, the plurality of transistors in the pixel circuit may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charge and the like, the Oxide thin film transistor has the advantages of low leakage current and the like, and the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate, namely, an LTPS+oxide (LTPO for short) display substrate, so that the advantages of the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In an exemplary embodiment, the light emitting element may be any one of a light emitting Diode (LIGHT EMITTING Diode, LED), an Organic LIGHT EMITTING Diode (OLED), a Quantum Dot LIGHT EMITTING Diode (QLED), a micro LED (including a mini-LED or micro-LED), and the like. For example, the light emitting element may be an OLED, and the light emitting element may emit red light, green light, blue light, white light, or the like under the driving of its corresponding pixel circuit. The color of the light emitted by the light emitting element may be determined as needed. In some examples, the light emitting element may include: an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element may be electrically connected to a corresponding pixel circuit. However, the embodiment of the present utility model is not limited thereto.

Fig. 3 is a schematic partial cross-sectional view of a display area of a display substrate according to an embodiment of the utility model. As shown in fig. 3, in a direction perpendicular to the display substrate, the display region of the display substrate may include: a substrate 10, and a circuit structure layer 20, a light emitting structure layer 30, a packaging layer 40, and a touch structure layer 100 sequentially disposed on the substrate 10. The touch structure layer 100 may include an Over Coating (OC) 101, a touch layer, and a touch insulating layer, which are stacked.

In an exemplary embodiment, the substrate 10 may be a flexible base, or may be a rigid base. The rigid substrate may be, but is not limited to, one or more of glass, quartz. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers, and the like.

In an exemplary embodiment, the substrate 10 may be a composite film layer. As illustrated in fig. 3, the substrate 10 may be a composite film layer of three film layers, and as illustrated, the substrate 10 may include a first inorganic sub-layer, an organic layer, and a second inorganic sub-layer stacked in this order.

In an exemplary embodiment, as shown in fig. 3, the circuit structure layer 20 may include a plurality of transistors and storage capacitors constituting a pixel circuit, and is described in fig. 3 by taking an example in which each sub-pixel includes only one transistor and one storage capacitor. The circuit structure layer 20 may include a semiconductor layer disposed on one side of the substrate 10, a first insulating layer 11 covering the semiconductor layer, a first conductive layer 11-1 disposed on the first insulating layer 11, a second insulating layer 12 covering the first conductive layer 11-1, a second conductive layer 12-1 disposed on the second insulating layer 12, a third insulating layer 13 covering the second conductive layer 12-1, a third conductive layer 13-1 disposed on the third insulating layer 13, a fourth conductive layer 14-1 on a side of the third conductive layer 13-1 remote from the substrate 10, and a fourth insulating layer 14. The semiconductor layer may include an active layer 16 of a transistor. The first conductive layer 11-1 may include a gate electrode 17 of a transistor and a first capacitor electrode 18 of a storage capacitor. The second conductive layer 12-1 may include a second capacitor electrode 19 that stores a capacitor. The third conductive layer 13-1 may include a source electrode 110, a drain electrode 111, and a data line of a transistor. The fourth conductive layer 14-1 may include a pixel connection electrode 112, and the pixel connection electrode 112 may be configured to be connected to an anode 113 of the light emitting element. In the embodiment of the utility model, in the display area of the display substrate, the first conductive layer may be referred to as a first gate metal layer, the second conductive layer may be referred to as a second gate metal layer, the third conductive layer may be referred to as a first source drain metal layer, and the fourth conductive layer may be referred to as a second source drain metal layer. The first insulating layer 11 may be referred to as a first gate insulating (GI 1) layer, the second insulating layer 12 may be referred to as a second gate insulating (GI 2) layer, the third insulating layer 13 may be referred to as an interlayer Insulating (ILD) layer, and the fourth insulating layer 14 may be referred to as a first planarization (PLN 1) layer.

In an exemplary embodiment, the material of the conductive layer may be a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), may be a single-layer structure, or a multi-layer composite structure such as Ti/Al/Ti, or the like.

In an exemplary embodiment, a material of the conductive layer may be a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), or the like.

In an exemplary embodiment, the material of the insulating layer may include any one or more of epoxy resin, phenolic resin, urea resin, melamine formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, and the like.

In an exemplary embodiment, the material of the insulating layer may include any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and the like, and may be a single layer, a multi-layer, or a composite layer.

In an exemplary embodiment, as shown in fig. 3, the light emitting structure layer 30 may include an anode layer, a pixel defining layer, an organic light emitting layer, and a cathode. The anode layer may include an anode 113 of the light emitting element, and the anode 113 is electrically connected to the pixel connection electrode 112. The pixel definition layer is provided with a pixel opening, the pixel opening exposes at least part of the surface of the anode 113, the organic light-emitting layer is at least partially arranged in the pixel opening, the organic light-emitting layer is connected with the anode 113, the cathode of the light-emitting element is arranged on the organic light-emitting layer, the cathode is connected with the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the driving of the anode 113 and the cathode.

In an exemplary embodiment, the encapsulation layer 40 may include more than two film layers. For example, the encapsulation layer 40 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, where the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, so that external moisture may not enter the light emitting structure layer 30.

Fig. 4 is a schematic partial cross-sectional view of a driving chip pin of a display substrate according to an embodiment of the utility model. As shown in fig. 4, in a plane perpendicular to the display substrate, the first frame region of the display substrate may include a substrate 10, a first insulating layer 11 located on a side of the substrate 10, a first conductive layer 11-1 located on a side of the first insulating layer 11 remote from the substrate 10, a second insulating layer 12 located on a side of the first conductive layer 11-1 remote from the substrate 10, a third insulating layer 13 located on a side of the second insulating layer 12 remote from the substrate 10, a third conductive layer 13-1 located on a side of the third insulating layer 13 remote from the substrate 10, a fourth conductive layer 14-1 located on a side of the third conductive layer 13-1 remote from the substrate 10, a fourth insulating layer 14 located on a side of the fourth conductive layer 14-1 remote from the substrate 10, a fifth insulating layer 15 located on a side of the fifth insulating layer 14-1 remote from the substrate 10, and a fifth conductive layer 15-1 located on a side of the fifth insulating layer 15 remote from the substrate 10. As shown in fig. 4, in the embodiment of the present utility model, the thickness direction of the display substrate is defined as a third direction, and the third direction is denoted as Z. In the embodiment of the present utility model, the first direction X, the second direction Y, and the third direction Z may be perpendicular to each other.

In the embodiment of the present utility model, in the first frame region of the display substrate, the conductive layer including the data line lead may be referred to as a first metal layer, the third conductive layer 13-1 may be referred to as a second metal layer, the fourth conductive layer 14-1 may be referred to as a third metal layer, and the fifth conductive layer 15-1 may be referred to as a fourth metal layer. In the embodiment of the present utility model, the film layer common to the first frame region and the display region has the same reference numerals, for example, the first insulating layer of the first frame region and the first insulating layer of the display region are both the first insulating layer 11, and the second insulating layer of the first frame region and the second insulating layer of the display region are both the second insulating layer 12. In the embodiment of the present utility model, the fifth conductive layer 15-1 located in the display area may be referred to as a touch layer, and the fifth insulating layer 15 may be referred to as a touch insulating layer. In this exemplary embodiment, the second insulating layer 12 located at the first frame region may be referred to as a first inorganic layer, and the third insulating layer 13 may be referred to as a second inorganic layer.

As shown in fig. 4, the first conductive layer 11-1 of the first frame region of the display substrate may include at least one data line lead 50. For example, the plurality of data line leads 50 may be arranged at intervals along the first direction X, which is also the line width direction of the data line leads 50 in the embodiment of the present utility model, and extend along the second direction Y. As shown in fig. 4, only one data line lead 50 is illustrated, and the data line lead 50 is illustrated as extending along the second direction Y. In the first frame region of the display substrate, the third conductive layer 13-1 may include at least one first connection electrode 51, the fourth conductive layer 14-1 may include at least one second connection electrode 52, the fifth conductive layer 15-1 may include at least one driving chip pin 53, and the driving chip pin 53 is connected to the data line lead 50 via the second connection electrode 52 and the first connection electrode 51, so that signal transmission may be achieved.

In an exemplary embodiment, as shown in fig. 4, the third conductive layer 13-1 of the first frame region of the display substrate may include at least one first connection electrode 51. A portion of the first connection electrode 51 is in contact with a portion of the data line lead 50 via a via hole located in the second insulating layer 12 and the third insulating layer 13. As shown in fig. 4, the second insulating layer 12 may be provided with at least one first via hole K1, the first via hole K1 penetrating the second insulating layer 12 in the thickness direction of the display substrate and exposing a portion of the surface of the data line lead 50 away from the side of the substrate 10. The orthographic projection of the data line lead 50 on the display substrate may include orthographic projection of the first via hole K1 on the display substrate, and the second insulating layer 12 may form protection on the edge of the data line lead 50, so as to prevent erosion of the data line lead caused by water and oxygen, and prolong the service life of the display substrate.

In an exemplary embodiment, as shown in fig. 4, the third insulating layer 13 may be provided with at least one second via hole K2, the second via hole K2 penetrating the third insulating layer 13 in the thickness direction of the display substrate and exposing a portion of the surface of the second insulating layer 12 on a side away from the substrate 10. The orthographic projection of the second via K2 on the display substrate may include an orthographic projection of the first via K1 on the display substrate, and the orthographic projection of the second via K2 on the display substrate is greater than the orthographic projection of the first via K1 on the display substrate. The orthographic projection of the second via K2 on the display substrate in the first direction X may include an orthographic projection of the data line lead 50 on the display substrate, and, for example, the orthographic projection of the second via K2 on the display substrate in the first direction X may be greater than an orthographic projection of the data line lead 50 on the display substrate. By limiting the relative relation between the apertures of the second via hole and the first via hole, the drop of the first connecting electrode along the thickness direction of the display substrate can be reduced, so that components (for example, a driving chip) in subsequent procedures are electrically connected with the pins of the driving chip in the first frame region, the problem of virtual connection can be avoided, the yield of the display substrate can be improved, and the reliability of the display substrate can be improved.

In an exemplary embodiment, as shown in fig. 4, at least a portion of the first connection electrode 51 may be located within the first via K1 and the second via K2. A portion of the first connection electrode 51 may be in contact connection with a portion of the surface of the data line lead 50 on a side remote from the substrate 10, and a portion of the first connection electrode 51 may be in contact connection with a portion of the surface of the second insulating layer 12 on a side remote from the substrate 10, and a portion of the first connection electrode 51 may be in contact connection with a portion of the surface of the third insulating layer 13 on a side remote from the substrate 10. As shown in fig. 4, the front projection of the first connection electrode 51 on the display substrate may include the front projection of the second via K2 on the display substrate.

In an exemplary embodiment, as shown in fig. 4, the fourth insulating layer 14 may be provided with at least one third via hole K3, and the third via hole K3 penetrates the fourth insulating layer 14 in the thickness direction of the display substrate.

In an exemplary embodiment, as shown in fig. 4, the fourth conductive layer 14-1 may include at least one second connection electrode 52, a portion of the second connection electrode 52 may be located within the third via K3, and the front projection of the fourth insulating layer 14 on the display substrate may include an edge of the front projection of the second connection electrode 52 on the display substrate. The second connection electrode 52 is in contact with the first connection electrode 51, and the orthographic projection of the second connection electrode 52 on the display substrate may include orthographic projection of the first connection electrode 51 on the display substrate, and for example, orthographic projection of the second connection electrode 52 on the display substrate may be greater than orthographic projection of the first connection electrode 51 on the display substrate.

In an exemplary embodiment, as shown in fig. 4, the fifth insulating layer 15 may be provided with at least one fourth via hole K4, the fourth via hole K4 penetrating the fifth insulating layer 15 in the thickness direction of the display substrate and exposing a portion of the surface of the second connection electrode 52 on the side away from the substrate 10. The orthographic projection of the fourth via K4 on the display substrate may be located within the range of the orthographic projection of the second connection electrode 52 on the display substrate.

In an exemplary embodiment, as shown in fig. 4, the fifth conductive layer 15-1 may include at least one driving chip pin 53, at least a portion of the driving chip pin 53 may be located within the fourth via K4, and for example, the orthographic projection of the driving chip pin 53 on the display substrate may include the orthographic projection of the fourth via K4 on the display substrate.

In an exemplary embodiment, as shown in fig. 4, the driving chip pins 53 have a groove structure 60, and the groove structure 60 is recessed toward one side of the substrate 10. The recess structure 60 is configured to receive a conductive paste, such as an anisotropic conductive paste, for electrically connecting the component to be mounted, which may be a driver chip (INTEGRATED CIRCUIT, IC), for example, to the data line lead 50. The driving chip may transfer signals to the data line leads 50 through the driving chip pins 53, and the data line leads 50 transfer signals to the data lines.

In an exemplary embodiment, as shown in FIG. 4, the groove structure 60 has a groove bottom 61, a groove top 62, and a groove wall 63. The groove bottom 61 and the groove top 62 may be disposed opposite to each other in the thickness direction of the display substrate, and the groove bottom 61 is closer to the substrate 10 than the groove top 62. The groove wall 63 may extend in a thickness direction of the display substrate, the groove wall 63 has oppositely disposed first and second ends, the first end of the groove wall 63 may be connected with the groove bottom 61, and the second end of the groove wall 63 may extend in a direction away from the substrate 10. The groove top 62 has a first end and a second end disposed opposite to each other, the first end of the groove top 62 may be connected to the second end of the groove wall 63, the second end of the groove top 62 extends away from the first end, the front projection of the groove top 62 on the display substrate may be annular, and the front projection of the groove top 62 on the display substrate may be annular or rectangular annular, for example.

In an exemplary embodiment, as shown in fig. 4, the groove bottom 61 and the groove top 62 have a distance H therebetween in the thickness direction of the display substrate, and the distance H may range from 0.55 micrometers to 0.65 micrometers. For example, distance H may be 0.63 microns, or distance H may be 0.60 microns, or distance H may be 0.55 microns. In the present embodiment, the distance H may also be referred to as the groove depth of the groove structure 60. According to the display substrate provided by the embodiment of the utility model, the groove depth of the groove structure is limited below 0.65 micrometers, so that a component to be mounted (for example, a driving chip) which is mounted later can be firmly connected with a data wire lead through the groove structure, the problem of virtual connection is avoided, and the use reliability of the display device can be improved.

In an exemplary embodiment, as shown in fig. 4, the second connection electrode 52 has a second sub-slot. The second sub-groove has a second groove bottom 521, a second groove top 522, and a second groove wall 523. The second groove bottom 521 and the second groove top 522 may be disposed opposite to each other in the thickness direction of the display substrate, and the second groove bottom 521 is closer to the substrate 10 than the second groove top 522. The second groove wall 523 may extend in the thickness direction of the display substrate, the second groove wall 523 has a first end and a second end disposed opposite to each other, the first end of the second groove wall 523 may be connected with the second groove bottom 521, and the second end of the second groove wall 523 may extend in a direction away from the substrate 10. The second groove top 522 has a first end and a second end disposed opposite to each other, the first end of the second groove top 522 may be connected to the second end of the second groove wall 523, the second end of the second groove top 522 extends away from the first end, the front projection of the second groove top 522 on the display substrate may be annular, and as an example, the front projection of the second groove top 522 on the display substrate may be annular or rectangular annular.

In an exemplary embodiment, as shown in fig. 4, the groove top 62 is in contact connection with the second groove top 522, and compared with a structure in which an insulating layer is provided between the groove top 62 and the second groove top 522, the contact connection of the groove top 62 and the second groove top 522 can reduce the groove depth of the groove structure 60, which is beneficial to the subsequent fixation of the component to be mounted (e.g., the driving chip), and can avoid the virtual connection of the component to be mounted.

In an exemplary embodiment, as shown in fig. 4, the first connection electrode 51 has a first sub-groove. The first sub-groove has a first groove bottom 511, a first groove top 512, and a first groove wall 513. The first groove bottom 511 and the first groove top 512 may be disposed opposite to each other in the thickness direction of the display substrate, and the first groove bottom 511 is closer to the substrate 10 than the first groove top 512. The first groove wall 513 may extend in a thickness direction of the display substrate, the first groove wall 513 may have a first end and a second end disposed opposite to each other, the first end of the first groove wall 513 may be connected to the first groove bottom 511, and the second end of the first groove wall 513 may extend in a direction away from the substrate 10. The first groove top 512 has a first end and a second end that are disposed opposite to each other, the first end of the first groove top 512 may be connected to the second end of the first groove wall 513, the second end of the first groove top 512 extends away from the first end, the front projection of the first groove top 512 on the display substrate may be annular, and as an example, the front projection of the first groove top 512 on the display substrate may be annular or rectangular annular.

In an exemplary embodiment, as shown in fig. 4, the first groove top 512 is in contact connection with the second groove top 522, and compared with a structure in which an insulating layer is disposed between the first groove top 512 and the second groove top 522, the contact connection between the first groove top 512 and the second groove top 522 can reduce the groove depth of the groove structure 60, which is beneficial to the subsequent fixation of the component to be mounted (e.g., the driving chip), and can avoid the virtual connection of the component to be mounted.

Fig. 5 is a schematic partial cross-sectional view of a driving chip pin of a display substrate according to an embodiment of the utility model. As shown in fig. 5, in a plane perpendicular to the display substrate, the first frame region of the display substrate may include the substrate 10, the first insulating layer 11 on the side of the substrate 10, the first conductive layer 11-1 on the side of the first insulating layer 11 away from the substrate 10, the second insulating layer 12 on the side of the first conductive layer 11-1 away from the substrate 10, the third conductive layer 13-1 on the side of the second insulating layer 12 away from the substrate 10, the fourth conductive layer 14-1 on the side of the third conductive layer 13-1 away from the substrate 10, the fourth insulating layer 14 on the side of the second insulating layer 12 away from the substrate 10, the fifth insulating layer 15 on the side of the fourth conductive layer 14-1 away from the substrate 10, and the fifth conductive layer 15-1 on the side of the fifth insulating layer 15 away from the substrate 10. The main structure of the driving chip pin shown in fig. 5 is substantially the same as that of the driving chip pin shown in fig. 4, except that the third insulating layer does not extend to the first frame region, so that the number of film layers in the first frame region can be reduced, and the film layer structure in the first frame region is optimized.

Fig. 6 is a schematic partial cross-sectional view of a driving chip pin of a display substrate according to an embodiment of the utility model. As shown in fig. 6, in a plane perpendicular to the display substrate, the first frame region of the display substrate may include the substrate 10, the first insulating layer 11 located on a side of the substrate 10, the first conductive layer 11-1 located on a side of the first insulating layer 11 away from the substrate 10, the second insulating layer 12 located on a side of the first conductive layer 11-1 away from the substrate 10, the third insulating layer 13 located on a side of the second insulating layer 12 away from the substrate 10, the third conductive layer 13-1 located on a side of the third insulating layer 13 away from the substrate 10, the fourth insulating layer 14 located on a side of the third insulating layer 13 away from the substrate 10, the fourth conductive layer 14-1 located on a side of the fourth insulating layer 14 away from the substrate 10, the fifth insulating layer 15 located on a side of the fifth insulating layer 14-1 away from the substrate 10, and the fifth conductive layer 15-1 located on a side of the fifth insulating layer 15 away from the substrate 10. The main structure of the driving chip pin shown in fig. 6 is substantially the same as that of the driving chip pin shown in fig. 4, except that the portion of the surface of the third conductive layer 13-1 on the side far from the substrate 10, which is close to the fourth insulating layer 14, is substantially flush with the portion of the surface of the fourth insulating layer 14 on the side far from the substrate 10, which is close to the third conductive layer 13-1, and the fourth conductive layer 14-1 is located on the side of the fourth insulating layer 14, which is far from the substrate 10, so that the process for preparing the third via hole K3 can be simplified, and the manufacturing cost of the display substrate can be reduced.

Fig. 7 is a schematic diagram showing a partial cross section of a driving chip pin of a display substrate according to an embodiment of the utility model. As shown in fig. 7, in a plane perpendicular to the display substrate, the first frame region of the display substrate may include the substrate 10, the first insulating layer 11 located on a side of the substrate 10, the first conductive layer 11-1 located on a side of the first insulating layer 11 away from the substrate 10, the second insulating layer 12 located on a side of the first conductive layer 11-1 away from the substrate 10, the third insulating layer 13 located on a side of the second insulating layer 12 away from the substrate 10, the third conductive layer 13-1 located on a side of the third insulating layer 13 away from the substrate 10, the fourth insulating layer 14 located on a side of the third insulating layer 13 away from the substrate 10, the fourth conductive layer 14-1 located on a side of the fourth insulating layer 14 away from the substrate 10, the fifth insulating layer 15 located on a side of the fourth insulating layer 14 away from the substrate 10, and the fifth conductive layer 15-1 located on a side of the fifth insulating layer 15 away from the substrate 10. The main structure of the driving chip pin shown in fig. 7 is substantially the same as that of the driving chip pin shown in fig. 6, except that the portion of the surface of the fourth conductive layer 14-1 on the side far from the substrate 10, which is close to the fifth insulating layer 15, is substantially flush with the portion of the surface of the fifth insulating layer 15 on the side far from the substrate 10, which is close to the fourth conductive layer 14-1, so that the process for preparing the fourth via K4 can be simplified, and the cost for preparing the display substrate can be reduced.

Fig. 8 is a schematic diagram of a partial cross section of a driving chip pin of a display substrate according to an embodiment of the utility model. As shown in fig. 8, in a plane perpendicular to the display substrate, the first frame region of the display substrate may include the substrate 10, the first insulating layer 11 on the side of the substrate 10, the first conductive layer 11-1 on the side of the first insulating layer 11 away from the substrate 10, the second insulating layer 12 on the side of the first conductive layer 11-1 away from the substrate 10, the third conductive layer 13-1 on the side of the second insulating layer 12 away from the substrate 10, the fourth insulating layer 14 on the side of the second insulating layer 12 away from the substrate 10, the fourth conductive layer 14-1 on the side of the fourth insulating layer 14 away from the substrate 10, the fifth insulating layer 15 on the side of the fourth insulating layer 14 away from the substrate 10, and the fifth conductive layer 15-1 on the side of the fifth insulating layer 15 away from the substrate 10. The main structure of the driving chip pins shown in fig. 8 is substantially the same as that of the driving chip pins shown in fig. 7, except that the third insulating layer does not extend to the first frame region, so that the film structure of the first frame region can be simplified.

An exemplary description will be made below by a manufacturing process of the display substrate. The patterning process disclosed by the utility model comprises the steps of coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and the like for organic materials, comprising the steps of coating organic materials, mask exposure, development and the like. The deposition can be any one or more of sputtering, vapor deposition and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink jet printing, and the etching can be any one or more of dry etching and wet etching, so that the utility model is not limited. "film" refers to a layer of film formed by depositing, coating, or other process a material on a substrate. The "film" may also be referred to as a "layer" if the "film" does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" prior to the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The utility model relates to a method for forming a display substrate, which comprises the steps of forming a film layer on a substrate, forming a first layer of the film layer, forming a second layer of the film layer, and forming a third layer of the film layer. In an exemplary embodiment of the present utility model, "the front projection of B is within the range of the front projection of a" or "the front projection of a includes the front projection of B" means that the boundary of the front projection of B falls within the boundary range of the front projection of a or the boundary of the front projection of a overlaps with the boundary of the front projection of B.

Taking the structure of the driving chip pins of the display substrate shown in fig. 4 as an example, the manufacturing process of the driving chip pins of the display substrate may include the following steps (11) to (17):

(11) A first conductive layer pattern is formed. Forming the first conductive layer pattern may include: a first insulating film and a first conductive film are sequentially deposited on one side of the substrate 10, and the first conductive film is patterned by a patterning process to form a first insulating layer 11 on one side of the substrate 10 and a first conductive layer pattern on one side of the first insulating layer 11. The first conductive layer 11-1 may include at least one data line lead 50, as shown in fig. 9A.

(12) And forming a third insulating layer pattern. Forming the third insulating layer pattern may include: a second insulating film and a third insulating film are sequentially deposited on the side of the substrate 10 on which the foregoing patterns are formed, and the third insulating film is patterned by a patterning process of a Half Tone Mask (Half Tone Mask) to form a second insulating layer pattern on the side of the first conductive layer 11-1 and a third insulating layer pattern on the side of the second insulating layer pattern, as shown in fig. 9B.

As shown in fig. 9B, the second insulating layer 12 may have at least one first via hole K1, and the first via hole K1 penetrates the second insulating layer 12 in the thickness direction of the display substrate and exposes a portion of the surface of the data line lead 50 on the side away from the substrate 10. The orthographic projection of the data line lead 50 on the display substrate may include orthographic projection of the first via K1 on the display substrate, and the second insulating layer 12 may form protection for the edge of the data line lead 50. The first via K1 may be a circular hole or an elliptical hole or a rectangular hole or a hexagonal hole, etc.

As shown in fig. 9B, the third insulating layer 13 may have at least one second via hole K2, and the second via hole K2 penetrates the third insulating layer 13 in the thickness direction of the display substrate and exposes a portion of the surface of the second insulating layer 12 on a side away from the substrate 10. The orthographic projection of the second via K2 on the display substrate may include an orthographic projection of the first via K1 on the display substrate, and the orthographic projection of the second via K2 on the display substrate is greater than the orthographic projection of the first via K1 on the display substrate. The orthographic projection of the second via K2 on the display substrate in the first direction X may include an orthographic projection of the data line lead 50 on the display substrate, and, for example, the orthographic projection of the second via K2 on the display substrate in the first direction X may be greater than an orthographic projection of the data line lead 50 on the display substrate. By limiting the relative relation between the apertures of the second via hole and the first via hole, the drop of the first connecting electrode formed subsequently along the thickness direction of the display substrate can be reduced, so that the conductive connection between a component to be mounted (for example, a driving chip) and a driving chip pin of the first frame region in the subsequent process is facilitated, and the problem of virtual connection can be avoided.

(13) And forming a third conductive layer pattern. Forming the third conductive layer pattern may include: a third conductive film is deposited on the side of the substrate 10 where the foregoing patterns are formed, and is patterned by a patterning process to form a third conductive layer pattern on the side of the third insulating layer 13, as shown in fig. 9C. The third conductive layer 13-1 may include at least one first connection electrode 51.

As shown in fig. 9C, at least a portion of the first connection electrode 51 may be located within the first via K1 and the second via K2. The first connection electrode 51 has a first sub-groove. The first sub-groove has a first groove bottom 511, a first groove top 512, and a first groove wall 513. The first groove bottom 511 and the first groove top 512 may be disposed opposite to each other in the thickness direction of the display substrate, and the first groove bottom 511 is closer to the substrate 10 than the first groove top 512. The first groove wall 513 may extend in a thickness direction of the display substrate, the first groove wall 513 may have a first end and a second end disposed opposite to each other, the first end of the first groove wall 513 may be connected to the first groove bottom 511, and the second end of the first groove wall 513 may extend in a direction away from the substrate 10. The first groove top 512 has a first end and a second end disposed opposite to each other, the first end of the first groove top 512 may be connected to the second end of the first groove wall 513, the second end of the first groove top 512 extends away from the first end, and the front projection of the first groove top 512 on the display substrate may be annular.

As shown in fig. 9C, the first groove top 512 may contact with the surface of the second insulating layer 12 on the side far from the substrate 10, and as described above, the relative relationship between the apertures of the second via K2 and the first via K1 is defined, so that the distance between the first groove top 512 and the first groove bottom 511 along the thickness direction of the display substrate can be reduced, and the groove depth of the groove structure formed later can be reduced.

(14) And forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: a fourth conductive film is deposited on the side of the substrate 10 where the aforementioned pattern is formed, and patterned by a patterning process to form a fourth conductive layer pattern on the side of the third conductive layer 13-1, as shown in fig. 9D.

As shown in fig. 9D, the fourth conductive layer 14-1 may include at least one second connection electrode 52. The second connection electrode 52 has a second sub-slot. The second sub-groove has a second groove bottom 521, a second groove top 522, and a second groove wall 523. The second groove bottom 521 and the second groove top 522 may be disposed opposite to each other in the thickness direction of the display substrate, and the second groove bottom 521 is closer to the substrate 10 than the second groove top 522. The second groove wall 523 may extend in the thickness direction of the display substrate, the second groove wall 523 has a first end and a second end disposed opposite to each other, the first end of the second groove wall 523 may be connected with the second groove bottom 521, and the second end of the second groove wall 523 may extend in a direction away from the substrate 10. The second groove top 522 has a first end and a second end disposed opposite to each other, the first end of the second groove top 522 may be connected to the second end of the second groove wall 523, the second end of the second groove top 522 extends away from the first end, and the front projection of the second groove top 522 on the display substrate may be annular.

As shown in fig. 9D, the second groove top 522 may be in contact with the first groove top 512, so that the groove depth of the groove structure formed later may be reduced, the virtual connection between the component to be mounted (e.g., the driving chip) and the data line lead 50 may be avoided, and the reliability of the display substrate may be improved.

(15) And forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: a fourth insulating film is deposited on the side of the substrate 10 on which the foregoing patterns are formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer pattern on the side of the fourth conductive layer 14-1, as shown in fig. 9E.

As shown in fig. 9E, the fourth insulating layer 14 has at least one third via K3, and the third via K3 exposes a portion of the surface of the second connection electrode 52 on the side away from the substrate 10. The fourth insulating layer 14 can protect the edge of the second connection electrode 52, and can improve the resistance of the second connection electrode to water and oxygen.

(16) A fifth insulating layer pattern is formed. Forming the fifth insulating layer pattern may include: a fifth insulating film is deposited on the side of the substrate 10 on which the foregoing patterns are formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer pattern on the side of the fourth conductive layer 14-1, as shown in fig. 9F.

As shown in fig. 9F, the fifth insulating layer 15 may be provided with at least one fourth via K4, the fourth via K4 penetrating the fifth insulating layer 15 in the thickness direction of the display substrate and exposing a portion of the surface of the second connection electrode 52 on the side away from the substrate 10. The orthographic projection of the fourth via K4 on the display substrate may be located within the range of the orthographic projection of the second connection electrode 52 on the display substrate.

(17) And forming a fifth conductive layer pattern. Forming the fifth conductive layer pattern may include: a fifth conductive film is deposited on the side of the substrate 10 on which the foregoing patterns are formed, and is patterned by a patterning process to form a fifth conductive layer pattern on the side of the fifth insulating layer 15, as shown in fig. 9G.

As shown in fig. 9G, the fifth conductive layer 15-1 may include at least one driving chip pin 53, at least a portion of the driving chip pin 53 may be located within the fourth via K4, and for example, the orthographic projection of the driving chip pin 53 on the display substrate may include the orthographic projection of the fourth via K4 on the display substrate.

As shown in fig. 9G, the driving chip pins 53 have a groove structure 60, and the groove structure 60 is recessed toward one side of the substrate 10. The recess structure 60 is configured to accommodate conductive glue or the like for making electrical connection of the component to be mounted, which may be a driver chip (INTEGRATED CIRCUIT, IC), for example, with the data line leads 50. The driver chip is electrically connected to the data line leads 50 via the recess structures 60.

The groove structure 60 has a groove bottom 61, a groove top 62 and groove walls 63. The groove bottom 61 and the groove top 62 may be disposed opposite to each other in the thickness direction of the display substrate, and the groove bottom 61 is closer to the substrate 10 than the groove top 62. The groove wall 63 may extend in a thickness direction of the display substrate, the groove wall 63 has oppositely disposed first and second ends, the first end of the groove wall 63 may be connected with the groove bottom 61, and the second end of the groove wall 63 may extend in a direction away from the substrate 10. The groove top 62 has a first end and a second end disposed opposite to each other, the first end of the groove top 62 may be connected to the second end of the groove wall 63, the second end of the groove top 62 extends away from the first end, and an orthographic projection of the groove top 62 on the display substrate may be annular. The groove depth H of the groove structure 60 may be between 0.60 microns and 0.65 microns.

Fig. 10 is a schematic partial cross-sectional view of a driving chip pin of a display substrate according to another embodiment of the utility model. As shown in fig. 10, in a plane perpendicular to the display substrate, the first frame region of the display substrate may include a substrate 10, a first insulating layer 11 on a side of the substrate 10, a second insulating layer 12 on a side of the first insulating layer 11 away from the substrate 10, a second conductive layer 12-1 on a side of the second insulating layer 12 away from the substrate 10, a third insulating layer 13 on a side of the second conductive layer 12-1 away from the substrate 10, a third conductive layer 13-1 on a side of the third insulating layer 13 away from the substrate 10, a fourth conductive layer 14-1 on a side of the third conductive layer 13-1 away from the substrate 10, a fourth insulating layer 14 on a side of the fourth conductive layer 14-1 away from the substrate 10, a fifth insulating layer 15 on a side of the fifth insulating layer 14-1 away from the substrate 10, and a fifth conductive layer 15-1 on a side of the fifth insulating layer 15 away from the substrate 10.

As shown in fig. 10, the second conductive layer 12-1 of the first frame region of the display substrate may include at least one data line lead 50. For example, the plurality of data line leads 50 may be spaced apart along the first direction X and extend along the second direction Y. As shown in fig. 10, only one data line lead 50 is illustrated, and the data line lead 50 is illustrated as extending along the second direction Y. In the first frame region of the display substrate, the third conductive layer 13-1 may include at least one first connection electrode 51, the fourth conductive layer 14-1 may include at least one second connection electrode 52, the fifth conductive layer 15-1 may include at least one driving chip pin 53, and the driving chip pin 53 is connected to the data line lead 50 via the second connection electrode 52 and the first connection electrode 51, so that signal transmission may be achieved.

In an exemplary embodiment, as shown in fig. 10, the third conductive layer 13-1 of the first frame region of the display substrate may include at least one first connection electrode 51. A portion of the first connection electrode 51 is in contact with a portion of the data line lead 50 via a via hole located in the third insulating layer 13. As shown in fig. 10, the third insulating layer 13 may be provided with at least one second via hole K2, the second via hole K2 penetrating the third insulating layer 13 in the thickness direction of the display substrate and exposing a portion of the surface of the data line lead 50 away from the side of the substrate 10. The orthographic projection of the data line lead 50 on the display substrate may include orthographic projection of the second via hole K2 on the display substrate, and the third insulating layer 13 may form protection on the edge of the data line lead 50, so as to prevent erosion of the data line lead caused by water and oxygen, and prolong the service life of the display substrate. The other structure of the driving chip pin shown in fig. 10 can refer to the description of the structure of the driving chip pin shown in fig. 4, and the description thereof will not be repeated here.

Fig. 11 is a schematic partial cross-sectional view of a driving chip pin of a display substrate according to another embodiment of the utility model. As shown in fig. 11, in a plane perpendicular to the display substrate, the first frame region of the display substrate may include the substrate 10, the first insulating layer 11 located on a side of the substrate 10, the first conductive layer 11-1 located on a side of the first insulating layer 11 remote from the substrate 10, the second conductive layer 12-1 located on a side of the first conductive layer 11-1 remote from the substrate 10, the third insulating layer 13 located on a side of the second conductive layer 12-1 remote from the substrate 10, the third conductive layer 13-1 located on a side of the third insulating layer 13 remote from the substrate 10, the fourth conductive layer 14-1 located on a side of the third conductive layer 13-1 remote from the substrate 10, the fourth insulating layer 14 located on a side of the fourth conductive layer 14-1 remote from the substrate 10, the fifth insulating layer 15 located on a side of the fifth insulating layer 14-1 remote from the substrate 10, and the fifth conductive layer 15-1 located on a side remote from the substrate 10. In this embodiment, the first conductive layer 11-1 located in the first frame region may be referred to as a fill-in layer.

As shown in fig. 11, the first conductive layer 11-1 may include at least one filling block 70, and the filling block 70 may have a rectangular block shape or the like. In the embodiment of the present utility model, only one compensation block 70 is illustrated as an example. The second conductive layer 12-1 may include at least one data line lead 50, and illustratively, a plurality of data line leads 50 may be spaced apart along the first direction X and extend along the second direction Y. As shown in fig. 11, only one data line lead 50 is illustrated, and the data line lead 50 is illustrated as extending along the second direction Y. In the first frame region of the display substrate, the third conductive layer 13-1 may include at least one first connection electrode 51, the fourth conductive layer 14-1 may include at least one second connection electrode 52, the fifth conductive layer 15-1 may include at least one driving chip pin 53, and the driving chip pin 53 is connected to the data line lead 50 via the second connection electrode 52 and the first connection electrode 51, so that signal transmission may be achieved.

As shown in fig. 11, the front projection of the data line lead 50 on the display substrate may include the front projection of the compensation block 70 on the display substrate, and for example, the front projection of the data line lead 50 on the display substrate may be larger than the front projection of the compensation block 70 on the display substrate. The third insulating layer 13 has at least one second via K2, and the orthographic projection of the second via K2 on the display substrate is located within the orthographic projection of the data line lead 50 on the display substrate. As shown in fig. 11, the surface of the side, away from the substrate 10, of the data line lead 50 is flush with the surface of the side, away from the substrate 10, of the third insulating layer 13, and the set level compensating block 70 can compensate the drop of the data line lead 50 and the third insulating layer 13 along the thickness direction of the display substrate, which is favorable for flattening the first connecting electrode and the second connecting electrode formed subsequently, can shorten the groove depth H of the groove structure formed subsequently, avoid the occurrence of virtual connection between the component to be mounted (e.g., the driving chip) and the display substrate, and can improve the use reliability of the display device.

In an exemplary embodiment, as shown in fig. 11, the third conductive layer 13-1 of the first frame region of the display substrate may include at least one first connection electrode 51. A portion of the first connection electrode 51 is in contact with a portion of the data line lead 50 via the second via hole K2 located in the third insulating layer 13. As shown in fig. 11, the first connection electrode 51 may have a rectangular block shape.

In an exemplary embodiment, as shown in fig. 11, in the first direction X, the front projection of the first connection electrode 51 on the display substrate may include the front projection of the data line lead 50 on the display substrate. The first connection electrode 51 can prevent the erosion of the data line lead 50 by water oxygen, and can improve the reliability of the display substrate.

In an exemplary embodiment, as shown in fig. 11, the fourth conductive layer 14-1 of the first frame region of the display substrate may include at least one second connection electrode 52. A portion of the second connection electrode 52 is in contact with a portion of the first connection electrode 51 via the third via hole K3 located in the fourth insulating layer 14. As shown in fig. 11, the second connection electrode 52 may have a rectangular block shape. The orthographic projection of the second connection electrode 52 on the display substrate may include the orthographic projection of the first connection electrode 51 on the display substrate.

In an exemplary embodiment, as shown in fig. 11, the fifth conductive layer 15-1 of the first frame region of the display substrate may include at least one driving chip pin 53. A portion of the driving chip pin 53 is in contact connection with a portion of the second connection electrode 52 via a fourth via K4 located in the fifth insulating layer 15. The front projection of the driving chip pin 53 on the display substrate may be located within the range of the front projection of the second connection electrode 52 on the display substrate.

In an exemplary embodiment, as shown in fig. 11, the driving chip pins 53 have a groove structure 60, and the groove structure 60 is recessed toward one side of the substrate 10. The groove structure 60 is configured to receive conductive paste for electrical connection of a component to be mounted (e.g., a driver chip) with the data line lead 50. The groove structure 60 can play a limiting role on the conductive particles in the conductive adhesive, after the part to be installed is assembled in place on the display substrate, the conductive particles are extruded by the part to be installed, so that the conductive particles can be stably kept in the groove structure 60, good connectivity between the part to be installed and the display substrate can be ensured, and the reliability of the display substrate can be improved.

In an exemplary embodiment, as shown in FIG. 11, the groove structure 60 has a groove bottom 61, a groove top 62, and a groove wall 63. The groove bottom 61 and the groove top 62 may be disposed opposite to each other in the thickness direction of the display substrate, and the groove bottom 61 is closer to the substrate 10 than the groove top 62. The groove wall 63 may extend in a thickness direction of the display substrate, the groove wall 63 has oppositely disposed first and second ends, the first end of the groove wall 63 may be connected with the groove bottom 61, and the second end of the groove wall 63 may extend in a direction away from the substrate 10. The groove top 62 has a first end and a second end disposed opposite to each other, the first end of the groove top 62 may be connected to the second end of the groove wall 63, the second end of the groove top 62 extends away from the first end, the front projection of the groove top 62 on the display substrate may be annular, and the front projection of the groove top 62 on the display substrate may be annular or rectangular annular, for example.

In an exemplary embodiment, as shown in fig. 11, the groove bottom 61 and the groove top 62 have a distance H therebetween in the thickness direction of the display substrate, that is, the groove depth of the groove structure 60, and the distance H may range from 0.40 micrometers to 0.55 micrometers. For example, the distance H may be 0.50 microns, or the distance H may be 0.45 microns.

Fig. 12 is a schematic partial cross-sectional view of a driving chip pin of a display substrate according to another embodiment of the utility model. As shown in fig. 12, in a plane perpendicular to the display substrate, the first frame region of the display substrate may include the substrate 10, the first insulating layer 11 located on a side of the substrate 10, the first conductive layer 11-1 located on a side of the first insulating layer 11 remote from the substrate 10, the second conductive layer 12-1 located on a side of the first conductive layer 11-1 remote from the substrate 10, the third insulating layer 13 located on a side of the second conductive layer 12-1 remote from the substrate 10, the third conductive layer 13-1 located on a side of the third insulating layer 13 remote from the substrate 10, the fourth conductive layer 14-1 located on a side of the third conductive layer 13-1 remote from the substrate 10, the fourth insulating layer 14 located on a side of the fourth conductive layer 14-1 remote from the substrate 10, the fifth insulating layer 15 located on a side of the fifth insulating layer 14-1 remote from the substrate 10, and the fifth conductive layer 15-1 located on a side remote from the substrate 10. As shown in fig. 12, the first conductive layer 11-1 may include at least one data line lead 50. The second conductive layer 12-1 may include at least one compensation block 70, in this embodiment, the second conductive layer 12-1 located in the first frame region may be referred to as a compensation layer, and other structures of the driving chip pins may refer to the foregoing description about the driving chip pin structure shown in fig. 11, which is not further described herein.

Taking the structure of the driving chip pins of the display substrate shown in fig. 12 as an example, the manufacturing process of the driving chip pins of the display substrate may include the following steps (21) to (28):

(21) A first conductive layer pattern is formed. Forming the first conductive layer pattern may include: a first insulating film and a first conductive film are sequentially deposited on one side of the substrate 10, and the first conductive film is patterned by a patterning process to form a first insulating layer 11 on one side of the substrate 10 and a first conductive layer pattern on one side of the first insulating layer 11. The first conductive layer 11-1 may include at least one data line lead 50, as shown in fig. 13A.

(22) And forming a second conductive layer pattern. Forming the second conductive layer pattern may include: a second conductive film is deposited on one side of the substrate 10 on which the foregoing patterns are formed, and is patterned by a patterning process to form a second conductive layer pattern on one side of the first conductive layer 11-1, as shown in fig. 13B.

As shown in fig. 13B, the second conductive layer 12-1 may include at least one fill-in bump 70. In the first direction X, the orthographic projection of the patch panel 70 on the display substrate may include the orthographic projection of the data line lead 50 on the display substrate.

(23) And forming a third insulating layer pattern. Forming the third insulating layer pattern may include: a third insulating film is deposited on the side of the substrate 10 where the foregoing patterns are formed, and the third insulating film is patterned by a patterning process to form a third insulating layer pattern on the side of the second conductive layer 12-1, as shown in fig. 13C.

As shown in fig. 13C, the third insulating layer 13 may include at least one second via K2, where the second via K2 penetrates through the thickness of the third insulating layer 13, and exposes at least a portion of the surface of the complementary flat block 70 on the side away from the substrate 10. The surface of the filling block 70 on the side away from the substrate 10 may be flush with the surface of the third insulating layer 13 on the side away from the substrate 10.

(24) And forming a third conductive layer pattern. Forming the third conductive layer pattern may include: a third conductive film is deposited on the side of the substrate 10 where the foregoing patterns are formed, and is patterned by a patterning process to form a third conductive layer pattern on the side of the third insulating layer 13, as shown in fig. 13D.

As shown in fig. 13D, the third conductive layer 13-1 may include at least one first connection electrode 51, and a portion of the first connection electrode 51 may be in contact with a portion of the filling-up block 70 via a second via K2 located in the third insulating layer 13. The first connection electrode 51 may have a rectangular block shape. In the first direction X, the front projection of the first connection electrode 51 on the display substrate may include the front projection of the patch 70 on the display substrate.

(25) And forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: a fourth conductive film is deposited on the side of the substrate 10 where the aforementioned pattern is formed, and patterned by a patterning process to form a fourth conductive layer pattern on the side of the third conductive layer 13-1, as shown in fig. 13E.

As shown in fig. 13E, the fourth conductive layer 14-1 may include at least one second connection electrode 52, and the second connection electrode 52 is in contact with a side surface of the first connection electrode 51 remote from the substrate 10. The orthographic projection of the second connection electrode 52 on the display substrate may include the orthographic projection of the first connection electrode 51 on the display substrate.

(26) And forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: a fourth insulating film is deposited on the side of the substrate 10 on which the foregoing patterns are formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer pattern on the side of the fourth conductive layer 14-1, as shown in fig. 13F.

As shown in fig. 13F, the fourth insulating layer 14 may include at least one third via K3, where the third via K3 exposes at least a portion of a surface of the second connection electrode 52 on a side away from the substrate 10.

(27) A fifth insulating layer pattern is formed. Forming the fifth insulating layer pattern may include: a fifth insulating film is deposited on the side of the substrate 10 where the aforementioned patterns are formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer pattern on the side of the fourth conductive layer 14-1, as shown in fig. 13G.

As shown in fig. 13G, the fifth insulating layer 15 may include at least one fourth via K4, the fourth via K4 penetrating the fifth insulating layer 15 in the thickness direction of the display substrate and exposing a portion of the surface of the second connection electrode 52 on a side away from the substrate 10. The fourth via K4 connects the subsequently formed driving chip pin with the second connection electrode 52 through the via.

(28) And forming a fifth conductive layer pattern. Forming the fifth conductive layer pattern may include: a fifth conductive film is deposited on the side of the substrate 10 where the aforementioned pattern is formed, and is patterned by a patterning process to form a fifth conductive layer pattern on the side of the fifth insulating layer 15, as shown in fig. 13H.

As shown in fig. 13H, the fifth conductive layer 15-1 may include at least one driving chip pin 53, a portion of the driving chip pin 53 may be located in the fourth via K4, and the driving chip pin 53 and the second connection electrode 52 are connected through the fourth via K4.

Fig. 14 is a schematic partial cross-sectional view of a display device according to an embodiment of the utility model. As shown in fig. 14, the display device includes a display substrate, a conductive paste 80, and a component to be mounted. By way of example, the component to be mounted may be an electrical component conventional in the display field. In the embodiment of the present utility model, the component to be mounted is taken as an example of the driving chip 90 (INTEGRATED CIRCUIT, IC). The driving chip 90 may be connected to the driving chip pins 53 of the first frame region of the display substrate through the conductive adhesive 80, and fig. 14 is a schematic partial cross-sectional view of the driving chip pins of the first frame region of the display device.

As shown in fig. 14, the conductive adhesive 80 may include a plurality of conductive particles, and part of the conductive particles may be located in the groove structure 60 of the first frame region, and after the driving chip 90 is assembled in place, the conductive particles may be pressed between the driving chip 90 and the groove structure 60, so that the driving chip 90 and the display substrate have good electrical connectivity, and defects such as dark lines in the first frame region are avoided, and reliability of the display device may be improved.

Another embodiment of the present utility model provides a display device, including a display substrate as described in any one of the above embodiments. The display device may be: the embodiment of the utility model is not limited to any product or component with display function such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

Although the embodiments of the present utility model are described above, the embodiments are only used for facilitating understanding of the present utility model, and are not intended to limit the present utility model. It should be noted that the above-described examples or implementations are merely exemplary and not limiting. Accordingly, the utility model is not limited to what has been particularly shown and described herein. Various modifications, substitutions, or omissions may be made in the form and details of the embodiments without departing from the scope of the utility model.

Claims

1. A display substrate, comprising:

A plurality of sub-pixels located in the display area;

2. The display substrate according to claim 1, wherein the first frame region includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer which are sequentially stacked on one side of the substrate in a plane perpendicular to the display substrate; the first metal layer comprises the plurality of data line leads, and the fourth metal layer comprises the plurality of driving chip pins.

3. The display substrate of claim 2, wherein the first frame region further comprises at least one insulating layer in a plane perpendicular to the display substrate, the at least one insulating layer being located between the first metal layer and the second metal layer; the second metal layer comprises at least one connecting electrode, and part of the connecting electrode is positioned in the through hole of the at least one insulating layer and is in contact connection with the surface of the data line lead far away from one side of the substrate.

4. The display substrate of claim 3, wherein the at least one insulating layer comprises a first inorganic layer and a second inorganic layer, and the second inorganic layer is farther from the substrate than the first inorganic layer; in the line width direction of the data line lead, the orthographic projection of the via hole arranged on the first inorganic layer on the display substrate is positioned in the orthographic projection of the data line lead on the display substrate, the orthographic projection of the via hole arranged on the second inorganic layer on the display substrate comprises the orthographic projection of the data line lead on the display substrate, and the orthographic projection of the via hole arranged on the second inorganic layer on the display substrate is larger than the orthographic projection of the data line lead on the display substrate.

5. A display substrate according to claim 3, wherein one insulating layer is arranged between the first metal layer and the second metal layer, and the orthographic projection of the via hole arranged on the insulating layer on the display substrate is positioned in the orthographic projection of the data line lead on the display substrate in the line width direction of the data line lead.

6. The display substrate according to any one of claims 2 to 5, wherein the display region includes a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer which are disposed in this order on one side of the substrate in a plane perpendicular to the display substrate; the first metal layer and the first gate metal layer are of the same layer structure, the second metal layer and the first source drain metal layer are of the same layer structure, and the third metal layer and the second source drain metal layer are of the same layer structure.

7. The display substrate according to any one of claims 2 to 5, wherein the display region includes a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer which are disposed in this order on one side of the substrate in a plane perpendicular to the display substrate; the first metal layer and the second gate metal layer are of the same layer structure, the second metal layer and the first source drain metal layer are of the same layer structure, and the third metal layer and the second source drain metal layer are of the same layer structure.

8. The display substrate according to any one of claims 2 to 5, wherein the second metal layer comprises at least one first connection electrode and the third metal layer comprises at least one second connection electrode; at least part of the surface of the second connecting electrode far away from one side of the substrate is in contact connection with the groove structure of the driving chip pin, and part of the surface of the first connecting electrode near one side of the substrate is in contact connection with the data line lead.

9. The display substrate of claim 8, wherein the first connection electrode has a first sub-slot, the second connection electrode has a second sub-slot, the groove structure of the driving chip pin is located within the front projection of the second sub-slot on the display substrate in front of the display substrate, and the front projection of the second sub-slot is located within the front projection of the first sub-slot on the display substrate in front of the display substrate.

10. The display substrate of claim 2, wherein the first frame region further comprises a fill-in layer in a plane perpendicular to the display substrate, the fill-in layer being located between the substrate and the first metal layer; the compensation layer comprises at least one compensation block; and in the line width direction of the data line lead, the orthographic projection of the data line lead on the display substrate comprises the orthographic projection of the compensation block on the display substrate.

11. The display substrate of claim 2, wherein the first frame region further comprises a fill-in layer in a plane perpendicular to the display substrate, the fill-in layer being located between the first metal layer and the second metal layer, the fill-in layer comprising at least one fill-in block; and in the line width direction of the data line lead, the orthographic projection of the compensation block on the display substrate comprises orthographic projection of the data line lead on the display substrate, and the data line lead is electrically connected with the groove structure of the driving chip pin through the compensation block.

12. The display substrate of claim 10 or 11, wherein the first frame region further comprises at least one insulating layer in a plane perpendicular to the display substrate, the at least one insulating layer being located between the first metal layer and the second metal layer, and a surface of the at least one insulating layer on a side away from the substrate is flush with a surface of the data line lead and the repair block on a side away from the substrate.

13. The display substrate of claim 12, wherein the second metal layer comprises at least one first connection electrode and the third metal layer comprises at least one second connection electrode; the data line lead is connected with the groove structure of the driving chip pin through the first connecting electrode and the second connecting electrode;

14. The display substrate according to claim 13, wherein a surface of the second connection electrode on a side away from the substrate is a plane.

15. The display substrate according to claim 10 or 11, wherein the display region includes a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer which are provided in this order on one side of the substrate in a plane perpendicular to the display substrate; the second metal layer and the first source drain metal layer are of the same layer structure, and the third metal layer and the second source drain metal layer are of the same layer structure;

16. A display device comprising the display substrate according to any one of claims 1 to 15.