CN216719948U

CN216719948U - Display substrate and display device

Info

Publication number: CN216719948U
Application number: CN202122408141.5U
Authority: CN
Inventors: 易宏; 张跳梅
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-09-29
Filing date: 2021-09-29
Publication date: 2022-06-10
Anticipated expiration: 2031-09-29

Abstract

A display substrate and a display device are provided, wherein the display substrate comprises a substrate, a semiconductor layer, a fourth conducting layer, a second flat layer and an anode layer which are sequentially arranged on the substrate; the semiconductor layer comprises an active layer of a plurality of transistors, the fourth conducting layer comprises a first anode connecting electrode and a second anode connecting electrode, the second flat layer comprises a first opening and a second opening, the anode layer comprises a first anode and a second anode, the first anode connecting electrode is connected with the first anode through the first opening, and the second anode connecting electrode is connected with the second anode through the second opening; the orthographic projection area of the first anode connecting electrode on the substrate is larger than that of the second anode connecting electrode on the substrate, and the orthographic projection area of the first opening on the substrate is larger than that of the second opening on the substrate. The light transmittance is improved, the light emitting efficiency of the light emitting device is improved, and the power consumption is saved.

Description

Display substrate and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and particularly relates to a display substrate and a display device.

Background

Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, very high response speed, thinness, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and using a Thin Film Transistor (TFT) for signal control has become a mainstream product in the Display field.

Disclosure of Invention

The embodiment of the disclosure provides a display substrate and a display device, which can improve the display effect.

An embodiment of the present disclosure provides a display substrate, including: the semiconductor layer, the fourth conducting layer, the second flat layer and the anode layer are sequentially arranged on the substrate;

the semiconductor layer includes active layers of a plurality of transistors, the fourth conductive layer includes a first anode connection electrode and a second anode connection electrode, the second flat layer includes a first opening and a second opening, the anode layer includes a first anode and a second anode, the first anode connection electrode is connected to the first anode through the first opening, and the second anode connection electrode is connected to the second anode through the second opening;

the orthographic projection area of the first anode connecting electrode on the substrate is larger than that of the second anode connecting electrode on the substrate, and the orthographic projection area of the first opening on the substrate is larger than that of the second opening on the substrate.

In an exemplary embodiment, the first anode connection electrode includes an electrode main body portion and an electrode protrusion portion provided on the electrode main body portion, wherein:

the orthographic projection of the electrode main body part on the substrate and the orthographic projection of the first anode on the substrate have an overlapping region, and the orthographic projection of the electrode convex part on the substrate and the orthographic projection of the first anode on the substrate have no overlapping region.

In an exemplary embodiment, a third conductive layer is further disposed on the substrate, the third conductive layer further including a plurality of first connection electrodes, and an orthogonal projection of the electrode protrusions on the substrate and an orthogonal projection of the first connection electrodes on the substrate have an overlapping region, wherein:

in the plane perpendicular to display substrate, display substrate still includes the first flat layer of setting between third conducting layer and fourth conducting layer, the electrode boss pass through via hole on the first flat layer with first connecting electrode is connected.

In an exemplary embodiment, there is an overlapping region between an orthogonal projection of the second anode connection electrode on the substrate and an orthogonal projection of the first connection electrode on the substrate, and the second anode connection electrode is connected to the first connection electrode through a via hole on the first flat layer.

In an exemplary embodiment, the second anode includes an anode main body portion and an anode protruding portion disposed on the anode main body portion, an orthogonal projection of the anode main body portion on the substrate and an orthogonal projection of the second anode connection electrode on the substrate do not have an overlapping region, an orthogonal projection of the anode protruding portion on the substrate and an orthogonal projection of the second anode connection electrode on the substrate have an overlapping region, and the second anode connection electrode is connected to the anode protruding portion through the second opening.

In an exemplary embodiment, the display substrate includes a plurality of pixel units, at least one of the pixel units includes a plurality of sub-pixels, at least one of the sub-pixels includes a circuit unit and a light emitting device, at least one of the light emitting devices includes a red light emitting device emitting red light, a blue light emitting device emitting blue light, and a green light emitting device emitting green light, at least one of the circuit units includes a first circuit unit connected to the red light emitting device, a second circuit unit connected to the blue light emitting device, and a third circuit unit connected to the green light emitting device;

the first circuit unit includes a first anode connection electrode, and the red light emitting device includes a first anode; the second circuit unit includes a second anode connection electrode; the third circuit unit includes a second anode connection electrode, and the blue light emitting device and/or the green light emitting device includes a second anode.

In an exemplary embodiment, at least one of the pixel units includes one first circuit unit, one second circuit unit, and two third circuit units, the plurality of circuit units form a plurality of unit rows and a plurality of unit columns, the unit columns include a first unit column and a second unit column, the first unit column includes a plurality of first circuit units and second circuit units alternately arranged in the second direction, and the second unit column includes a plurality of third circuit units arranged in the second direction.

In an exemplary embodiment, a third conductive layer is further disposed on the substrate, the third conductive layer further including a first branch of a first power line, the fourth conductive layer further including a second branch of the first power line, wherein:

an overlapping area exists between the orthographic projection of the first branch of the first power supply line on the substrate and the orthographic projection of the second branch of the first power supply line on the substrate; the first branch of the first power line is electrically connected to the second branch of the first power line through a via.

In an exemplary embodiment, the display substrate further includes a touch structure layer disposed on the anode layer in a plane perpendicular to the display substrate, the touch structure layer including a plurality of grid patterns, at least one of the grid patterns including a first touch branch, wherein:

an overlapping area exists between the orthographic projection of the first touch branch on the substrate and the orthographic projection of the second branch of the first power line on the substrate, and no overlapping area exists between the orthographic projection of the first touch branch on the substrate and the orthographic projection of the first branch of the first power line on the substrate.

In an exemplary embodiment, at least one of the grid patterns comprises a second touch branch, wherein:

the orthographic projection of the second touch branch on the substrate, the orthographic projection of the second branch of the first power line on the substrate and the orthographic projection of the first branch of the first power line on the substrate are overlapped.

In an exemplary embodiment, the fourth conductive layer further comprises a power supply connection electrode, wherein:

the power supply connection electrode extends along a first direction, the second branches of the first power supply lines extend along a second direction, and the second branches of two adjacent first power supply lines are connected through one or more power supply connection electrodes.

In an exemplary embodiment, there is no overlapping area of the orthographic projection of the first anode on the substrate and the orthographic projection of the second branch of the first power supply line on the substrate; an overlapping area exists between the orthographic projection of the second anode on the substrate and the orthographic projection of the second branch of the first power supply line on the substrate.

In an exemplary embodiment, the second branch of the first power line is provided with a bent portion configured such that a distance of the second branches of the two first power lines on both sides of the first anode in the first direction is greater in the first anode region than in a region other than the first anode in the first direction.

In an exemplary embodiment, a width of the second branch of the first power supply line near the first anode region is smaller than a width of the second branch of the first power supply line far from the first anode region.

The embodiment of the present disclosure also provides a display device, including: a display substrate as claimed in any preceding claim.

The display substrate and the display device provided by the embodiment of the disclosure have the advantages that the orthographic projection area of the first anode connecting electrode on the substrate is larger than the orthographic projection area of the second anode connecting electrode on the substrate, and the orthographic projection area of the first opening on the substrate is larger than the orthographic projection area of the second opening on the substrate, so that the light transmittance is effectively improved, the luminous efficiency of the light-emitting device is effectively improved, the power consumption is saved, and the display effect is improved. In addition, the preparation process disclosed by the invention can be well compatible with the existing preparation process, and is simple in process implementation, easy to implement, high in production efficiency, low in production cost and high in yield.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the disclosure;

fig. 2a and fig. 2b are schematic diagrams of pixel arrangement structures of two display panels according to an embodiment of the disclosure;

fig. 3 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 4 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 3;

fig. 5 is a schematic plan view illustrating a display substrate according to an embodiment of the disclosure;

FIG. 6a is a cross-sectional view of the display substrate shown in FIG. 5 taken along the line A-A;

FIG. 6b is a schematic diagram of a stacked structure of a third conductive layer, a first planarization layer and a fourth conductive layer in the display substrate shown in FIG. 5;

FIG. 6c is a schematic view of a stacked structure of a fourth conductive layer, a second planarization layer and an anode layer in the display substrate shown in FIG. 5;

fig. 6d is a schematic view of a stacked structure of the third conductive layer, the fourth conductive layer and the touch structure layer in the display substrate shown in fig. 5;

FIG. 7 is a schematic structural diagram of the display substrate shown in FIG. 5 after a semiconductor layer is formed thereon;

FIG. 8a is a schematic structural diagram of the display substrate shown in FIG. 5 after a first conductive layer is formed thereon;

FIG. 8b is a schematic diagram of a first conductive layer in the display substrate shown in FIG. 5;

FIG. 9a is a schematic structural diagram of the display substrate shown in FIG. 5 after a second conductive layer is formed thereon;

FIG. 9b is a schematic diagram illustrating a structure of a second conductive layer in the display substrate shown in FIG. 5;

FIG. 10a is a schematic structural diagram of the display substrate shown in FIG. 5 after a fourth insulating layer is formed thereon;

FIG. 10b is a schematic structural diagram of a fourth insulating layer in the display substrate shown in FIG. 5;

FIG. 11a is a schematic structural diagram of the display substrate shown in FIG. 5 after a third conductive layer is formed thereon;

FIG. 11b is a schematic structural diagram of a third conductive layer in the display substrate shown in FIG. 5;

FIG. 12a is a schematic structural view of the display substrate shown in FIG. 5 after a first planarization layer is formed thereon;

FIG. 12b is a schematic diagram illustrating a structure of a first planarization layer in the display substrate shown in FIG. 5;

FIG. 13a is a schematic structural diagram of the display substrate shown in FIG. 5 after a fourth conductive layer is formed thereon;

FIG. 13b is a schematic diagram of a fourth conductive layer in the display substrate shown in FIG. 5;

FIG. 14a is a schematic structural view of the display substrate shown in FIG. 5 after a second planarization layer is formed thereon;

FIG. 14b is a structural diagram of a second planarization layer in the display substrate shown in FIG. 5;

FIG. 15a is a schematic view of the display substrate shown in FIG. 5 after an anode layer is formed thereon;

FIG. 15b is a schematic diagram of an anode layer of the display substrate shown in FIG. 5;

fig. 16a is a graph showing a simulation result of a voltage drop of the first power line (VDD) in the display substrate according to the embodiment of the disclosure;

fig. 16b is a graph illustrating a simulation result of a voltage drop of the second power line (VSS) in the display substrate according to the embodiment of the disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of each component, the thickness of layers, or regions may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, which may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of subpixels Pxij. In some exemplary embodiments, the timing controller may supply a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, may supply a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and may supply a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, n may be a natural number. The scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number. The light emitting signal driver may generate emission signals to be supplied to the light emitting signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emitting signal driver may sequentially supply the emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting signal driver may be configured in the form of a shift register, and may generate the light emitting signal in such a manner that the light emitting stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, and o may be a natural number. The pixel array may include a plurality of subpixels Pxij, each of which may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, and i and j may be natural numbers. The subpixel Pxij may refer to a subpixel in which a transistor is connected to an ith scan signal line and to a jth data signal line.

Fig. 2a and 2b are schematic plan views of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the pixel units P may include one first subpixel P1 emitting light of a first color, one second subpixel P2 emitting light of a second color, and two third and fourth subpixels P3 and P4 emitting light of a third color, the four subpixels may each include a circuit unit and a light emitting device, the circuit unit may include a scan signal line, a data signal line, and a light emitting signal line and a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the data signal line, and the light emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted from the data signal line and output a corresponding current to the light emitting device under control of the scan signal line and the light emitting signal line. The light emitting device in each sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light emitting device is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 and the fourth subpixel P4 may be a green subpixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixel may be a rectangular shape, a diamond shape, a pentagon shape, or a hexagon shape. In an exemplary embodiment, the four sub-pixels may be arranged in a Square (Square) manner to form a GGRB pixel arrangement, as shown in fig. 2 a. In another exemplary embodiment, the four sub-pixels may be arranged in a Diamond (Diamond) manner to form an RGBG pixel arrangement, as shown in fig. 2 b. In other exemplary embodiments, the four sub-pixels may be arranged in a horizontal or vertical parallel manner. In an exemplary embodiment, the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a delta-shaped manner, or the like, and the disclosure is not limited thereto.

In an exemplary embodiment, a plurality of sub-pixels sequentially arranged in a horizontal direction are referred to as pixel rows, a plurality of sub-pixels sequentially arranged in a vertical direction are referred to as pixel columns, and the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array.

In some exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Fig. 3 is an equivalent circuit schematic diagram of a pixel driving circuit according to an exemplary embodiment of the disclosure. As shown in fig. 3, the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7), 1 storage capacitor C, and a plurality of signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, an initial signal line INIT, a first power supply line VDD, a second power supply line VSS, and a light emission control signal line E).

In some exemplary embodiments, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first pole of the first transistor T1 is connected to the initial signal line INIT, and the second pole of the first transistor T1 is connected to the first node N1. A gate electrode of the second transistor T2 is connected to the first scan signal line S1, a first pole of the second transistor T2 is connected to the third node N3, and a second pole of the second transistor T2 is connected to the first node N1. A gate electrode of the third transistor T3 is connected to the first node N1, a first pole of the third transistor T3 is connected to the second node N2, and a second pole of the third transistor T3 is connected to the third node N3. A gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first pole of the fourth transistor T4 is connected to the data signal line D, and a second pole of the fourth transistor T4 is connected to the second node N2. A gate electrode of the fifth transistor T5 is connected to the light emission control signal line E, a first pole of the fifth transistor T5 is connected to the first power source line VDD, and a second pole of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the light emission control signal line E, a first pole of the sixth transistor T6 is connected to the third node N3, and a second pole of the sixth transistor T6 is connected to the fourth node N4 (i.e., a first pole of the light emitting device). A gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first pole of the seventh transistor T7 is connected to the initial signal line INIT, and a second pole of the seventh transistor T7 is connected to the fourth node N4. A first terminal of the storage capacitor C is connected to the first power supply line VDD, and a second terminal of the storage capacitor C is connected to the first node N1.

In some example embodiments, the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

In some exemplary embodiments, the second electrode of the light emitting device is connected to a second power line VSS, the second power line VSS continuously supplying a low-level signal, and the first power line VDD continuously supplying a high-level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the display line, the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display line, that is, for the nth display line, the first scanning signal line S1 is S (n), the second scanning signal line S2 is S (n-1), and the second scanning signal line S2 of the display line and the first scanning signal line S1 of the pixel driving circuit of the previous display line may be the same signal line, so as to reduce the signal lines of the display panel and realize the narrow frame of the display panel.

In some exemplary embodiments, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, and the initial signal line INIT all extend in a horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in a vertical direction.

In some exemplary embodiments, the light emitting device may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

Fig. 4 is a timing diagram illustrating an operation of the pixel driving circuit shown in fig. 3. The exemplary embodiment of the present disclosure will be explained below by the operation process of the pixel driving circuit illustrated in fig. 4, and the pixel driving circuit in fig. 3 includes 7 transistors (the first transistor T1 to the sixth transistor T7), 1 storage capacitor C1, and 7 signal lines (the DATA signal line DATA, the first scanning signal line S1, the second scanning signal line S2, the initial signal line INIT, the first power supply line VDD, the second power supply line VSS, and the light emitting signal line EM), and all of the 7 transistors are P-type transistors.

In an exemplary embodiment, the operation of the pixel driving circuit may include:

in the first phase a1, which is referred to as a reset phase, the signal of the second scan signal line S2 is a low level signal, and the signals of the first scan signal line S1 and the light-emitting signal line E are high level signals. The signal of the second scan signal line S2 is a low level signal, which turns on the first transistor T1, and the signal of the initial signal line INIT is provided to the first node N1, so as to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light emitting signal line E are high level signals, turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the OLED does not emit light at this stage.

In the second phase a2, which is referred to as a data write phase or a threshold compensation phase, the signal of the first scan signal line S1 is a low level signal, the signals of the second scan signal line S2 and the light-emitting signal line E are high level signals, and the data signal line D outputs a data voltage. At this stage, the second terminal of the storage capacitor C is at a low level, so the third transistor T3 is turned on. The signal of the first scan signal line S1 is a low level signal to turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output from the data signal line D is supplied to the first node N1 through the second node N2, the turned-on third transistor T3, the turned-on third node N3, and the turned-on second transistor T2, and the sum of the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, the voltage of the second terminal (the second node N2) of the storage capacitor C is Vdata + Vth, Vdata is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to supply the initial voltage of the initial signal line INIT to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, clear the pre-stored voltage therein, complete the initialization, and ensure that the OLED does not emit light. The signal of the second scanning signal line S2 is a high level signal, turning off the first transistor T1. The signal of the light emitting signal line E is a high level signal, turning off the fifth transistor T5 and the sixth transistor T6.

In the third stage a3, referred to as a light-emitting stage, a signal of the light-emitting signal line E is a low-level signal, and signals of the first scan signal line S1 and the second scan signal line S2 are high-level signals. The signal on the light emitting signal line E is a low level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output from the first power line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, so that the OLED is driven to emit light.

During the driving of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vdata + Vth, the driving current of the third transistor T3 is:

I＝K*(Vgs-Vth)²＝K*[(Vdata+Vth-Vdd)-Vth]²＝K*[(Vdata–Vdd)]²

where I is a driving current flowing through the third transistor T3, that is, a driving current driving the OLED, K is a constant, Vgs is a voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is a threshold voltage of the third transistor T3, Vdata is a data voltage output from the data signal line D, and Vdd is a power voltage output from the first power line Vdd.

As can be seen from the above formula, the current I flowing through the light emitting device is independent of the threshold voltage Vth of the third transistor T3, eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I, and ensuring uniformity of luminance.

Based on the working time sequence, the pixel circuit eliminates residual positive charges of the light-emitting device after last light emission, realizes compensation of the grid voltage of the third transistor, avoids influence of threshold voltage drift of the third transistor on the driving current of the light-emitting device, and improves uniformity of displayed images and display quality of a display panel.

In recent years, with the progress of Display technology, more and more Active Matrix Organic Light Emitting Diode (AMOLED) Display panels are coming into the market, and compared with a conventional Thin Film Transistor Liquid Crystal Display panel (TFTLCD), the AMOLED has a faster response speed, a higher contrast ratio and a wider viewing angle. With the development of display technology, fingerprint unlocking becomes the mainstream mode at present, and the requirement on the optical fingerprint identification transmittance of the product is continuously expanded. In addition, improving the display effect and reducing the power consumption are the main research directions in the current display industry.

Fig. 5 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure, fig. 6a is a cross-sectional view of the display substrate shown in fig. 5 along a position a-a, fig. 6b is a schematic structural diagram of a stacked structure of a third conductive layer, a first planarization layer, and a fourth conductive layer in the display substrate shown in fig. 5, fig. 6c is a schematic structural diagram of a stacked structure of a fourth conductive layer, a second planarization layer, and an anode layer in the display substrate shown in fig. 5, and fig. 6d is a schematic structural diagram of a stacked structure of a third conductive layer, a fourth conductive layer, and a touch control structure layer in the display substrate shown in fig. 5. As shown in fig. 5, 6a, 6b, 6c and 6d, the display substrate includes a base 10, a semiconductor layer, a fourth conductive layer, a second flat layer 96 and an anode layer sequentially disposed on the base 10 in a plane perpendicular to the display substrate;

the semiconductor layer includes active layers of a plurality of transistors, the fourth conductive layer includes a first anode connection electrode 53 and a second anode connection electrode 54, the second planar layer 96 includes a first opening (i.e., a twelfth via hole V12 described later) and a second opening (i.e., a thirteenth via hole V13 described later), the anode layer includes a first anode 61 and a second anode 62, the first anode connection electrode 53 is connected to the first anode 61 through the first opening, and the second anode connection electrode 54 is connected to the second anode 62 through the second opening.

The area of the orthographic projection of the first anode connecting electrode 53 on the substrate 10 is larger than the area of the orthographic projection of the second anode connecting electrode 54 on the substrate 10, and the area of the orthographic projection of the first opening on the substrate 10 is larger than the area of the orthographic projection of the second opening on the substrate 10.

According to the display substrate provided by the embodiment of the disclosure, by making the area of the orthographic projection of the first anode connecting electrode 53 on the substrate 10 larger than the area of the orthographic projection of the second anode connecting electrode 54 on the substrate 10, and making the area of the orthographic projection of the first opening on the substrate 10 larger than the area of the orthographic projection of the second opening on the substrate 10, not only can the light transmittance be effectively improved, but also the sheet resistance of the metal of the fourth conducting layer where the first anode connecting electrode 53 is located is about 0.1 times of the sheet resistance of the metal of the anode layer, the light emitting efficiency of the light emitting device is effectively improved, the power consumption is saved, and the display effect is improved.

In some exemplary embodiments, a first conductive layer, a second conductive layer and a third conductive layer are further disposed on the substrate, the first conductive layer including gate electrodes of the plurality of transistors and a first plate of the storage capacitor, the second conductive layer including a second plate of the storage capacitor, and the third conductive layer including first and second poles of the plurality of transistors.

In some exemplary embodiments, the first anode connection electrode 53 includes an electrode main body portion 53-2 and an electrode convex portion 53-1 disposed on the electrode main body portion 53-2, an orthogonal projection of the electrode main body portion 53-2 on the substrate 10 has an overlapping region with an orthogonal projection of the first anode 61 on the substrate 10, and an orthogonal projection of the electrode convex portion 53-1 on the substrate 10 has no overlapping region with an orthogonal projection of the first anode 61 on the substrate 10.

In some exemplary embodiments, the third conductive layer includes a plurality of first connection electrodes 43, and there is an overlapping region where an orthogonal projection of the electrode protrusions 53-1 on the substrate 10 overlaps an orthogonal projection of the first connection electrodes 43 on the substrate 10.

The display substrate further includes a first planarization layer 95 disposed between the third conductive layer and the fourth conductive layer in a plane perpendicular to the display substrate, and the electrode protrusion 53-1 is electrically connected to the first connection electrode 43 through a via hole on the first planarization layer 95.

In some exemplary embodiments, there is an overlapping region of an orthogonal projection of the second anode connection electrode 54 on the substrate 10 and an orthogonal projection of the first connection electrode 43 on the substrate 10, and the second anode connection electrode 54 is connected to the first connection electrode 43 through a via hole on the first planarization layer 95.

In some exemplary embodiments, the second anode 62 includes an anode main portion 62-2 and an anode protruding portion 62-1 disposed on the anode main portion 62-2, an orthogonal projection of the anode main portion 62-2 on the substrate 10 has no overlapping area with an orthogonal projection of the second anode connection electrode 54 on the substrate 10, an orthogonal projection of the anode protruding portion 62-1 on the substrate 10 has an overlapping area with an orthogonal projection of the second anode connection electrode 54 on the substrate 10, and the second anode connection electrode 54 is electrically connected to the anode protruding portion 62-1 through the second opening.

In some exemplary embodiments, a display substrate includes a plurality of pixel units, each pixel unit including a plurality of sub-pixels, each sub-pixel including a circuit unit and a light emitting device including a red light emitting device emitting red light, a blue light emitting device emitting blue light, and a green light emitting device emitting green light. The circuit unit includes a first circuit unit connected with the red light emitting device, a second circuit unit connected with the blue light emitting device, and a third circuit unit connected with the green light emitting device.

The first circuit unit includes a first anode connection electrode 53, and the red light emitting device includes a first anode 61; the second circuit unit includes a second anode connection electrode 54, and the blue light emitting device includes a second anode 62; the third circuit unit includes a second anode connection electrode 54 and the green light emitting device includes a second anode 62.

In some exemplary embodiments, each of the pixel units includes one first circuit unit, one second circuit unit, and two third circuit units, the plurality of circuit units form a plurality of unit rows and a plurality of unit columns, the unit columns include first unit columns including a plurality of first circuit units and second circuit units alternately arranged in the second direction Y, and the second unit columns include a plurality of third circuit units arranged in the second direction Y.

In some exemplary embodiments, the third conductive layer further comprises a first branch 41 of the first power supply line, and the fourth conductive layer further comprises a second branch 51 of the first power supply line, wherein:

an overlapping area exists between the orthographic projection of the first branch 41 of the first power line on the substrate 10 and the orthographic projection of the second branch 51 of the first power line on the substrate 10; the first branch 41 of the first power line is electrically connected to the second branch 51 of the first power line through a via on the first planarization layer 95.

In some exemplary embodiments, the display substrate further includes a touch structure layer 105 disposed on the anode layer in a plane perpendicular to the display substrate, the touch structure layer 105 includes a plurality of grid patterns, at least one grid pattern includes the first touch branch 71, wherein:

an overlapping area exists between the orthographic projection of the first touch branch 71 on the substrate 10 and the orthographic projection of the second branch 51 of the first power line on the substrate 10, and no overlapping area exists between the orthographic projection of the first touch branch 71 on the substrate 10 and the orthographic projection of the first branch 41 of the first power line on the substrate 10.

In the display substrate provided by the embodiment of the present disclosure, the first branch 41 of the first power line and the second branch 51 of the first power line are overlapped as much as possible, and in an area where the first branch 41 of the first power line and the second branch 51 of the first power line cannot be overlapped, the trace of the second branch 51 of the first power line and the trace of the grid pattern of the touch structure layer 105 are overlapped, so that the light transmittance is effectively improved.

In some exemplary embodiments, the at least one grid pattern further comprises a second touch branch 72, wherein:

the orthographic projection of the second touch branch 72 on the substrate 10, the orthographic projection of the second branch 51 of the first power line on the substrate 10 and the orthographic projection of the first branch 41 of the first power line on the substrate 10 are overlapped.

In some exemplary embodiments, the fourth conductive layer further comprises a power supply connection electrode 52, wherein: the power connection electrodes 52 extend along the first direction X, the second branches 51 of the first power lines extend along the second direction Y, and the second branches 51 of two adjacent first power lines are electrically connected by one or more power connection electrodes 52.

In some exemplary embodiments, there is no overlapping area of the orthographic projection of the first anode 61 on the substrate 10 and the orthographic projection of the second branch 51 of the first power supply line on the substrate 10; there is an overlapping area of the orthographic projection of the second anode 62 on the substrate 10 and the orthographic projection of the second branch 51 of the first power supply line on the substrate 10.

In some exemplary embodiments, the second branch 51 of the first power line is provided with a bent portion 51-1, and the bent portion 51-1 is configured such that the distance d2 of the second branches 51 of the two first power lines on both sides of the first anode 61 in the first direction X in the area of the first anode 61 is greater than the distance d1 in the first direction X in the area other than the first anode 61.

In some exemplary embodiments, the width d3 of the second branch 51 of the first power line in the region near the first anode 61 is smaller than the width d4 of the second branch 51 of the first power line in the region away from the first anode 61.

The structure of the display substrate according to the embodiment of the present disclosure is exemplified by the process of manufacturing the display substrate. The "patterning process" referred to in this disclosure includes processes of depositing a film layer, coating a photoresist, mask exposing, developing, etching, and stripping a photoresist. The deposition may employ any one or more selected from sputtering, evaporation and chemical vapor deposition, the coating may employ any one or more selected from spray coating and spin coating, and the etching may employ any one or more selected from dry etching and wet etching. "thin film" refers to a layer of a material deposited or coated onto a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. When the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The "a and B are disposed in the same layer" in the present disclosure means that a and B are simultaneously formed by the same patterning process. "the orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

In some exemplary embodiments, the process of preparing the display substrate shown in fig. 6a and 6b may include the steps of:

(1) in an exemplary embodiment, the forming of the semiconductor layer pattern may include: a first insulating film and a semiconductor film are sequentially deposited on the substrate 10, and the semiconductor film is patterned by a patterning process to form a first insulating layer 91 covering the substrate 10, and a semiconductor layer disposed on the first insulating layer 91, as shown in fig. 7.

In an exemplary embodiment, the semiconductor layer of each sub-pixel may include the first to seventh active layers 11 to 17 of the first to seventh transistors T7 of the first transistor T1, and the first to seventh active layers 11 to 17 are integrated structures connected to each other.

In an exemplary embodiment, the first region R1 may include at least portions of the first active layer 11 of the first transistor T1, the second active layer 12 of the second transistor T2, the fourth active layer 14 of the fourth transistor T4, and the seventh active layer 17 of the seventh transistor T7, the second region R2 may include at least portions of the third active layer 13 of the third transistor T3, and the third region R3 may include at least portions of the fifth active layer 15 of the fifth transistor T5 and the sixth active layer 16 of the sixth transistor T6. The first and seventh

active layers

11 and 17 are disposed in the first region R1 on a side away from the second region R2, and the second and fourth

active layers

12 and 14 are disposed in the first region R1 on a side adjacent to the second region R2.

In an exemplary embodiment, the first active layer 11 may have an "n" shape, the second active layer 12 may have a "7" shape, the third active layer 13 may have a "several" shape, the fourth active layer 14 may have a "1" shape, and the fifth, sixth and seventh

active layers

15, 16 and 17 may have an "L" shape.

In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 11-1 of the first active layer 11 simultaneously serves as the first region 17-1 of the seventh active layer 17, the second region 11-2 of the first active layer 11 simultaneously serves as the first region 12-1 of the second active layer 12, the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, the second region 13-2 of the third active layer 13 simultaneously serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, and the second region 16-2 of the sixth active layer 16 simultaneously serves as the second region 17-2 of the seventh active layer 17. In an exemplary embodiment, the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are separately provided.

In an exemplary embodiment, the third active layer 13 of the third transistor includes a first region 13-1, a second region 13-2, and a channel region, the channel region of the third active layer 13 is disposed between the first region 13-1 and the second region 13-2, and both ends of the channel region are connected to the first region 13-1 and the second region 13-2, respectively. The first region 13-1 of the third active layer 13 serves as both the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, i.e., the first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15 are connected to each other. The second region 13-2 of the third active layer 13 serves as both the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, i.e., the second region 13-2 of the third active layer 13, the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16 are connected to each other.

(2) A first conductive layer pattern is formed. In an exemplary embodiment, the forming of the first conductive layer pattern may include: on the substrate on which the aforementioned pattern is formed, a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned by a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern provided on the second insulating layer 92, the first conductive layer pattern including at least: as shown in fig. 8a and 8b, the first scanning signal line 21, the second scanning signal line 22, the light-emitting control line 23, and the first plate 24 of the storage capacitor, fig. 8b is a schematic plan view of the first conductive layer in fig. 8 a. In an exemplary embodiment, the first conductive layer may be referred to as a first GATE metal (GATE 1) layer.

In the exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, and the light emission control line 23 extend in the first direction X. The first scanning signal line 21 and the second scanning signal line 22 are disposed in the first region R1, the second scanning signal line 22 is located on the side of the first scanning signal line 21 away from the second region R2, the light emission control line 23 is disposed in the third region R3, and the first plate 24 of the storage capacitor is disposed in the second region R2 between the first scanning signal line 21 and the light emission control line 23.

In an exemplary embodiment, the first plate 24 may have a rectangular shape, corners of the rectangular shape may be provided with chamfers, and an overlapping region exists between an orthographic projection of the first plate 24 on the substrate 10 and an orthographic projection of the third active layer of the third transistor T3 on the substrate 10. In an exemplary embodiment, the first plate 24 simultaneously serves as a gate electrode of the third transistor T3.

In an exemplary embodiment, a region where the first scan signal line 21 overlaps the fourth active layer of the fourth transistor T4 serves as a gate electrode of the fourth transistor T4. The first scan signal line 21 is provided with a gate block 21-1 protruding toward the second scan signal line 22, an overlapping region exists between an orthographic projection of the gate block 21-1 on the substrate 10 and an orthographic projection of the second active layer of the second transistor T2 on the substrate 10, and a region where the first scan signal line 21 and the gate block 21-1 overlap with the second active layer of the second transistor T2 serves as a gate electrode of the second transistor T2 dual gate structure. A region where the second scan signal line 22 overlaps with the first active layer of the first transistor T1 serves as a gate electrode of the first transistor T1 dual gate structure, a region where the second scan signal line 22 overlaps with the seventh active layer of the seventh transistor T7 serves as a gate electrode of the seventh transistor T7, a region where the light emission control line 23 overlaps with the fifth active layer of the fifth transistor T5 serves as a gate electrode of the fifth transistor T5, and a region where the light emission control line 23 overlaps with the sixth active layer of the sixth transistor T6 serves as a gate electrode of the sixth transistor T6.

In an exemplary embodiment, after the first conductive layer pattern is formed, a semiconductor layer may be subjected to a conductor process using the first conductive layer as a mask, channel regions of the first to seventh transistors T1 to T7 are formed by the semiconductor layer of regions masked by the first conductive layer, and the semiconductor layer of regions not masked by the first conductive layer is subjected to a conductor, that is, both the first and second regions of the first to seventh active layers are subjected to a conductor.

After this process, the display substrate includes a first insulating layer 91 disposed on the substrate 10, a semiconductor layer disposed on the first insulating layer 91, which may include the first to seventh active layers 11 to 17, a second insulating layer 92 covering the semiconductor layer, and a first conductive layer disposed on the second insulating layer 92, which may include the first scan signal line 21, the second scan signal line 22, the light emission control line 23, and the first plate 24 of the storage capacitor.

(3) Forming a second conductive layer pattern. In an exemplary embodiment, the forming of the second conductive layer pattern may include: depositing a third insulating film and a second metal film in sequence on the substrate with the patterns, patterning the second metal film by using a patterning process, and forming a third insulating layer 93 covering the first conductive layer and a second conductive layer pattern arranged on the third insulating layer 93, wherein the second conductive layer pattern at least comprises: the initial signal line 31, the second plate 32 of the storage capacitor, the shielding electrode 33 and the plate connection line 35, as shown in fig. 9a and 9b, fig. 9b is a schematic plan view of the second conductive layer in fig. 9 a. In an exemplary embodiment, the second conductive layer may be referred to as a second GATE metal (GATE 2) layer.

In an exemplary embodiment, the initial signal line 31 extends in the first direction X, is disposed within the first region R1, and is located on a side of the second scan signal line 22 away from the second region R2. The second plate 32 of the storage capacitor is disposed in the second region R2 between the first scanning signal line 21 and the light emission control line 23. The shielding electrode 33 is disposed in the first region R1, and the shielding electrode 33 is configured to shield the influence of the data voltage jump on the key node, so as to prevent the data voltage jump from influencing the potential of the key node of the pixel driving circuit, thereby improving the display effect.

In an exemplary embodiment, the initial signal lines 31 may be arranged in unequal widths, and the width of the initial signal lines 31 is the dimension of the initial signal lines 31 in the second direction Y. The preliminary signal line 31 includes a region overlapping with the semiconductor layer and a region not overlapping with the semiconductor layer, and the width of the preliminary signal line 31 in the region not overlapping with the semiconductor layer may be smaller than the width of the preliminary signal line 31 in the region overlapping with the semiconductor layer.

In an exemplary embodiment, the outline of the second plate 32 may be rectangular, corners of the rectangular shape may be provided with chamfers, and there is an overlapping region between an orthographic projection of the second plate 32 on the substrate 10 and an orthographic projection of the first plate 24 on the substrate 10. The second pole plate 32 is provided with an opening 34, and the opening 34 may be located in the middle of the second region R2. The opening 34 may be rectangular such that the second pole plate 32 forms a ring-shaped structure. The opening 34 exposes the third insulating layer covering the first plate 24, and the orthographic projection of the first plate 24 on the substrate 10 includes the orthographic projection of the opening 34 on the substrate 10. In an exemplary embodiment, the opening 34 is configured to receive a subsequently formed first via that is located within the opening 34 and exposes the first plate 24, connecting the second pole of the subsequently formed first transistor T1 with the first plate 24.

In an exemplary embodiment, the plate connection line 35 is disposed between the second plates 32 of the adjacent sub-pixels in the first direction X, a first end of the plate connection line 35 is connected to the second plate 32 of the present sub-pixel, and a second end of the plate connection line 35 extends in the first direction X or a direction opposite to the first direction X and is connected to the second plates 32 of the adjacent sub-pixels, i.e., the plate connection line 35 is configured to connect the second plates of the adjacent sub-pixels in the first direction X to each other. In an exemplary embodiment, the second plates in a sub-pixel row are connected to each other by the plate connection lines 35 to form an integrated structure, and the integrated structure of the second plates can be reused as power signal lines, so that the plurality of second plates in a sub-pixel row are ensured to have the same potential, which is beneficial to improving the uniformity of the panel, avoiding the display defects of the display substrate, and ensuring the display effect of the display substrate.

In an exemplary embodiment, an orthogonal projection of the edge of the second plate 32 adjacent to the first region R1 on the substrate 10 overlaps an orthogonal projection of the boundary line of the first region R1 and the second region R2 on the substrate 10, an orthogonal projection of the edge of the second plate 32 adjacent to the third region R3 on the substrate 10 overlaps an orthogonal projection of the boundary line of the second region R2 and the third region R3 on the substrate 10, that is, the length of the second plate 32 is equal to the length of the second region R2, and the length of the second plate 32 refers to a dimension of the second plate 32 in the second direction Y.

After this process, the display substrate includes a first insulating layer 91 disposed on the substrate 10, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, a first conductive layer disposed on the second insulating layer 92, a third insulating layer 93 covering the first conductive layer, and a second conductive layer disposed on the third insulating layer 93, the semiconductor layer may include first to seventh active layers 11 to 17, the first conductive layer may include the first and second

scanning signal lines

21 and 22, the light emitting control line 23, and the first plate 24 of the storage capacitor, and the second conductive layer may include the initial signal line 31, the second plate 32 of the storage capacitor, the shielding electrode 33, and the plate connection line 35.

(4) The fourth insulating layer 94 is patterned. In an exemplary embodiment, the forming of the fourth insulation layer pattern may include: depositing a fourth insulating film on the substrate on which the patterns are formed, patterning the fourth insulating film by adopting a patterning process to form a fourth insulating layer 94 covering the second conductive layer, wherein a plurality of via holes are formed in the fourth insulating layer 94, and the plurality of via holes at least comprise: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8 and a ninth via V9, as shown in fig. 10a and 10b, fig. 10b is a schematic plan view of the fourth insulating layer in fig. 10 a.

In an exemplary embodiment, the first via V1 is located within the opening 34 of the second plate 32, an orthographic projection of the first via V1 on the substrate 10 is located within an orthographic projection of the opening 34 on the substrate 10, and the fourth insulating layer and the third insulating layer within the first via V1 are etched away, exposing the surface of the first plate 24. The first via V1 is configured to connect the second pole of the subsequently formed first transistor T1 with the first plate 24 through the via.

In an exemplary embodiment, the second via V2 is located at the area of the second plate 32, the orthographic projection of the second via V2 on the substrate 10 is located within the range of the orthographic projection of the second plate 32 on the substrate 10, and the fourth insulating layer in the second via V2 is etched away to expose the surface of the second plate 32. The second via V2 is configured to allow a subsequently formed first power line to be connected to the second plate 32 through the via. In an exemplary embodiment, the second via V2 as a power via may include a plurality, and the plurality of second vias V2 may be sequentially arranged along the second direction Y, increasing the connection reliability of the first power line and the second plate 32.

In an exemplary embodiment, the third via hole V3 is located at the third region R3, and the fourth insulating layer, the third insulating layer, and the second insulating layer within the third via hole V3 are etched away, exposing the surface of the first region of the fifth active layer. The third via V3 is configured to allow a subsequently formed first power line to be connected to the fifth active layer through the via.

In an exemplary embodiment, the fourth via hole V4 is located at the third region R3, and the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via hole V4 are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer). The fourth via V4 is configured to connect the second pole of the subsequently formed sixth transistor T6 to the sixth active layer through the via, and to connect the second pole of the subsequently formed seventh transistor T7 to the seventh active layer through the via.

In an exemplary embodiment, the fifth via hole V5 is located at the first region R1, and the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via hole V5 are etched away, exposing the surface of the first region of the fourth active layer. The fifth via hole V5 is configured to connect a subsequently formed data signal line to the fourth active layer through the via hole, and the fifth via hole V5 is referred to as a data write hole.

In an exemplary embodiment, the sixth via hole V6 is located in the first region R1, and the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via hole V6 are etched away, exposing the surface of the second region of the first active layer (also the first region of the second active layer). The sixth via V6 is configured to connect the second pole of the subsequently formed first transistor T1 to the first active layer through the via, and to connect the first pole of the subsequently formed second transistor T2 to the second active layer through the via.

In an exemplary embodiment, the seventh via hole V7 is located at the first region R1, and the fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via hole V7 are etched away, exposing the surface of the first region of the seventh active layer (which is also the first region of the first active layer). The seventh via V7 is configured to connect the first pole of the subsequently formed seventh transistor T7 to the seventh active layer through the via, and to connect the first pole of the subsequently formed first transistor T1 to the first active layer through the via.

In an exemplary embodiment, the eighth via V8 is located at the first region R1, and the fourth insulating layer within the eighth via V8 is etched away, exposing the surface of the shielding electrode 33. The eighth via V8 is configured to connect a subsequently formed first power line to the shield electrode 33 through the via.

In an exemplary embodiment, the ninth via V9 is located at the first region R1, and the fourth insulating layer within the ninth via V9 is etched away, exposing the surface of the preliminary signal line 31. The ninth via V9 is configured to connect the first pole of the subsequently formed seventh transistor T7 (also the first pole of the first transistor T1) with the initial signal line 31 through the via.

(5) Forming a third conductive layer pattern. In an exemplary embodiment, the forming of the third conductive layer may include: depositing a third metal film on the substrate on which the pattern is formed, patterning the third metal film by using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer 94, where the third conductive layer at least includes: the first branch 41 of the first power line, the data signal line 42, the first connection electrode 43, the second connection electrode 44, and the third connection electrode 45, as shown in fig. 11a and 11b, and fig. 11b is a plan view schematically illustrating the third conductive layer in fig. 11 a. In an exemplary embodiment, the third conductive layer may be referred to as a first source drain metal (SD1) layer.

In the exemplary embodiment, the first branch 41 of the first supply line extends along the second direction Y, the first branch 41 of the first supply line being connected on the one hand to the second plate 32 via a second via V2, on the other hand to the shielding electrode 33 via an eighth via V8, and on the other hand to the fifth active layer via a third via V3, so that the shielding electrode 33 and the second plate 32 have the same potential as the first branch 41 of the first supply line. Because the orthographic projection of the shielding electrode 33 on the substrate 10 and the orthographic projection of the subsequently formed data signal line on the substrate 10 have an overlapping region, and the shielding electrode 33 is connected with the first branch 41 of the first power line, the influence of data voltage jump on the key node is effectively shielded, the influence of the data voltage jump on the key node of the pixel driving circuit is avoided, and the display effect is improved.

In an exemplary embodiment, the data signal line 42 extends along the second direction Y, and the data signal line 42 is connected to the first region of the fourth active layer through the fifth via V5 such that the data signal transmitted by the data signal line 42 is written in the fourth transistor T4.

In an exemplary embodiment, the first connection electrode 43 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4 such that the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 have the same potential. In an exemplary embodiment, the first connection electrode 43 may serve as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7. In the exemplary embodiment, the first connection electrode 43 is configured to be connected with anode connection electrodes (a first anode connection electrode 53 and a second anode connection electrode 54) that are formed later.

In an exemplary embodiment, the second connection electrode 44 extends along the second direction Y, has a first end connected to the second region of the first active layer (also the first region of the second active layer) through the sixth via V6, and has a second end connected to the first plate 24 through the first via V1, such that the first plate 24, the second pole of the first transistor T1, and the first pole of the second transistor T2 have the same potential. In an exemplary embodiment, the second connection electrode 44 may serve as the second pole of the first transistor T1 and the first pole of the second transistor T2.

In an exemplary embodiment, the third connection electrode 45 extends along the second direction Y, has a first end connected to the initial signal line 31 through the ninth via V9, and has a second end connected to the first region of the seventh active layer (which is also the first region of the first active layer) through the seventh via V7, such that the first pole of the seventh transistor T7 and the first pole of the first transistor T1 have the same potential as the initial signal line 31. In an exemplary embodiment, the third connection electrode 45 may serve as a first pole of the seventh transistor T7 and a first pole of the first transistor T1.

In an exemplary embodiment, the first branch 41 of the first power line and the data signal line 42 may be straight lines of equal width, or straight lines of unequal width.

(6) A first planarization layer 95 is patterned. In an exemplary embodiment, patterning the first planarization layer 95 may include: a first planarization film is coated on the substrate on which the pattern is formed, and is patterned by a patterning process to form a first planarization layer 95 covering the third conductive layer, wherein a tenth via hole V10 and an eleventh via hole V11 are disposed on the first planarization layer 95, as shown in fig. 12a and 12b, and fig. 12b is a schematic plan view of the first planarization layer in fig. 12 a.

The tenth via V10 is located in the area of the first branch 41 of the first power line, the first planarization layer in the tenth via V10 is removed to expose the surface of the first branch 41 of the first power line, and the tenth via V10 is configured to connect the second branch 51 of the first power line with the first branch 41 of the first power line through the via.

The eleventh via hole V11 is located at the region where the first connection electrode 43 is located, the first planarization layer in the eleventh via hole V11 is removed to expose the surface of the first connection electrode 43, and the eleventh via hole V11 is configured such that a subsequently formed anode connection electrode is connected to the first connection electrode 43 through the via hole.

(7) Forming a fourth conductive layer pattern. Forming the fourth conductive layer may include: depositing a fourth metal film on the substrate on which the pattern is formed, patterning the fourth metal film by using a patterning process, and forming a fourth conductive layer disposed on the first planarization layer 95, where the fourth conductive layer at least includes: the second branch 51 of the first power line, the power connection electrode 52, the first anode connection electrode 53 and the second anode connection electrode 54, as shown in fig. 13a and 13b, and fig. 13b is a schematic plan view of the fourth conductive layer in fig. 13 a. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source drain metal (SD2) layer.

In the exemplary embodiment, the second branch 51 of the first power line extends along the second direction Y, there is an overlapping area of an orthographic projection of the first branch 41 of the first power line on the substrate 10 and an orthographic projection of the second branch 51 of the first power line on the substrate 10, and the second branch 51 of the first power line is connected with the first branch 41 of the first power line through the tenth via V10.

In an exemplary embodiment, the second branch 51 of the first power line is provided with a plurality of bent portions 51-1, and the bent portions 51-1 are configured such that the distance of the second branches of the two first power lines on both sides of the first anode connection electrode 53 in the first direction X in the region of the first anode connection electrode 53 is greater than the distance in the first direction X in the region other than the first anode connection electrode 53.

In an exemplary embodiment, the second branch 51 of the first power line has a smaller width in a region near the first anode connection electrode 53 than in a region far from the first anode connection electrode 53.

In the exemplary embodiment, the power supply connection electrodes 52 extend along the first direction X, and the second branches 51 of adjacent first power supply lines are connected to each other by one or more power supply connection electrodes 52.

In an exemplary embodiment, the second anode connection electrode 54 is connected to the first connection electrode 43 through the eleventh via hole V11.

In an exemplary embodiment, the first anode connection electrode 53 is positioned at a first circuit unit region, and the first circuit unit is electrically connected to a red light emitting device emitting red light.

In an exemplary embodiment, the second anode connection electrode 54 is positioned at the second circuit unit region electrically connected to the blue light emitting device emitting blue light and the third circuit unit region electrically connected to the green light emitting device emitting green light.

In an exemplary embodiment, an area of an orthogonal projection of the first anode connection electrode 53 on the substrate 10 is larger than an area of an orthogonal projection of the second anode connection electrode 54 on the substrate 10.

In an exemplary embodiment, the first anode connection electrode 53 includes an electrode main body portion 53-2 and an electrode protrusion portion 53-1 disposed on the electrode main body portion 53-2, an orthogonal projection of the electrode protrusion portion 53-1 on the substrate 10 has an overlapping region with an orthogonal projection of the first connection electrode 43 on the substrate 10, and the electrode protrusion portion 53-1 is connected to the first connection electrode 43 through the eleventh via hole V11.

In an exemplary embodiment, the size and shape of the electrode main body portion 53-2 may be close to or the same as those of the first anode 61 to be subsequently formed, and the size and shape of the electrode protrusion portion 53-1 may be close to or the same as those of the second anode connection electrode 54. In practical use, the size and shape of the first anode connecting electrode 53 and the second anode connecting electrode 54 may be determined according to practical situations, and the present disclosure does not limit this.

In an exemplary embodiment, there is an overlapping region of an orthogonal projection of the second anode connection electrode 54 on the substrate 10 and an orthogonal projection of the first connection electrode 43 on the substrate 10, and the second anode connection electrode 54 is connected to the first connection electrode 43 through the eleventh via hole V11.

In an exemplary embodiment, the second branch 51 of the first power line may be a straight line of equal width, or a straight line of unequal width.

(8) A second planar layer 96 is patterned. In some exemplary embodiments, patterning the second planarization layer 96 may include: a second flat film is coated on the substrate on which the pattern is formed, and the second flat film is patterned by a patterning process to form a second flat layer 96 covering the fourth conductive layer, wherein at least a twelfth via hole V12 (i.e., a first opening) and a thirteenth via hole V13 (i.e., a second opening) are disposed on the second flat layer 96, as shown in fig. 14a and 14b, and fig. 14b is a schematic plan view of the second flat layer in fig. 14 a.

In some exemplary embodiments, the twelfth via hole V12 is located at a region where the first anode connection electrode 53 is located, the second planarization layer in the twelfth via hole V12 is removed to expose the surface of the first anode connection electrode 53, and the twelfth via hole V12 is configured to electrically connect the subsequently formed second sub-anode with the first anode connection electrode 53 through the via hole.

In some exemplary embodiments, the thirteenth via hole V13 is located at the area where the second anode connection electrode 54 is located, the second planarization layer in the thirteenth via hole V13 is removed to expose the surface of the second anode connection electrode 54, and the thirteenth via hole V13 is configured to electrically connect the subsequently formed second anode with the second anode connection electrode 54 through the via hole.

In some exemplary embodiments, an area of an orthogonal projection of the twelfth via V12 on the substrate 10 is greater than an area of an orthogonal projection of the thirteenth via V13 on the substrate 10.

In an exemplary embodiment, the size and shape of the twelfth via V12 may be close to or the same as those of the first anode 61 formed subsequently, and in practical use, the twelfth via V12 may be made as large as possible to increase the contact area between the first anode connection electrode 53 and the first anode 61 formed subsequently, reduce the resistance thereof, and improve the light emitting efficiency of the light emitting device connected to the first anode 61. The size and shape of the thirteenth via hole V13 may be determined according to the size and shape of the second anode connection electrode 54, and the thirteenth via hole V13 may be formed as long as the surface of the second anode connection electrode 54 is exposed.

To this end, a pattern of the driving circuit layer 102 in fig. 6a is prepared on the substrate 10. The driving circuit layer 102 may include a plurality of circuit units each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, an emission control line, a data signal line, a first power supply line, an initial signal line, and the like connected to the pixel driving circuit, in a plane parallel to the display substrate. The driving circuit layer 102 may include a first insulating layer 91, a semiconductor layer, a second insulating layer 92, a first conductive layer, a third insulating layer 93, a second conductive layer, a fourth insulating layer 94, a third conductive layer, a first planarization layer 95, a fourth conductive layer, and a second planarization layer 96, which are sequentially stacked on the substrate 10 in a plane perpendicular to the display substrate.

In an exemplary embodiment, after the driving circuit layer 102 is prepared, the light emitting structure layer 103 is prepared on the driving circuit layer 102, and the preparation process of the light emitting structure layer 103 may include the operations of:

(9) an anode layer pattern is formed. In some exemplary embodiments, forming the anode pattern may include: on the substrate with the aforementioned pattern, a transparent conductive film is deposited, and the transparent conductive film is patterned by a patterning process to form an anode layer disposed on the second planar layer, as shown in fig. 15a and 15b, where fig. 15b is a schematic plan view of the anode layer in fig. 15 a.

In some exemplary embodiments, the anode layer includes a first anode 61 and a second anode 62, the first anode 61 is connected to the first anode connection electrode 53 through a twelfth via V12, and the second anode 62 is connected to the second anode connection electrode 54 through a thirteenth via V13. Since the anode connection electrode (the first anode connection electrode 53 or the second anode connection electrode 54) is electrically connected to the first connection electrode 43 through the eleventh via V11, and the first connection electrode 43 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via V4, it is achieved that the pixel circuit can drive the light emitting device to emit light.

In some exemplary embodiments, the second anode 62 includes an anode main portion 62-2 and an anode protruding portion 62-1 disposed on the anode main portion 62-2, an orthogonal projection of the anode main portion 62-2 on the substrate 10 has no overlapping area with an orthogonal projection of the second anode connection electrode 54 on the substrate 10, an orthogonal projection of the anode protruding portion 62-1 on the substrate has an overlapping area with an orthogonal projection of the second anode connection electrode 54 on the substrate, and the second anode connection electrode 54 is connected to the anode protruding portion 62-1 through a thirteenth via V13.

In an exemplary embodiment, the shape of the anode body portion 62-2 may be pentagonal-like or hexagonal-like. The anode projection 62-1 may be a rectangle projecting toward the second anode connection electrode 54 in the pixel driving circuit connected thereto.

In some exemplary embodiments, a display substrate includes a plurality of pixel units, each pixel unit including a plurality of sub-pixels, each sub-pixel including a circuit unit and a light emitting device, each light emitting device including a red (R) light emitting device emitting red light, a blue (B) light emitting device emitting blue light, and a green (G) light emitting device emitting green light, each circuit unit including a first circuit unit connected with the red light emitting device, a second circuit unit connected with the blue light emitting device, and a third circuit unit connected with the green light emitting device.

The first circuit unit includes a first anode connection electrode 53, and the red light emitting device includes a first anode 61; the second circuit unit includes a second anode connection electrode 54, the blue light emitting device includes a second anode 62; the third circuit unit includes a second anode connection electrode 54 and the green light emitting device includes a second anode 62.

In some exemplary embodiments, each of the pixel units includes one first circuit unit, one second circuit unit, and two third circuit units, the plurality of circuit units form a plurality of unit rows and a plurality of unit columns, the unit columns include a first unit column including a plurality of first circuit units and second circuit units alternately arranged in the second direction Y, and a second unit column including a plurality of third circuit units arranged in the second direction Y.

In some exemplary embodiments, the subsequent preparation process may include: a pixel defining film is coated and patterned by a patterning process to form a Pixel Defining Layer (PDL), and the pixel defining layer of each sub-pixel is provided with a sub-pixel opening (SA) exposing the anode. An organic light emitting layer is formed using an evaporation or ink jet printing process, and a cathode is formed on the organic light emitting layer, and the anode, the pixel defining layer, the organic light emitting layer, and the cathode constitute the light emitting structure layer 103 pattern in fig. 6 a. Forming a pattern of the encapsulation layer 104, as shown in fig. 6a, the encapsulation layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, so as to ensure that external water vapor cannot enter the light emitting structure layer.

In some exemplary embodiments, the subsequent preparation process may further comprise: a pattern of the touch structure layer 105 is formed on the substrate on which the pattern is formed, as shown in fig. 5 and 6 a. The touch structure layer 105 may include a buffer layer, a first touch electrode layer (i.e., a bridge layer), a touch insulating layer (TLD), a second touch electrode layer, and a protective layer stacked on the encapsulation layer 104, the plurality of first touch electrodes, the plurality of second touch electrodes, and the plurality of first connection portions may be disposed on the second touch electrode layer at the same layer and may be formed through the same patterning process, and the first touch electrodes and the first connection portions may be connected to each other as an integral structure. The second connecting portion may be disposed on the first touch electrode layer, and the second touch electrodes adjacent to each other are connected to each other through the via hole, and a touch insulating layer is disposed between the second touch electrode layer and the first touch electrode layer. In some possible implementations, the plurality of first touch electrodes, the plurality of second touch electrodes, and the plurality of second connection portions may be disposed on the second touch electrode layer at the same layer, the second touch electrodes and the second connection portions may be connected to each other to form an integrated structure, and the first connection portions may be disposed on the first touch electrode layer, and the adjacent first touch electrodes are connected to each other through the via holes.

In an exemplary embodiment, as shown in fig. 6d, the second touch electrode layer includes a plurality of grid patterns, at least one grid pattern includes a first touch branch 71, the first touch branch 71 extends along the second direction Y, an overlapping area exists between an orthographic projection of the first touch branch 71 on the substrate and an orthographic projection of the second branch 51 of the first power line on the substrate, and an overlapping area does not exist between an orthographic projection of the first touch branch 71 on the substrate and an orthographic projection of the first branch 41 of the first power line on the substrate.

In an exemplary embodiment, the at least one grid pattern further includes a second touch branch 72, and an area where an orthographic projection of the second touch branch 72 on the substrate, an orthographic projection of the second branch 51 of the first power line on the substrate, and an orthographic projection of the first branch 41 of the first power line on the substrate overlap each other.

In an exemplary embodiment, when the flexible display substrate is manufactured, the manufacturing process of the display substrate may include processes of peeling off the glass carrier, attaching the back film, cutting, and the like, and the disclosure is not limited herein.

In some exemplary embodiments, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass, quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some exemplary embodiments, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked, the first flexible material layer and the second flexible material layer may be made of Polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, the first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx), silicon oxide (SiOx), or the like, for improving the water and oxygen resistance of the substrate, and the semiconductor layer may be made of amorphous silicon (a-si).

In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, and the like. The anode layer can be made of transparent conductive materials such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer is called a Buffer (BUF) layer for improving the water and oxygen resistance of the substrate, the second insulating layer is called a first gate insulating (GI1) layer, the third insulating layer is called a second gate insulating (GI2) layer, and the fourth insulating layer is called an interlayer Insulating (ILD) layer. The first planar (PLN1) layer and the second planar (PLN2) layer may employ organic materials. The semiconductor layer may use polysilicon (p-Si) or oxide.

The display substrate of the embodiment of the disclosure effectively improves the light emitting efficiency of the light emitting device and saves the power consumption by enabling the orthographic projection area of the first anode connecting electrode on the substrate to be larger than the orthographic projection area of the second anode connecting electrode on the substrate and the orthographic projection area of the first opening on the substrate to be larger than the orthographic projection area of the second opening on the substrate. In addition, the preparation process disclosed by the invention can be well compatible with the existing preparation process, and is simple in process implementation, easy to implement, high in production efficiency, low in production cost and high in yield.

Table 1 shows a simulation result of a Long Range Uniformity (LRU) of the first power line (VDD) and the second power line (VSS) of the display substrate according to the embodiment of the disclosure, and fig. 16a is a graph of a simulation result of an IR Drop of the first power line (VDD). Fig. 16b is a graph showing the IR Drop simulation result of the second power line (VSS), and as can be seen from table 1, fig. 16a and fig. 16b, the voltage Drop (IR Drop) of VDD and VSS is reduced and the LRU is improved in the display substrate according to the embodiment of the disclosure.

TABLE 1

The structure of the display substrate and the preparation process thereof shown in the present disclosure are merely exemplary illustrations, and in some exemplary embodiments, the corresponding structure may be changed and the patterning process may be added or reduced according to actual needs, and the present disclosure is not limited herein. The structure of the display substrate and the manufacturing process thereof shown in the present disclosure are illustrated by taking the pixel circuit of 8T1C shown in fig. 3 as an example, in other exemplary embodiments, the pixel circuit may also be a structure such as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C, and the present disclosure is not limited thereto.

The present disclosure also provides a display device, which includes the display substrate. The display device may be: any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., but the embodiment of the present invention is not limited thereto.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims

1. A display substrate, comprising: the semiconductor layer, the fourth conducting layer, the second flat layer and the anode layer are sequentially arranged on the substrate;

2. A display substrate according to claim 1, wherein the first anode connection electrode comprises an electrode main body portion and an electrode projection portion provided on the electrode main body portion, wherein:

3. The display substrate according to claim 2, wherein a third conductive layer is further disposed on the substrate, the third conductive layer further comprises a plurality of first connecting electrodes, and an overlapping region exists between an orthographic projection of the electrode protrusion on the substrate and an orthographic projection of the first connecting electrodes on the substrate;

4. A display substrate according to claim 3, wherein there is an overlapping region between the orthographic projection of the second anode connecting electrode on the substrate and the orthographic projection of the first connecting electrode on the substrate, and the second anode connecting electrode is connected to the first connecting electrode through the via hole on the first flat layer.

5. The display substrate according to claim 1, wherein the second anode comprises an anode body portion and an anode protrusion portion disposed on the anode body portion, an orthogonal projection of the anode body portion on the substrate does not have an overlapping region with an orthogonal projection of the second anode connecting electrode on the substrate, an orthogonal projection of the anode protrusion portion on the substrate has an overlapping region with an orthogonal projection of the second anode connecting electrode on the substrate, and the second anode connecting electrode is connected to the anode protrusion portion through the second opening.

6. The display substrate according to claim 1, wherein the display substrate comprises a plurality of pixel units, at least one of the pixel units comprises a plurality of sub-pixels, at least one of the sub-pixels comprises a circuit unit and a light emitting device, at least one of the light emitting devices comprises a red light emitting device for emitting red light, a blue light emitting device for emitting blue light and a green light emitting device for emitting green light, and at least one of the circuit units comprises a first circuit unit connected to the red light emitting device, a second circuit unit connected to the blue light emitting device and a third circuit unit connected to the green light emitting device;

7. The substrate of claim 6, wherein at least one of the pixel units comprises a first circuit unit, a second circuit unit and two third circuit units, the plurality of circuit units form a plurality of unit rows and a plurality of unit columns, the unit columns comprise a first unit column and a second unit column, the first unit column comprises a plurality of first circuit units and second circuit units alternately arranged along the second direction, and the second unit column comprises a plurality of third circuit units arranged along the second direction.

8. A display substrate according to claim 1, wherein a third conductive layer is further disposed on the substrate, the third conductive layer further comprises a first branch of the first power line, the fourth conductive layer further comprises a second branch of the first power line, and wherein:

an overlapping area exists between the orthographic projection of the first branch of the first power line on the substrate and the orthographic projection of the second branch of the first power line on the substrate; the first branch of the first power line is electrically connected to the second branch of the first power line through a via.

9. The display substrate of claim 8, further comprising a touch structure layer disposed on the anode layer in a plane perpendicular to the display substrate, wherein the touch structure layer comprises a plurality of grid patterns, at least one of the grid patterns comprises a first touch branch, and wherein:

10. The display substrate of claim 9, wherein at least one of the grid patterns comprises a second touch branch, wherein:

11. The display substrate according to claim 8, wherein the fourth conductive layer further comprises a power supply connection electrode, wherein:

12. The display substrate of claim 8, wherein there is no overlapping area between the orthographic projection of the first anode on the base and the orthographic projection of the second branch of the first power line on the base; an overlapping area exists between the orthographic projection of the second anode on the substrate and the orthographic projection of the second branch of the first power supply line on the substrate.

13. The display substrate according to claim 8, wherein the second branch of the first power line is provided with a bending portion, and the bending portion is configured to make the distance between the second branches of the two first power lines at two sides of the first anode along the first direction larger than the distance between the second branches of the two first power lines outside the first anode along the first direction.

14. The display substrate of claim 8, wherein the second branch of the first power line has a smaller width near the first anode region than a width of the second branch of the first power line away from the first anode region.

15. A display device, comprising: a display substrate as claimed in any one of claims 1 to 14.