CN115835701A

CN115835701A - Display substrate, preparation method thereof and display device

Info

Publication number: CN115835701A
Application number: CN202211651921.5A
Authority: CN
Inventors: 龙祎璇; 承天一; 李孟; 尚庭华; 刘彪; 陈家兴; 牛佐吉; 徐鹏; 屈忆
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2023-03-21
Anticipated expiration: 2042-04-29
Also published as: CN115835701B

Abstract

A display substrate, a preparation method thereof and a display device are provided. The display substrate comprises a display area (100) and a binding area (200), wherein the display area (100) comprises M pixel rows which are sequentially arranged, at least one pixel row comprises a scanning signal line and a plurality of sub-pixels which are sequentially arranged along the extending direction of the scanning signal line, at least one sub-pixel comprises a pixel driving circuit which is connected with the scanning signal line, the pixel driving circuit at least comprises a storage capacitor (40) and a first transistor (T1) which is used as a first initialization transistor, and the scanning signal line at least comprises a second scanning signal line (32) which controls the first transistor (T1) to be switched on or off; in at least one pixel row, the second scanning signal line (32) is disposed on a side of the storage capacitor (40) near a display area Boundary (BD) which is an edge of the display area (100) near a binding area (200).

Description

Display substrate, preparation method thereof and display device

The present case is the divisional application of patent application 202280001029.4, and the application date of former application is: at 29/4/2022, application No.: 202280001029.4, the name invented and created: display substrate, preparation method thereof and display device.

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.

Background

Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, very high response speed, thinness, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and performing signal control by a Thin Film Transistor (TFT) has become a mainstream product in the Display field at present.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

In one aspect, the present disclosure provides a display substrate, including a display area and a binding area located on one side of the display area, where the display area includes M pixel rows sequentially arranged, and M is a positive integer greater than 1; at least one pixel row comprises a scanning signal line and a plurality of sub-pixels arranged in sequence along the extending direction of the scanning signal line, at least one sub-pixel comprises a pixel driving circuit connected with the scanning signal line, the pixel driving circuit at least comprises a storage capacitor and a plurality of transistors, the plurality of transistors at least comprise a first transistor serving as a first initialization transistor, the scanning signal line at least comprises a second scanning signal line, and the second scanning signal line is configured to control the first transistor to be switched on or switched off; in at least one pixel row, the second scanning signal line is arranged on one side of the storage capacitor close to a display area boundary, and the display area boundary is the edge of the display area close to one side of the binding area.

In an exemplary embodiment, a first pole of the first transistor is connected to a first initialization signal line disposed on a side of the storage capacitor near a boundary of the display area.

In an exemplary embodiment, an edge of the first initial signal line in the mth pixel row on a side close to the binding region forms a pixel driving circuit boundary.

In an exemplary embodiment, the pixel driving circuit boundary is located at a side of the display area boundary away from the binding area.

In an exemplary embodiment, the plurality of transistors further includes a seventh transistor as a second initialization transistor, and the scanning signal line further includes a first scanning signal line configured to control the seventh transistor to be turned on or off, the first scanning signal line being provided on a side of the storage capacitor away from the boundary of the display area.

In an exemplary embodiment, a first pole of the seventh transistor is connected to a second initial signal line provided on a side of the storage capacitor away from the boundary of the display area.

In an exemplary embodiment, a forward projection of the second preliminary signal line on the display substrate in the ith pixel row at least partially overlaps a forward projection of the second scan signal line on the display substrate in the ith-1 pixel row, i =2,3, \8230; \, M.

In an exemplary embodiment, the plurality of transistors further includes a second transistor as a compensation transistor and a fourth transistor as a data writing transistor, the scanning signal line further includes a third scanning signal line controlling the fourth transistor to be turned on or off and a fourth scanning signal line controlling the compensation transistor to be turned on or off, and the third scanning signal line and the fourth scanning signal line are disposed on a side of the storage capacitor near a boundary of the display region.

In an exemplary embodiment, the first scan signal line in the ith pixel row and the third scan signal line in the ith-1 pixel row are in an integral structure, i =2,3, \8230 \ 8230;, M.

In an exemplary embodiment, the plurality of transistors further includes a fifth transistor and a sixth transistor, the display region further includes a light emission control line configured to control the fifth transistor and the sixth transistor to be turned on or off, and the light emission control line is disposed on a side of the storage capacitor away from a boundary of the display region.

In an exemplary embodiment, the plurality of transistors further includes a second transistor as a compensation transistor, a third transistor as a driving transistor, a fourth transistor as a data writing transistor, fifth and sixth transistors as light emitting transistors, and a seventh transistor as a second initialization transistor; the first transistor, the second transistor, and the fourth transistor are provided on a side of the third transistor close to the boundary of the display area, and the fifth transistor, the sixth transistor, and the seventh transistor are provided on a side of the third transistor away from the boundary of the display area.

In an exemplary embodiment, the first and second transistors are oxide transistors, and the third to seventh transistors are low temperature polysilicon transistors.

In an exemplary embodiment, the scan signal lines include a first scan signal line controlling the seventh transistor to be turned on or off, a second scan signal line controlling the first transistor to be turned on or off, a third scan signal line controlling the fourth transistor to be turned on or off, and a fourth scan signal line controlling the second transistor to be turned on or off; in at least one pixel row, the first scanning signal line, the fourth scanning signal line, the third scanning signal line, and the second scanning signal line are sequentially arranged along a direction close to a boundary of the display region.

In an exemplary embodiment, the display region further includes a light emission control line controlling the fifth transistor and the sixth transistor to be turned on or off; in at least one pixel row, the first scanning signal line, the light emission control line, the fourth scanning signal line, the third scanning signal line, and the second scanning signal line are sequentially arranged along a direction close to a boundary of the display region.

In an exemplary embodiment, the display region further includes a first initial signal line connected to a first pole of the first transistor; in at least one pixel row, along a direction close to a boundary of the display region, the first scanning signal line, the light emission control line, the fourth scanning signal line, the third scanning signal line, the second scanning signal line, and the first initial signal line are sequentially arranged.

In an exemplary embodiment, in at least one pixel row, the plurality of pixel driving circuits are respectively connected to the plurality of anode patterns, and a minimum distance between at least one anode pattern and the boundary of the display area is smaller than a minimum distance between a seventh transistor of the pixel driving circuit to which the anode pattern is connected and the boundary of the display area.

In an exemplary embodiment, the plurality of anode electrode patterns connected to the plurality of pixel driving circuits in the same pixel row include a first anode electrode, a second anode electrode, a third anode electrode, and a fourth anode electrode, and a minimum distance between the first anode electrode or the second anode electrode and the display area boundary is smaller than a minimum distance between the third anode electrode and the display area boundary.

In an exemplary embodiment, the mth pixel row further includes a first initial signal line connected to the first electrode of the first transistor, and in the plurality of anode patterns connected to the plurality of pixel driving circuits in the mth pixel row, an orthogonal projection of the first anode or the second anode on the display substrate at least partially overlaps an orthogonal projection of the first initial signal line on the display substrate, and an orthogonal projection of the third anode or the fourth anode on the display substrate does not overlap an orthogonal projection of the first initial signal line on the display substrate.

In an exemplary embodiment, the mth pixel row further includes a second initial signal line connected to the first electrode of the seventh transistor, and in the plurality of anode patterns connected to the plurality of pixel driving circuits in the mth pixel row, an orthogonal projection of the first anode or the second anode on the display substrate does not overlap an orthogonal projection of the second initial signal line on the display substrate, and an orthogonal projection of the third anode or the fourth anode on the display substrate does not overlap an orthogonal projection of the second initial signal line on the display substrate.

In an exemplary embodiment, the display substrate includes a driving circuit layer disposed on a base and a light emitting structure layer disposed on a side of the driving circuit layer away from the base in a plane perpendicular to the display substrate; the driving circuit layer comprises a first semiconductor layer, a first conducting layer, a second semiconductor layer and a third conducting layer which are arranged along the direction far away from the substrate; the first semiconductor layer at least comprises an active layer of a plurality of polysilicon transistors, the first conducting layer at least comprises a first scanning signal line, a third scanning signal line, gate electrodes of the polysilicon transistors and a first polar plate of a storage capacitor, the second conducting layer at least comprises a second scanning signal line, a fourth scanning signal line, a first initial signal line, gate electrodes of the oxide transistors and a second polar plate of the storage capacitor, the second semiconductor layer at least comprises an active layer of the oxide transistors, and the third conducting layer at least comprises a second initial signal line.

On the other hand, the present disclosure also provides a display device, including the aforementioned display substrate.

In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, where the display substrate includes a display area and a binding area located on one side of the display area, the display area includes M pixel rows, and M is a positive integer greater than 1; at least one pixel row comprises a scanning signal line and a plurality of sub-pixels which are sequentially arranged along the extending direction of the scanning signal line, at least one sub-pixel comprises a pixel driving circuit which is connected with the scanning signal line, the pixel driving circuit at least comprises a storage capacitor and a plurality of transistors, the plurality of transistors at least comprise a first transistor which is used as a first initialization transistor, the scanning signal line at least comprises a second scanning signal line, and the second scanning signal line is configured to control the first transistor to be switched on or switched off; the preparation method comprises the following steps:

and forming a pixel driving circuit and a second scanning signal line in at least one pixel row, the second scanning signal line being disposed on a side of the storage capacitor near a display area boundary, the display area boundary being a boundary of the display area near the binding area side.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a schematic diagram of a display device;

FIG. 2 is a schematic view of a display substrate;

FIG. 3 is a schematic plan view of a display region of a display substrate;

FIG. 4 is a schematic cross-sectional view of a display region of a display substrate;

FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

FIG. 6 is a timing diagram of a pixel driving circuit;

fig. 7 is a schematic plan view illustrating a display substrate according to an exemplary embodiment of the disclosure;

fig. 8 is a schematic view after a first semiconductor layer pattern is formed according to an embodiment of the disclosure;

fig. 9a and 9b are schematic views after a first conductive layer pattern is formed according to an embodiment of the disclosure;

fig. 10a and 10b are schematic views after forming a second conductive layer pattern according to an embodiment of the disclosure;

fig. 11a and 11b are schematic views after a second semiconductor layer pattern is formed according to an embodiment of the present disclosure;

FIG. 12 is a schematic view illustrating a fifth insulating layer pattern according to an embodiment of the present disclosure;

fig. 13a and 13b are schematic views after a third conductive layer pattern is formed according to an embodiment of the disclosure;

FIG. 14 is a schematic view illustrating a first planarization layer pattern formed according to an embodiment of the present disclosure;

fig. 15a and 15b are schematic views after forming a fourth conductive layer pattern according to an embodiment of the disclosure;

FIG. 16 is a schematic view illustrating a second planarization layer pattern formed according to an embodiment of the present disclosure;

fig. 17a to 17d are schematic views illustrating an anode conductive layer pattern according to an embodiment of the disclosure;

fig. 18a and 18b are schematic views after forming a pixel defining layer pattern according to an embodiment of the disclosure;

fig. 19 is a schematic plan view of a conventional display substrate.

Description of reference numerals:

11 — a first active layer; 12 — a second active layer; 13 — a third active layer;

14-a fourth active layer; 15-a fifth active layer; 16-a sixth active layer;

17-a seventh active layer; 21-a first scanning signal line; 22-light emission control line;

23-third scanning signal lines; 24-a first plate; 31 — a first initial signal line;

32-second scanning signal lines; 33-fourth scanning signal line; 34-a second plate;

35-an opening; 40-storage capacitance; 51 — a first connecting electrode;

52-second connecting electrode; 53-third connecting electrode; 54 — a fourth connecting electrode;

55-fifth connecting electrode; 56-sixth connecting electrode; 57 — second initial signal line;

61-data signal lines; 62-a first power line; 63-anode connecting electrode;

90-an anode; 100-a display area; 101-a substrate;

102-a driving circuit layer; 103-light emitting structure layer; 104-packaging structure layer;

200-a binding region; 300-a border area; 400-pixel opening.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

The drawing scale in this disclosure may be referenced in the actual process, but is not limited thereto. For example: the width-length ratio of the channel, the thickness and the interval of each film layer and the width and the interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings, and the drawings described in the present disclosure are only schematic structural views, and one embodiment of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other, and "source terminal" and "drain terminal" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" means a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which an angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

In this specification, a triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like is not strictly defined, and may be an approximate triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like, and some small deformations due to tolerances may exist, and a lead angle, a curved edge, deformation, or the like may exist.

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller connected to the data driver, the scan driver and the light emitting driver, respectively, the data driver connected to the plurality of data signal lines (D1 to Dn), respectively, the scan driver connected to the plurality of scan signal lines (S1 to Sm), respectively, and the light emitting driver connected to the plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may supply a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, \8230; \8230, and Dn using the gray scale values and the control signals received from the timing controller. For example, the data driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, n may be a natural number. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, \8230; and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number. The light emitting driver may generate an emission signal to be supplied to the light emitting signal lines E1, E2, E3, \8230;, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo. For example, the light emission driver may be configured in the form of a shift register, and may generate the emission signal in such a manner that the emission stop signal provided in the form of off-level pulses is sequentially transmitted to the next stage circuit under the control of a clock signal, and o may be a natural number.

Fig. 2 is a schematic structural diagram of a display substrate. As shown in fig. 2, the display substrate may include a display area 100, a binding area 200 located at one side of the display area 100, and a bezel area 300 located at the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of subpixels Pxij constituting a pixel array, the plurality of subpixels Pxij being configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an effective area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as rolled, bent, folded, or rolled. In an exemplary embodiment, the display substrate may further include a display area boundary BD, which may be an edge of the display area 100 on a side close to the binding area 200.

In an exemplary embodiment, the bonding region 200 may include a fan-out region, a bending region, a driving chip region, and a bonding pin region sequentially arranged in a direction away from the display region, the fan-out region being connected to the display region and including a plurality of Data fan-out lines configured to connect Data signal lines (Data lines) of the display region in a fan-out (Fanout) routing manner. The bending region is connected to the fan-out region, and may include a composite insulating layer provided with a groove configured to bend the binding region to a rear surface of the display region. The driving chip region may include an Integrated Circuit (IC) configured to be connected to the plurality of data fan-out lines. The Bonding Pad area may include a Bonding Pad (Bonding Pad) configured to be bonded and connected to an external Flexible Printed Circuit (FPC).

In an exemplary embodiment, the bezel area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially disposed in a direction away from the display area. The circuit region is connected to the display region and may include at least a gate driving circuit connected to the first scanning signal line, the second scanning signal line, the third scanning signal line, and the emission control line of the pixel driving circuit in the display region. The power line region is connected to the circuit region and may include at least a power lead extending in a direction parallel to an edge of the display region and connected to the cathode in the display region. The crack dam region is connected to the power line region, and may include at least a plurality of cracks disposed on the composite insulating layer. The cutting area is connected to the crack dam area, and may at least include a cutting groove disposed on the composite insulating layer, and the cutting groove is configured such that after all the films of the display substrate are prepared, the cutting device cuts along the cutting groove, respectively.

In an exemplary embodiment, the fan-out area in the bonding area 200 and the power line area in the bezel area 300 may be provided with a first barrier dam and a second barrier dam, which may extend in a direction parallel to an edge of the display area, which is an edge of one side of the display area bonding area or the bezel area, forming a ring structure surrounding the display area.

Fig. 3 is a schematic plan view of a display region in a display substrate. As shown in fig. 3, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the pixel units P may include a first subpixel P1 emitting light of a first color, a second subpixel P2 emitting light of a second color, and third and fourth subpixels P3 and P4 emitting light of a third color. Each of the sub-pixels may include a circuit unit and a light emitting device, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the data signal line, and the light emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted from the data signal line and output a corresponding current to the light emitting device under control of the scan signal line and the light emitting signal line. The light emitting device in each sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light emitting device is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 and the fourth subpixel P4 may be a green subpixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be a rectangle, a Diamond, a pentagon or a hexagon, and the four sub-pixels may be arranged in a Diamond (Diamond) manner to form an RGBG pixel arrangement. In other exemplary embodiments, the four sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a square shape, or the like, and the disclosure is not limited thereto.

In an exemplary embodiment, the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a delta-shaped manner, or the like, and the disclosure is not limited thereto.

Fig. 4 is a schematic cross-sectional structure diagram of a display area in a display substrate, which illustrates the structure of four sub-pixels in the display area. As shown in fig. 4, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a package structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101, in a plane perpendicular to the display substrate. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, and the disclosure is not limited herein.

In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light emitting structure layer 103 of each sub-pixel may include a light emitting device formed by a plurality of film layers, and the plurality of film layers may include at least an anode, a pixel defining layer, an organic light emitting layer, and a cathode, the anode is connected to the pixel driving circuit, the organic light emitting layer is connected to the anode, the cathode is connected to the organic light emitting layer, and the organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer, which are stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material stacked structure, so that it is ensured that external water vapor cannot enter the light emitting structure layer 103.

In an exemplary embodiment, the organic light emitting layer may include an emission layer (EML) and any one or more of: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all the sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated from each other.

Fig. 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in fig. 5, the pixel driving circuit may include 7 transistors (first to seventh transistors T1 to T7) and 1 storage capacitor C, and the pixel driving circuit is connected to 10 signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a fourth scanning signal line S4, a light emitting signal line E, a first initialization signal line INIT1, a second initialization signal line INIT1, a first power supply line VDD, and a second power supply line VSS), respectively.

In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5, the second node N2 is connected to the second pole of the first transistor T1, the control pole of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6.

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the first power line VDD, and a second terminal of the storage capacitor C is connected to the second node N2, that is, the second terminal of the storage capacitor C is connected to the control electrode of the third transistor T3.

In an exemplary embodiment, a control electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor T1 is connected to the second node N2. When the turned-on scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the first initialization voltage to the second terminal of the storage capacitor C, thereby implementing initialization of the storage capacitor C.

In an exemplary embodiment, a control electrode of the second transistor T2 is connected to the fourth scan signal line S4, a first electrode of the second transistor T2 is connected to a second electrode of the first transistor T1, and a second electrode of the second transistor T2 is connected to the third node N3. When the turned-on scan signal is applied to the fourth scan signal line S4, the second transistor T2 connects the control electrode of the third transistor T3 with the second electrode of the third transistor T3.

In an exemplary embodiment, a control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, a first electrode of the third transistor T3 is connected to the first node N1, and a second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the light emitting device according to a potential difference between the control electrode and the first electrode thereof.

In an exemplary embodiment, a control electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1. When the turned-on scan signal is applied to the third scan signal line S3, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the first node N1.

In an exemplary embodiment, a control electrode of the fifth transistor T5 is connected to the light emitting signal line E, a first electrode of the fifth transistor T5 is connected to the first power source line VDD, and a second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the light emitting signal line E, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. When the turned-on light emission signal is applied to the light emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a driving current path between the first power supply line VDD and the light emitting device.

In an exemplary embodiment, a control electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the turned-on scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits a second initial voltage to the first pole of the light emitting device to initialize or release the amount of charges accumulated in the first pole of the light emitting device.

In an exemplary embodiment, the light emitting device may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or may be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

In an exemplary embodiment, the second pole of the light emitting device is connected to a second power line VSS, the second power line VSS being a low level signal, and the first power line VDD being a high level signal.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may employ a low temperature polysilicon transistor, or may employ an oxide transistor, or may employ a low temperature polysilicon transistor and a metal oxide transistor. The active layer of the Low Temperature polysilicon transistor adopts Low Temperature polysilicon (LTPS for short), and the active layer of the metal Oxide transistor adopts metal Oxide semiconductor (Oxide). The Low-Temperature Polycrystalline silicon transistor has the advantages of high mobility, high charging speed and the like, the Oxide transistor has the advantages of Low leakage current and the like, the Low-Temperature Polycrystalline silicon transistor and the metal Oxide transistor are integrated on one display substrate to form a Low-Temperature Polycrystalline Oxide (LTPO) display substrate, the advantages of the Low-Temperature Polycrystalline Oxide and the LTPO can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

Fig. 6 is a timing diagram of an operation of a pixel driving circuit. The exemplary embodiment of the present disclosure will be explained by the operation process of the pixel driving circuit illustrated in fig. 5, where the pixel driving circuit in fig. 5 includes 7 transistors (first to seventh transistors T1 to T7) and 1 storage capacitor C, the first and second transistors T1 and T2 are N-type oxide transistors, and the third to seventh transistors T3 to T7 are P-type low temperature polysilicon transistors. In an exemplary embodiment, the operation of the pixel driving circuit may include:

in the first phase A1, which is referred to as a reset phase, the signal of the second scanning signal line S2 is an on signal (high level), and the signals of the first scanning signal line S1, the third scanning signal line S3, the fourth scanning signal line S4, and the light-emitting signal line E are off signals. The conducting signal of the second scanning signal line S2 turns on the first transistor T1, and the signal of the first initialization signal line INIT1 is provided to the second node N2 through the first transistor T1, so as to initialize (reset) the storage capacitor C and clear the original charge in the storage capacitor. The turn-off signals of the first scanning signal line S1, the third scanning signal line S3, the fourth scanning signal line S4, and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the OLED does not emit light at this stage.

In the second stage A2, which is referred to as a data writing stage or a threshold compensation stage, signals of the first scanning signal line S1, the third scanning signal line S3, and the fourth scanning signal line S4 are on signals, signals of the second scanning signal line S2 and the light-emitting signal line E are off signals, and the data signal line D outputs a data voltage. At this stage, the second terminal of the storage capacitor C is at a low level, so the third transistor T3 is turned on. The turn-on signals of the first, third and fourth scan signal lines S1, S3 and S4 turn on the second, fourth and seventh transistors T2, T4 and T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the turned-on third node N3, and the turned-on second transistor T2, and a difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, the voltage of the second end (the second node N2) of the storage capacitor C is Vd- | Vth |, vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to supply the signal of the second initialization signal line INIT2 to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, clear the pre-stored voltage therein, complete the initialization, and ensure that the OLED does not emit light. The turn-off signal of the second scanning signal line S2 turns off the first transistor T1, and the turn-off signal of the light emitting signal line E turns off the fifth transistor T5 and the sixth transistor T6.

In the third stage A3, referred to as a light-emitting stage, a signal of the light-emitting signal line E is an on signal, and signals of the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3, and the fourth scanning signal line S4 are off signals. The on signal of the light emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output from the first power line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the OLED to emit light.

During driving of the pixel driving circuit, a driving current flowing through the third transistor T3 (driving transistor) is determined by a voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vdata- | Vth |, the driving current of the third transistor T3 is:

I＝K*(Vgs-Vth) ² ＝K*[(Vdd-Vd+|Vth|)-Vth] ² ＝K*[(Vdd-Vd] ²

where I is a driving current flowing through the third transistor T3, that is, a driving current driving the OLED, K is a constant, vgs is a voltage difference between the gate electrode and the first electrode of the third transistor T3, vth is a threshold voltage of the third transistor T3, vd is a data voltage output from the data signal line D, and Vdd is a power voltage output from the first power line Vdd.

With the development of the OLED display technology, the requirement of consumers for the display effect of the display product is higher and higher, and the extremely narrow frame becomes a new trend of the development of the display product, so that the narrowing of the frame and even the design without the frame are more and more emphasized in the design of the OLED display product. At present, a left frame, a right frame and an upper frame of a display device can be controlled within 1.0mm, but the narrowing design difficulty of a lower frame (a frame on one side of a binding area) is large and is always maintained at about 2.0 mm. In order to reduce the width of the lower frame, some display substrates mainly adopt a scheme of reducing the length of the fan-out area or the bending area, but under the existing process capability condition, the lower frame is still much larger than the left frame and the right frame.

Exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, a display substrate may include a display area and a binding area on one side of the display area, the display area including M pixel rows sequentially arranged, M being a positive integer greater than 1; at least one pixel row comprises a scanning signal line and a plurality of sub-pixels which are sequentially arranged along the extending direction of the scanning signal line, at least one sub-pixel comprises a pixel driving circuit which is connected with the scanning signal line, the pixel driving circuit at least comprises a storage capacitor and a plurality of transistors, the plurality of transistors at least comprise a first transistor which is used as a first initialization transistor, the scanning signal line at least comprises a second scanning signal line, and the second scanning signal line is configured to control the first transistor to be switched on or switched off; in at least one pixel row, the second scanning signal line is arranged on one side of the storage capacitor close to a display area boundary, and the display area boundary is the edge of the display area close to one side of the binding area.

In an exemplary embodiment, a distance between the pixel driving circuit boundary and the display region boundary is 6 μm to 10 μm.

Fig. 7 is a schematic plan view illustrating a structure of a display substrate according to an exemplary embodiment of the disclosure, which is a structure of a pixel driving circuit of an M-1 th pixel row and an M-th pixel row in a display region, which are close to a binding region. In an exemplary embodiment, the display substrate may include a display area 100 and a binding area 200 located at one side of the display area 100 in a second direction Y, the display area 100 may include M pixel rows sequentially arranged along the second direction Y, at least one pixel row may include a plurality of sub-pixels sequentially arranged along a first direction X, and M is a positive integer greater than 1. As shown in fig. 7, the mth row is the row of pixels closest to the display area boundary BD, the M-1 row is the row of pixels located on the mth row on the side away from the display area boundary BD, and the display area boundary BD is the edge of the display area 100 on the side closer to the binding area 200.

In an exemplary embodiment, a plurality of anodes provided for the display area each having an edge near one side of the binding area, an edge of the most near binding area among the plurality of anodes is referred to as an anode boundary, and the display area boundary BD may be a straight line passing through the anode boundary and extending in the first direction X.

In an exemplary embodiment, the display area boundary may be located within the display area or may be located within the binding area, and the display area boundary may be a related structural reference line having structural features. For example, the display area boundary may be the location of a barrier boundary within the binding area. As another example, the display area boundary may be the location within the binding area where the cathode ends. As another example, the display area boundary may be the position of the straight edge region of the fan-out trace within the binding region. For another example, the boundary of the display area may be the position of the data signal line in the bonding area for switching in (via hole), which is not limited in this disclosure.

In an exemplary embodiment, at least one pixel row may include a scan signal line extending along the first direction X, and at least one sub-pixel in one pixel row may include a pixel driving circuit connected to the scan signal line.

In an exemplary embodiment, the pixel driving circuit may include at least a plurality of transistors and a storage capacitor. The plurality of transistors in the pixel driving circuit may include at least a first transistor T1 as a first initialization transistor, the scan signal line may include at least a second scan signal line 32, and the second scan signal line 32 is configured to control on or off of the first transistor T1.

In an exemplary embodiment, the storage capacitor 40 may be located in a middle region of the subpixel second direction Y and may include a first plate and a second plate that are stacked.

In an exemplary embodiment, the second scan signal line 32 may be disposed at a side of the storage capacitor 40 near the display area boundary BD in at least one pixel row.

In an exemplary embodiment, the first transistor T1 may include a gate electrode, a first pole and a second pole, the gate electrode of the first transistor T1 may be connected to the second scan signal line 32, the first pole of the first transistor T1 may be connected to the first initializing signal line 31, and the first initializing signal line 31 may be disposed at a side of the storage capacitor 40 near the display area boundary BD.

In an exemplary embodiment, an edge of the first initial signal line 31 on a side close to the binding area 200 in the mth pixel row forms a pixel driving circuit boundary PD, and the pixel driving circuit boundary PD may be located on a side of the display area boundary BD away from the binding area 200.

In an exemplary embodiment, the distance L between the pixel driving circuit boundary PD and the display area boundary BD may be about 6 μm to 10 μm.

In an exemplary embodiment, the plurality of transistors in the pixel driving circuit may further include a seventh transistor T7 as the second initialization transistor, the scanning signal line may further include a first scanning signal line 21, the first scanning signal line 21 is configured to control on or off of the seventh transistor T7, and the first scanning signal line 21 is disposed on a side of the storage capacitor 40 away from the display area boundary BD.

In an exemplary embodiment, the seventh transistor T7 may include a gate electrode, a first pole and a second pole, the gate electrode of the seventh transistor T7 may be connected to the first scanning signal line 21, the first pole of the seventh transistor T7 may be connected to the second preliminary signal line 57, and the second preliminary signal line 57 may be disposed at a side of the storage capacitor 40 away from the display area boundary BD.

In an exemplary embodiment, the orthographic projection of the second preliminary signal line 57 on the display substrate in the ith pixel row at least partially overlaps the orthographic projection of the second scan signal line 32 on the display substrate in the ith-1 pixel row, i =2,3, \ 8230 \ 8230;, M.

In an exemplary embodiment, the plurality of transistors in the pixel driving circuit may further include a second transistor T2 as a compensation transistor and a fourth transistor T4 as a data writing transistor, the scanning signal line may further include a third scanning signal line 23 and a fourth scanning signal line 33, the third scanning signal line 23 may be configured to control on or off of the fourth transistor T4, the fourth scanning signal line 33 may be configured to control on or off of the second transistor T2, and the third scanning signal line 23 and the fourth scanning signal line 33 may be disposed on a side of the storage capacitor 40 near the display area boundary BD.

In an exemplary embodiment, the third scanning signal line 23 may be disposed at a side of the fourth scanning signal line 33 close to the display area boundary BD.

In an exemplary embodiment, the first scan signal line 21 in the ith pixel row and the third scan signal line 23 in the (i-1) th pixel row may be an integral structure.

In an exemplary embodiment, the plurality of transistors in the pixel driving circuit further include a fifth transistor T5 and a sixth transistor T6 as light emitting transistors, the display substrate may further include a light emitting control line 22, the light emitting control line 22 is configured to control the fifth transistor T5 and the sixth transistor T6 to be turned on or off, and the light emitting control line 22 is disposed at a side of the storage capacitor 40 away from the display area boundary BD.

In an exemplary embodiment, the plurality of transistors in the pixel driving circuit may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, fifth and sixth transistors T5 and T6 as light emitting transistors, and a seventh transistor T7 as a second initialization transistor. A first transistor T1 and a second transistor T2

In an exemplary embodiment, the fourth transistor T4 may be disposed at a side of the third transistor T3 close to the display area boundary BD, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be disposed at a side of the third transistor T3 far from the display area boundary BD.

In an exemplary embodiment, the first and second transistors T1 and T2 may be oxide transistors, and the third to seventh transistors T3 to T7 may be low temperature polysilicon transistors.

In an exemplary embodiment, the display substrate may include a driving circuit layer disposed on a base and a light emitting structure layer disposed on a side of the driving circuit layer away from the base in a plane perpendicular to the display substrate. The driving circuit layer may include a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a third conductive layer disposed in a direction away from the substrate. The first semiconductor layer may include at least active layers of a plurality of polysilicon transistors, the first conductive layer may include at least the first scan signal line 21, the third scan signal line 23, gate electrodes of the plurality of polysilicon transistors, and a first plate of the storage capacitor 40, the second conductive layer may include at least the second scan signal line 32, the fourth scan signal line 33, the first initialization signal line 31, gate electrodes of the plurality of oxide transistors, and a second plate of the storage capacitor 40, the second semiconductor layer may include at least active layers of a plurality of oxide transistors, and the third conductive layer may include at least the second initialization signal line 57.

In the present disclosure, the extension of a along the B direction means that a may include a main portion and a secondary portion connected to the main portion, the main portion being a line, a line segment or a bar-shaped body, the main portion extending along the B direction, and the length of the main portion extending along the B direction being greater than the length of the secondary portion extending along other directions. The phrase "a extends in the B direction" in the following description means "a main body portion of a extends in the B direction". In an exemplary embodiment, the second direction Y may be a direction pointing from the display area to the binding area, and an opposite direction of the second direction Y may be a direction pointing from the binding area to the display area.

The following is an exemplary description through a process of manufacturing a display substrate. The "patterning process" referred to in the present disclosure includes processes of coating a photoresist, mask exposure, development, etching, stripping a photoresist, and the like, for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposure, development, and the like, for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, and the disclosure is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, the term "a and B are disposed in the same layer" means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, the phrase "the orthographic projection of B is within the range of the orthographic projection of a" or "the orthographic projection of a includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of a, or the boundary of the orthographic projection of a overlaps the boundary of the orthographic projection of B.

In an exemplary embodiment, taking 8 sub-pixels in the M-1 th pixel row and the M-th pixel row near the display area boundary BD as an example, the preparation process of the display substrate may include the following operations.

(1) A substrate is prepared on a glass support plate. In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass, quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier plate. The first and second flexible material layers may be made of Polyimide (PI), polyethylene terephthalate (PET), or a polymer soft film with a surface treatment, the first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called Barrier (Barrier) layers, and the semiconductor layer may be made of amorphous silicon (a-si). In an exemplary embodiment, taking the stacked structure PI1/Barrier1/a-si/PI2/Barrier2 as an example, the preparation process may include: coating a layer of polyimide on a glass carrier plate, and forming a first flexible (PI 1) layer after curing and film forming; subsequently depositing a Barrier film on the first flexible layer to form a first Barrier (Barrier 1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and forming a second flexible (PI 2) layer after curing and film forming; and then depositing a Barrier film on the second flexible layer to form a second Barrier (Barrier 2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

(2) A first semiconductor layer pattern is formed. In an exemplary embodiment, the forming of the first semiconductor layer pattern may include: a first insulating film and a first semiconductor film are sequentially deposited on a substrate, and the first semiconductor film is patterned through a patterning process to form a first insulating layer covering the substrate and a first semiconductor layer pattern disposed on the first insulating layer, as shown in fig. 8.

In an exemplary embodiment, the first semiconductor layer pattern of each sub-pixel may include at least the third to seventh active layers 13 to 17 of the third to seventh transistors T3 to T7, and the third to seventh active layers 13 to 17 are integrated structures connected to each other.

In an exemplary embodiment, in the first direction X, the sixth active layer 16 may be positioned at one side of the third active layer 13 in the present sub-pixel, and the fourth active layer 14 and the fifth active layer 15 may be positioned at the other side of the third active layer 13 in the present sub-pixel. In the second direction Y, the fourth active layer 14 in the ith row of sub-pixels may be located at one side of the third active layer 13 in the second direction Y in the present sub-pixels (i.e., a side close to the boundary BD of the display area), and the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 in the ith row of sub-pixels may be located at one side opposite to the second direction Y of the third active layer 13 in the present sub-pixels (i.e., a side far from the boundary BD of the display area), i =2,3, 8230,' \8230, M.

In an exemplary embodiment, the third active layer 13 may have an inverted "Ω" shape, and the fourth to seventh active layers 14 to 17 may have an "I" shape.

In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 13-1 of the third active layer 13 may simultaneously serve as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, the second region 13-2 of the third active layer 13 may simultaneously serve as the first region 16-1 of the sixth active layer 16, the second region 16-2 of the sixth active layer 16 may simultaneously serve as the second region 17-2 of the seventh active layer 17, and the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, and the first region 17-1 of the seventh active layer 17 may be separately provided.

In an exemplary embodiment, the first region 17-1 of the seventh active layer 17 in the ith row of subpixels may be disposed in the ith-1 row of subpixels, i =2,3, \8230;, M.

In an exemplary embodiment, the first regions 15-1 of the fifth active layer 15 in adjacent two sub-pixels in one pixel row may be connected to each other. For example, the first region 15-1 of the fifth active layer 15 of the (N-2) th column and the first region 15-1 of the fifth active layer 15 of the (N-1) th column are connected to each other, the first region 15-1 of the fifth active layer 15 of the (N) th column and the first region 15-1 of the fifth active layer 15 of the (N + 1) th column are connected to each other, and the first region 15-1 of the fifth active layer 15 of the (N + 2) th column and the first region 15-1 of the fifth active layer 15 of the (N + 3) th column are connected to each other. In an exemplary embodiment, since the first region of the fifth active layer in each sub-pixel is configured to be connected to the first power line formed later, the first electrodes of the fifth transistors T5 of the adjacent sub-pixels can be ensured to have the same potential by forming the first regions of the fifth active layers of the adjacent sub-pixels into an integral structure connected to each other, which is beneficial to improving the uniformity of the panel, avoiding the display defect of the display substrate, and ensuring the display effect of the display substrate.

In an exemplary embodiment, the first semiconductor layer may use polysilicon (p-Si), that is, the first to sixth transistors are LTPS thin film transistors. In an exemplary embodiment, patterning the first semiconductor thin film through a patterning process may include: an amorphous silicon (a-si) thin film is formed on a first insulating thin film, dehydrogenation treatment is performed on the amorphous silicon thin film, and crystallization treatment is performed on the amorphous silicon thin film after the dehydrogenation treatment to form a polycrystalline silicon thin film. Then, the polysilicon thin film is patterned to form a first semiconductor layer pattern.

(3) A first conductive layer pattern is formed. In an exemplary embodiment, the forming of the first conductive layer pattern may include: on the substrate on which the aforementioned patterns are formed, a second insulating film and a first conductive film are sequentially deposited, and the first conductive film is patterned through a patterning process to form a second insulating layer covering the first semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer, as shown in fig. 9a and 9b, where fig. 9b is a schematic plan view of the first conductive layer in fig. 9 a. In an exemplary embodiment, the first conductive layer may be referred to as a first GATE metal (GATE 1) layer.

In an exemplary embodiment, the first conductive layer pattern of each sub-pixel includes at least: a first scanning signal line 21, a light emission control line 22, a third scanning signal line 23, and a first plate 24 of a storage capacitor.

In an exemplary embodiment, the first plate 24 may have a rectangular shape, corners of the rectangular shape may be provided with chamfers, and an orthographic projection of the first plate 24 on the substrate may at least partially overlap with an orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first plate 24 may serve as both one plate of the storage capacitor and the gate electrode of the third transistor T3.

In an exemplary embodiment, the shape of the first scanning signal line 21 may be a zigzag shape in which a main portion extends along the first direction X, the first scanning signal line 21 in the i-th row of sub-pixels may be located on a side opposite to the second direction Y of the first plate 24 of the sub-pixel (i.e., a side away from the display region boundary BD), and a region where the first scanning signal line 21 overlaps with the seventh active layer of the sub-pixel serves as a gate electrode of the seventh transistor T7.

In an exemplary embodiment, the first scan signal line 21 in the ith row of sub-pixels may be disposed in the (i-1) th row of sub-pixels.

In an exemplary embodiment, the shape of the emission control line 22 may be a line shape in which the main body portion extends along the first direction X, the emission control line 22 in the ith row of sub-pixels may be located on a side opposite to the second direction Y of the first plate 24 (i.e., a side away from the display region boundary BD) and between the first plate 24 and the first scan signal line 21, a region where the emission control line 22 overlaps with the fifth active layer of the present sub-pixel serves as the gate electrode of the fifth transistor T5, and a region where the emission control line 22 overlaps with the sixth active layer of the present sub-pixel serves as the gate electrode of the sixth transistor T6.

In an exemplary embodiment, the third scanning signal line 23 may have a broken line shape in which a main portion extends along the first direction X, the third scanning signal line 23 in the i-th row of sub-pixels may be located on one side of the first plate 24 of the sub-pixel in the second direction Y (i.e., on a side close to the display region boundary BD), and a region where the third scanning signal line 23 overlaps with the fourth active layer of the sub-pixel serves as the gate electrode of the fourth transistor T4.

In an exemplary embodiment, the third scanning signal line 23 in the sub-pixel of the i-1 th row may be used as the first scanning signal line 21 in the sub-pixel of the i-1 th row, i.e., the third scanning signal line 23 of the i-1 th row and the first scanning signal line 21 in the i-th row are integrally configured.

In an exemplary embodiment, the first scanning signal line 21, the light-emitting control line 22 and the third scanning signal line 23 may be designed to have unequal widths, and the widths of the first scanning signal line 21, the light-emitting control line 22 and the third scanning signal line 23 are the size of the second direction Y, which may not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, and the disclosure is not limited herein.

In an exemplary embodiment, the first and third

scanning signal lines

21 and 23 may include an overlapping region with the first semiconductor layer and a non-overlapping region with the first semiconductor layer, and the widths of the first and third

scanning signal lines

21 and 23 of the overlapping region with the first semiconductor layer may be smaller than the widths of the first and third

scanning signal lines

21 and 23 of the non-overlapping region with the first semiconductor layer. In an exemplary embodiment, the widths LS1 of the first and third

scan signal lines

21 and 23 at the overlapping region with the first semiconductor layer may be about 3.6 μm to 4.0 μm. For example, the width LS1 may be about 3.8 μm.

In an exemplary embodiment, the emission control line 22 may include an overlapping region with the first semiconductor layer and a non-overlapping region with the first semiconductor layer, and a width of the first scan signal line 21 of the overlapping region with the first semiconductor layer may be greater than a width of the first scan signal line 21 of the non-overlapping region with the first semiconductor layer. In an exemplary embodiment, the width LEM of the first scan signal line 21 in a non-overlapping region with the first semiconductor layer may be about 1.8 μm to 2.2 μm. For example, the width LEM may be about 2.0 μm or so.

In an exemplary embodiment, after the first conductive layer pattern is formed, the first semiconductor layer may be subjected to a conductivation process using the first conductive layer as a mask, the first semiconductor layer of a region masked by the first conductive layer forms channel regions of the third to seventh transistors T3 to T7, and the first semiconductor layer of a region not masked by the first conductive layer is subjected to a conductivation, that is, both the first and second regions of the third to seventh active layers are subjected to a conductivation.

(4) Forming a second conductive layer pattern. In an exemplary embodiment, the forming of the second conductive layer pattern may include: as shown in fig. 10a and 10b, fig. 10b is a schematic plan view of the second conductive layer in fig. 10a, and fig. 10b is a schematic plan view of the second conductive layer in fig. 10 a. In an exemplary embodiment, the second conductive layer may be referred to as a second GATE metal (GATE 2) layer.

In an exemplary embodiment, the second conductive layer pattern of each sub-pixel includes at least: a first initial signal line 31, a second scanning signal line 32, a fourth scanning signal line 33, and a second plate 34 of a storage capacitor.

In an exemplary embodiment, the second plate 34 may have a rectangular shape, corners of the rectangular shape may be provided with chamfers, an orthogonal projection of the second plate 34 on the substrate may at least partially overlap an orthogonal projection of the first plate 24 on the substrate, the second plate 34 may serve as the other plate of the storage capacitor, and the first plate 24 and the second plate 34 constitute the storage capacitor of the pixel driving circuit. The second plate 34 is provided with an opening 35, and the opening 35 may be rectangular and may be located in the middle of the second plate 34, so that the second plate 34 forms a ring structure. The opening 35 exposes the third insulating layer covering the first plate 24, and the orthographic projection of the first plate 24 on the substrate includes the orthographic projection of the opening 35 on the substrate. In an exemplary embodiment, the opening 35 is configured to receive a subsequently formed first via, which is located within the opening 35 and exposes the first plate 24, connecting the second pole of the subsequently formed first transistor T1 with the first plate 24.

In an exemplary embodiment, the second plates 34 in adjacent two sub-pixels in one pixel row may be connected to each other. For example, the second plate 34 of the N-2 th column and the second plate 34 of the N-1 th column may be connected to each other by the first connection bar 34. For another example, the second plate 34 of the nth column and the second plate 34 of the N +1 th column are connected to each other by a second connection bar 35. For another example, the second plate 34 of the (N + 2) th column and the second plate 34 of the (N + 3) th column are connected to each other by a second connecting bar 35. In an exemplary embodiment, since the second plate 34 in each sub-pixel is connected to the first power line formed subsequently, and the second plates 34 of adjacent sub-pixels are formed into an integrated structure connected to each other, the second plates of the integrated structure can be reused as power signal lines, so that multiple second plates in a pixel row can have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

In an exemplary embodiment, the first preliminary signal line 31 may have a linear shape in which a main portion extends along the first direction X, and the first preliminary signal line 31 in the ith row of sub-pixels may be located on one side of the second plate 34 of the sub-pixel in the second direction Y (i.e., on a side close to the display area boundary BD).

In an exemplary embodiment, the width LIN1 of the first preliminary signal line 31 may be about 1.8 μm to 2.2 μm. For example, the width of the first preliminary signal line 31 may be about 2.0 μm or so.

In an exemplary embodiment, the first preliminary signal line 31 of the mth pixel row may form a pixel driving circuit boundary, and the distance L between the first preliminary signal line 31 and the display area boundary BD may be about 6 μ M to 10 μ M. For example, the distance L may be about 7.99 μm or so.

In an exemplary embodiment, the second scanning signal line 32 may have a polygonal line shape in which the main portion extends along the first direction X, the second scanning signal line 32 in the ith row of sub-pixels may be located on one side of the second plate 34 of the sub-pixel in the second direction Y (i.e., on a side close to the display area boundary BD), and the second scanning signal line 32 may be located between the first initial signal line 31 and the second plate 34.

In an exemplary embodiment, the second scanning signal line 32 may be positioned between the first preliminary signal line 31 and the third scanning signal line 23.

In an exemplary embodiment, the fourth scanning signal line 33 may have a line shape in which the main portion extends along the first direction X, the fourth scanning signal line 33 in the ith row of sub-pixels may be positioned at one side of the second plate 34 of the sub-pixel in the second direction Y (i.e., at a side close to the boundary BD of the display area), and the fourth scanning signal line 33 may be positioned between the second scanning signal line 32 and the second plate 34.

In an exemplary embodiment, the fourth scanning signal line 33 may be positioned between the third scanning signal line 23 and the second plate 34.

In an exemplary embodiment, the second scanning signal line 32 and the fourth scanning signal line 33 may be designed to have unequal widths, and the widths of the second scanning signal line 32 and the fourth scanning signal line 33 are the size of the second direction Y, which may not only facilitate layout of the pixel structure, but also reduce parasitic capacitance between the signal lines, and the disclosure is not limited herein.

In an exemplary embodiment, the second scan signal line 32 may include an overlapping region with a subsequently formed second semiconductor layer and a non-overlapping region with the second semiconductor layer, and a width of the second scan signal line 32 in the overlapping region with the second semiconductor layer may be greater than a width of the second scan signal line 32 in the non-overlapping region with the second semiconductor layer. In an exemplary embodiment, the width LS2 of the second scan signal line 32 in the non-overlapping region with the second semiconductor layer may be about 2.2 μm to 2.6 μm. For example, the width LS2 may be about 2.4 μm or so.

In an exemplary embodiment, the fourth scan signal line 33 may include an overlapping region with a subsequently formed second semiconductor layer and a non-overlapping region with the second semiconductor layer, and a width of the fourth scan signal line 33 in the overlapping region with the second semiconductor layer may be greater than a width of the fourth scan signal line 33 in the non-overlapping region with the second semiconductor layer. In an exemplary embodiment, the width LS3 of the fourth scan signal line 33 in a region not overlapping with the second semiconductor layer may be about 1.8 μm to 2.2 μm. For example, the width LS3 may be about 2.0 μm or so.

(5) A second semiconductor layer pattern is formed. In an exemplary embodiment, the forming of the second semiconductor layer pattern may include: on the substrate on which the aforementioned pattern is formed, a fourth insulating film and a second semiconductor film are sequentially deposited, and the second semiconductor film is patterned through a patterning process to form a fourth insulating layer covering the substrate and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in fig. 11a and 11b, where fig. 11b is a schematic plan view of the second semiconductor layer in fig. 11 a.

In an exemplary embodiment, the second semiconductor layer pattern of each sub-pixel includes at least: a first active layer 11 of the first transistor T1 and a second active layer 12 of the second transistor T2.

In an exemplary embodiment, the shape of the first active layer 11 may be in an "I" shape, an orthographic projection of the first active layer 11 on the substrate at least partially overlaps an orthographic projection of the second scan signal line 32 on the substrate, and a region of the second scan signal line 32 overlapping the first active layer 11 of the present sub-pixel serves as a gate electrode of the first transistor T1.

In an exemplary embodiment, the first region 11-1 of the first active layer 11 may be located at one side of the second direction Y of the second scanning signal line 32 (i.e., a side close to the display area boundary BD), and the second region 11-2 of the first active layer 11 may be located at one side opposite to the second direction Y of the second scanning signal line 32 (i.e., a side far from the display area boundary BD).

In an exemplary embodiment, the shape of the second active layer 12 may be in an "I" shape, an orthographic projection of the second active layer 12 on the substrate at least partially overlaps an orthographic projection of the fourth scan signal line 33 on the substrate, and a region of the fourth scan signal line 33 overlapping the second active layer 12 of the present sub-pixel serves as a gate electrode of the second transistor T2.

In an exemplary embodiment, the first region 12-1 of the second active layer 12 may be located at a side of the fourth scanning signal line 33 in the second direction Y (i.e., a side close to the display area boundary BD), and the second region 12-2 of the second active layer 12 may be located at a side opposite to the second direction Y of the fourth scanning signal line 33 (i.e., a side far from the display area boundary BD).

In an exemplary embodiment, the second region 11-2 of the first active layer 11 may serve as the first region 12-1 of the second active layer 12, i.e., the second region 11-2 of the first active layer 11 and the first region 12-1 of the second active layer 12 are integrally connected to each other, and may be located between the second scan signal line 32 and the fourth scan signal line 33.

In an exemplary embodiment, an orthogonal projection of the second region 11-2 of the first active layer 11 and the first region 12-1 of the second active layer 12 of the integral structure in the sub-pixel of the ith row on the substrate at least partially overlaps an orthogonal projection of the third scan signal line 23 in the sub-pixel of the ith row on the substrate, and an orthogonal projection of the second region 11-2 of the first active layer 11 and the first region 12-1 of the second active layer 12 of the integral structure in the sub-pixel of the ith row on the substrate at least partially overlaps an orthogonal projection of the third scan signal line 23 in the sub-pixel of the ith row 1 (i.e., the first scan signal line 21 in the sub-pixel of the ith row) on the substrate.

In an exemplary embodiment, the second semiconductor layer may employ an oxide, that is, the first transistor T1 and the second transistor T2 are oxide transistors. In an exemplary embodiment, the second semiconductor thin film may employ Indium Gallium Zinc Oxide (IGZO) having higher electron mobility than amorphous silicon.

(6) Forming a fifth insulating layer pattern. In an exemplary embodiment, the forming of the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the pattern is formed, patterning the fifth insulating film by using a patterning process to form a fifth insulating layer covering the second semiconductor layer, wherein a plurality of via holes are formed in the fifth insulating layer, as shown in fig. 12.

In an exemplary embodiment, the plurality of vias of each sub-pixel includes at least: the first via hole V1, the second via hole V2, the third via hole V3, the fourth via hole V4, the fifth via hole V5, the sixth via hole V6, the seventh via hole V7, the eighth via hole V8, the ninth via hole V9, the tenth via hole V10, and the eleventh via hole V11.

In an exemplary embodiment, an orthographic projection of the first via hole V1 on the substrate is located within an orthographic projection of the opening 35 on the substrate, and the fifth insulating layer, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first plate 24. The first via V1 is configured to connect a second pole of the subsequently formed first transistor T1 with the first plate 24 through the via.

In an exemplary embodiment, the second via V2 is located within an orthographic projection of the second plate 34 on the substrate, and the fifth and fourth insulating layers within the second via V2 are etched away to expose a surface of the second plate 34. The second via V2 is configured to connect the first pole of the subsequently formed fifth transistor T5 with the second pole plate 34 through the via.

In an exemplary embodiment, an orthographic projection of the third via hole V3 on the substrate is within an orthographic projection of the first region of the fifth active layer on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the third via hole V3 are etched away to expose a surface of the first region of the fifth active layer, and the third via hole V3 is configured to connect the first electrode of the subsequently formed fifth transistor T5 with the first region of the fifth active layer through the via hole.

In an exemplary embodiment, an orthographic projection of the fourth via V4 on the substrate is within an orthographic projection of the second region of the sixth active layer on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fourth via V4 are etched away to expose a surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the fourth via V4 is configured to connect the second pole of the subsequently formed sixth transistor T6 (the second pole of the seventh transistor T7) with the second region of the sixth active layer through the via.

In an exemplary embodiment, an orthographic projection of the fifth via V5 on the substrate is located within an orthographic projection of the first region of the fourth active layer on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via V5 are etched away to expose a surface of the first region of the fourth active layer, and the fifth via V5 is configured to connect the first pole of the subsequently formed fourth transistor T4 with the first region of the fourth active layer through the via.

In an exemplary embodiment, an orthographic projection of the sixth via V6 on the substrate is within an orthographic projection of the second region of the third active layer on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via V6 are etched away to expose a surface of the second region of the third active layer (also the first region of the sixth active layer), and the sixth via V6 is configured such that the second pole of the subsequently formed third transistor T3 (the first pole of the sixth transistor T6) is connected to the second region of the third active layer through the via.

In an exemplary embodiment, an orthographic projection of the seventh via V7 on the substrate is within an orthographic projection of the first region of the seventh active layer on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the seventh via V7 are etched away to expose a surface of the first region of the seventh active layer, and the seventh via V7 is configured to connect the first pole of the subsequently formed seventh transistor T7 with the first region of the seventh active layer through the via.

In an exemplary embodiment, an orthographic projection of the eighth via V8 on the substrate is within an orthographic projection of the first region of the first active layer on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose a surface of the first region of the first active layer, and the eighth via V8 is configured to connect the first pole of the subsequently formed first transistor T1 with the first region of the first active layer through the via.

In an exemplary embodiment, an orthographic projection of the ninth via V9 on the substrate is within an orthographic projection of the second region of the second active layer on the substrate, the fifth insulating layer within the ninth via V9 is etched away to expose a surface of the second region of the second active layer, and the ninth via V9 is configured to connect the second pole of the subsequently formed second transistor T2 with the second region of the second active layer through the via.

In an exemplary embodiment, an orthographic projection of the tenth via V10 on the substrate is located within an orthographic projection of the second region of the first active layer on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via V10 are etched away to expose a surface of the second region of the first active layer (also the first region of the second active layer), and the tenth via V10 is configured to connect a second pole of the first transistor T1 (also the first pole of the second transistor T2) to be subsequently formed with the second region of the first active layer through the via.

In an exemplary embodiment, an orthographic projection of the eleventh via V11 on the substrate is within a range of an orthographic projection of the first preliminary signal line 31 on the substrate, the fifth and fourth insulating layers within the eleventh via V11 are etched away to expose a surface of the first preliminary signal line 31, and the eleventh via V11 is configured to connect a first electrode of the subsequently formed first transistor T1 with the first preliminary signal line 31 through the via.

(7) Forming a third conductive layer pattern. In an exemplary embodiment, the forming of the third conductive layer may include: depositing a third conductive film on the substrate on which the pattern is formed, and patterning the third conductive film by a patterning process to form a third conductive layer disposed on the fifth insulating layer, as shown in fig. 13a and 13b, where fig. 13b is a schematic plan view of the third conductive layer in fig. 13 a. In an exemplary embodiment, the third conductive layer may be referred to as a third GATE metal (GATE 3) layer.

In an exemplary embodiment, the third conductive layer of each sub-pixel includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, and a second initial signal line 57.

In an exemplary embodiment, the first connection electrode 51 may have a zigzag shape in which a body portion extends in the second direction Y, a first end of the first connection electrode 51 is connected to the first electrode plate 24 through the first via V1, and a second end of the first connection electrode 51 extends in the second direction Y and then is connected to the second region of the first active layer (also, the first region of the second active layer) through the tenth via V10 such that the first electrode plate 24, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 51 may serve as both the second pole of the first transistor T1 and the first pole (the second node N2) of the second transistor T2.

In an exemplary embodiment, the second connection electrode 52 may have a shape of a bar extending along the first direction X, a first end of the second connection electrode 52 is connected to the first region of the first active layer through an eighth via V8, and a second end of the second connection electrode 52 is connected to the first initiation signal line 31 through an eleventh via V11, so that the first initiation voltage transmitted by the first initiation signal line 31 is written to the first pole of the first transistor T1. In an exemplary embodiment, the second connection electrode 52 may serve as a first pole of the first transistor T1.

In an exemplary embodiment, in each pixel row, the second connection electrode 52 of the N-1 th column and the second connection electrode 52 of the nth column may be integrally connected to each other, and the second connection electrode 52 of the N +1 th column and the second connection electrode 52 of the N +2 th column may be integrally connected to each other.

In an exemplary embodiment, the third connection electrode 53 may have a rectangular shape, and the third connection electrode 53 is connected to the first region of the fourth active layer through the fifth via hole V5. In an exemplary embodiment, the third connection electrode 53 may serve as a first electrode of the fourth transistor T4 and be configured to be connected to a data signal line to be formed later.

In an exemplary embodiment, the fourth connection electrode 54 may have a "Y" shape, a first end of the fourth connection electrode 54 is connected to the second plate 34 through the second via V2, and a second end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through the third via V3, thereby achieving that the first electrode of the fifth transistor T5 and the second plate 34 of the storage capacitor in the sub-pixel have the same potential. In an exemplary embodiment, the fourth connection electrode 54 may serve as a first electrode of the fifth transistor T5.

In an exemplary embodiment, an orthographic projection of the fourth connection electrode 54 on the substrate at least partially overlaps with an orthographic projection of the second region of the seventh active layer on the substrate.

In an exemplary embodiment, in each pixel row, the fourth connection electrode 54 of the N-2 th column and the fourth connection electrode 54 of the N-1 st column may be an integrally connected structure, the fourth connection electrode 54 of the N-th column and the fourth connection electrode 54 of the N +1 th column may be an integrally connected structure, and the fourth connection electrode 54 of the N +2 th column and the fourth connection electrode 54 of the N +3 th column may be an integrally connected structure. In the exemplary embodiment, since the fourth connection electrode 54 in each sub-pixel is connected to the first power line formed subsequently, the fourth connection electrodes 54 of the adjacent sub-pixels are connected to each other to form an integrated structure, so that the fourth connection electrodes 54 of the adjacent sub-pixels can be guaranteed to have the same potential, the first pole of the fifth transistor T5 in the adjacent sub-pixels can have the same potential, and the second poles 34 of the storage capacitors in the adjacent sub-pixels can have the same potential, which is beneficial to improving the uniformity of the panel, avoiding the display defects of the display substrate, and guaranteeing the display effect of the display substrate.

In an exemplary embodiment, the fifth connection electrode 55 may have a rectangular shape, a first end of the fifth connection electrode 55 is connected to the second region of the third active layer (also, the first region of the sixth active layer) through the sixth via V6, and a second end of the fifth connection electrode 55 is connected to the second region of the second active layer through the ninth via V9. The fifth connection electrode 55 may simultaneously serve as the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole (the third node N3) of the sixth transistor T6.

In an exemplary embodiment, the sixth connection electrode 56 may have a rectangular shape, and the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4. In an exemplary embodiment, the sixth connection electrode 56 may serve as both the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, and the sixth connection electrode 56 is configured to be connected to a subsequently formed anode connection electrode.

In an exemplary embodiment, the second initial signal line 57 may be a polygonal line shape having a main portion extending along the first direction X, the second initial signal line 57 may be disposed at a side of the storage capacitor away from the display area boundary BD, and the second initial signal line 57 may be connected to the first region of the seventh active layers through the seventh via holes V7 in the pixel row to write the second initial voltage to the seventh transistors T7 in the pixel row. In the exemplary embodiment, since the second initial signal line 57 is connected to the first regions of all the seventh active layers in one pixel row, the first electrodes of all the seventh transistors T7 in one pixel row can be ensured to have the same potential, which is beneficial to improving the uniformity of the panel, avoiding the display defects of the display substrate, and ensuring the display effect of the display substrate. In an exemplary embodiment, the width LIN2 of the second preliminary signal line 57 may be about 1.9 μm to 2.3 μm. For example, the width of the second preliminary signal line 57 may be about 2.1 μm or so.

In an exemplary embodiment, the second initial signal line 57 of the ith pixel row may be located within the area where the (i-1) th pixel row is located.

(8) A first planarization layer pattern is formed. In an exemplary embodiment, forming the first flat layer pattern may include: coating a first flat film on the substrate with the pattern, patterning the first flat film by a patterning process to form a first flat layer covering the third conductive layer pattern, wherein the first flat layer is provided with a plurality of via holes, as shown in fig. 14.

In an exemplary embodiment, the plurality of vias in each sub-pixel includes at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

In an exemplary embodiment, an orthographic projection of the twenty-first via V21 on the substrate is within an orthographic projection of the third connection electrode 53 on the substrate, the first planarization layer in the twenty-first via V21 is etched away to expose a surface of the third connection electrode 53, and the twenty-first via V21 is configured to connect a subsequently formed data signal line to the third connection electrode 53 through the via.

In an exemplary embodiment, an orthographic projection of the twenty-second via V22 on the substrate is located within an orthographic projection of the first sub-electrode 54-1 of the fourth connection electrode 54 on the substrate, the first planarization layer within the twenty-second via V22 is etched away to expose a surface of the first sub-electrode 54-1, and the twenty-second via V22 is configured to connect a subsequently formed first power line via with the fourth connection electrode 54.

In an exemplary embodiment, an orthographic projection of the twenty-third via V23 on the substrate is located within an orthographic projection of the sixth connection electrode 56 on the substrate, the first planarization layer in the twenty-third via V23 is etched away to expose a surface of the sixth connection electrode 56, and the twenty-third via V232 is configured to connect a subsequently formed anode connection electrode with the sixth connection electrode 56.

(9) Forming a fourth conductive layer pattern. In an exemplary embodiment, the forming of the fourth conductive layer may include: a fourth conductive film is deposited on the substrate with the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the first planarization layer, as shown in fig. 15a and 15b, where fig. 15b is a schematic plan view of the fourth conductive layer in fig. 15 a. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source drain metal (SD 1) layer.

In an exemplary embodiment, the fourth conductive layer of each sub-pixel includes at least: a data signal line 61, a first power line 62, and an anode connection electrode 63.

In an exemplary embodiment, the data signal line 61 may have a shape of a straight line having a body portion extending in the second direction Y, and the data signal line 61 is connected to the third connection electrode 53 through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the connection of the data signal line 61 to the first pole of the fourth transistor T4 is accomplished, and the data signal is written to the first pole of the fourth transistor T4.

In an exemplary embodiment, the first power line 62 may have a shape of a zigzag with a body portion extending in the second direction Y, and the first power line 62 is connected to the fourth connection electrode 54 through the twelfth via V22. Since the fourth connection electrode 54 is connected to the second electrode 34 and the first region of the fifth active layer through via holes, respectively, the connection of the first power line 62 to the second electrode 34 and the first pole of the fifth transistor T5 is accomplished, and a power signal is written to the first pole of the fifth transistor T5.

In an exemplary embodiment, the first power line 62 in adjacent two sub-pixels in one pixel row may be an integral structure connected to each other. For example, the first power line 62 of the N-1 th column and the first power line 62 of the nth column are connected to each other, and the first power line 62 of the N +1 th column and the first power line 62 of the N +2 th column are connected to each other. In the exemplary embodiment, the first power lines 62 of the adjacent sub-pixels are connected to each other to form an integrated structure, so that the first power lines 62 of the adjacent sub-pixels can have the same potential, which is beneficial to improving the uniformity of the panel, avoiding the display defects of the display substrate, and ensuring the display effect of the display substrate.

In an exemplary embodiment, the first power line 62 may be a polygonal line of unequal width, which may not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the first power line and the data signal line.

In an exemplary embodiment, an orthographic projection of the first power line 62 on the substrate may at least partially overlap with an orthographic projection of the first connection electrode 51 on the substrate, and an orthographic projection of the first power line 62 on the substrate may at least partially overlap with an orthographic projection of the second connection electrode 52 on the substrate, so that the first power line 62 may serve as a shielding electrode, which may effectively shield an influence of a data voltage jump on a key node in the pixel driving circuit, avoid the data voltage jump from influencing a potential of the key node of the pixel driving circuit, and improve a display effect.

In an exemplary embodiment, the anode connection electrode 63 may have a rectangular shape, the anode connection electrode 63 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the anode connection electrode 63 is configured to be connected to a subsequently formed anode.

(10) A second flat layer pattern is formed. In an exemplary embodiment, forming the second flat layer pattern may include: and coating a second flat film on the substrate with the pattern, patterning the second flat film by using a patterning process to form a second flat layer covering the fourth conductive layer pattern, wherein the second flat layer is provided with a plurality of through holes, as shown in fig. 16.

In an exemplary embodiment, the via hole of each sub-pixel includes at least a thirty-one via hole V31.

In an exemplary embodiment, an orthographic projection of the thirty-first via V31 on the substrate is within a range of an orthographic projection of the anode connection electrode 63 on the substrate, the second planarization layer in the thirty-first via V31 is removed to expose a surface of the anode connection electrode 63, and the thirty-first via V31 is configured to connect a subsequently formed anode to the anode connection electrode 63 through the via.

Thus, the driving circuit layer is prepared and completed on the substrate. The driving circuit layer may include a plurality of sub-pixels in a plane parallel to the display substrate, and each of the sub-pixels may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emission control line, a data signal line, a first power supply line, a first initialization signal line, and a second initialization signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer, which are sequentially disposed on the substrate. The first semiconductor layer includes at least active layers of third to seventh transistors, the first conductive layer includes at least gate electrodes of the third to seventh transistors and a first plate of a storage capacitor, the second conductive layer includes at least gate electrodes of the first to second transistors and a second plate of the storage capacitor, the second semiconductor layer includes at least active layers of the first to second transistors, the third conductive layer includes at least first and second poles of the plurality of transistors, and the fourth conductive layer includes at least a data signal line and a first power supply line.

In an exemplary embodiment, the first, second, third, and fourth conductive layers may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may have a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, and the like. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a Buffer (Buffer) layer for improving water and oxygen resistance of the substrate, the second, third, fourth, and fifth insulating layers may be referred to as a Gate Insulating (GI) layer, and the fifth insulating layer may be referred to as an interlayer Insulating (ILD) layer. The first and second planarization layers may employ an organic material such as resin or the like.

In an exemplary embodiment, the pixel driving circuits in adjacent two sub-pixels in one pixel row may be substantially mirror-symmetrical with respect to a first center line, which is a straight line located between the adjacent two sub-pixels and extending along the second direction Y. For example, the pixel driving circuit of the N-1 th column and the pixel driving circuit of the nth column may be mirror-symmetrical with respect to the first center line. As another example, the pixel driving circuit of the nth column and the pixel driving circuit of the N +1 th column may be mirror-symmetrical with respect to the first center line.

In an exemplary embodiment, the pixel driving circuits in two adjacent sub-pixels may be substantially mirror-symmetrical with respect to the first center line and may include any one or more of: the first semiconductor layers in two adjacent sub-pixels in one pixel row may be mirror-symmetrical with respect to a first center line, the first conductive layers in two adjacent sub-pixels in one pixel row may be mirror-symmetrical with respect to the first center line, the second semiconductor layers in two adjacent sub-pixels in one pixel row may be mirror-symmetrical with respect to the first center line, the third conductive layers in two adjacent sub-pixels in one pixel row may be mirror-symmetrical with respect to the first center line, and the fourth conductive layers in two adjacent sub-pixels in one pixel row may be mirror-symmetrical with respect to the first center line.

In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light emitting structure layer may include the following operations.

(11) An anode conductive layer pattern is formed. In an exemplary embodiment, the forming of the anode conductive layer pattern may include: depositing an anode conductive film on the substrate with the pattern, patterning the anode conductive film by a patterning process to form an anode conductive layer disposed on the second planar layer, where the anode conductive layer at least includes a plurality of anode patterns, as shown in fig. 17a to 17d, fig. 17a is a schematic diagram of one anode conductive layer pattern formed in the embodiment of the disclosure, fig. 17b is a schematic plan view of the anode conductive layer in fig. 17a, fig. 17c is a schematic diagram of another anode conductive layer pattern formed in the embodiment of the disclosure, and fig. 17d is a schematic plan view of the anode conductive layer in fig. 17 c.

In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO, etc.

In an exemplary embodiment, the plurality of anode patterns may include a first anode 90A of a red light emitting device, a second anode 90B of a blue light emitting device, a third anode 90C of a first green light emitting device, and a fourth anode 90D of a second green light emitting device, the first anode 90A may be positioned at a red subpixel emitting red light, the second anode 90B may be positioned at a blue subpixel emitting blue light, the third anode 90C may be positioned at a first green subpixel emitting green light, and the fourth anode 90D may be positioned at a second green subpixel emitting green light.

In an exemplary embodiment, the first and

second anodes

90A and 90B may be sequentially disposed along the second direction Y, the third and

fourth anodes

90C and 90D may be sequentially disposed along the second direction Y, and the third and

fourth anodes

90C and 90D may be disposed at one side of the first direction X of the first and

second anodes

90A and 90B. Alternatively, the first anode 90A and the second anode 90B may be sequentially disposed along the first direction X, the third anode 90C and the fourth anode 90D may be sequentially disposed along the first direction X, and the third anode 90C and the fourth anode 90D may be disposed at one side of the first anode 90A and the second anode 90B in the second direction Y.

In an exemplary embodiment, the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may be respectively connected to the anode connection electrode 63 of the sub-pixel through the thirty-one via hole V31, and the anode shapes and areas of the four sub-pixels in one pixel unit may be the same or may be different.

In an exemplary embodiment, a plurality of anodes provided for a display area, each having an edge near one side of a binding area, the edge of the most near binding area among the plurality of anodes being referred to as an anode boundary 90-1, a display area boundary BD of an exemplary embodiment of the present disclosure is a straight line passing through the anode boundary 90-1 and extending in a first direction X.

In an exemplary embodiment, at least one of the first, second, third and

fourth anodes

90A, 90B, 90C and 90D may include an anode body part and an anode connection part connected to each other, and the anode connection part is connected to the anode connection electrode 63 through the thirty-first via hole V31.

In an exemplary embodiment, the first anode 90A may include a first anode body portion and a first anode connection portion connected to each other, the first anode body portion may have a rectangular shape, corners of the rectangular shape may be provided with rounded chamfers, the first anode connection portion may have a strip shape extending along the second direction Y, and the first anode connection portion may be connected to the anode connection electrode 63 through the thirty-one via hole V31.

In an exemplary embodiment, the second anode 90B may include a second anode body portion and a second anode connection portion connected to each other, the second anode body portion may have a rectangular shape, corners of the rectangular shape may be provided with rounded chamfers, the second anode connection portion may have a strip shape extending along the second direction Y, and the second anode connection portion may be connected to the anode connection electrode 63 through the thirty-one via hole V31.

In an exemplary embodiment, the third anode 90C may include a third anode body portion and a third anode connection portion connected to each other, the third anode body portion may have a rectangular shape, corners of the rectangular shape may be provided with rounded chamfers, the third anode connection portion may have a strip shape extending along the first direction X, and the third anode connection portion may be connected to the anode connection electrode 63 through a thirty-one via V31.

In an exemplary embodiment, the fourth anode 90D may include a fourth anode body portion and a fourth anode connection portion connected to each other, the fourth anode body portion may have a rectangular shape, corners of the rectangular shape may be provided with rounded chamfers, the fourth anode connection portion may have a strip shape extending along the first direction X, and the fourth anode connection portion may be connected to the anode connection electrode 63 through the thirty-one via V31.

In an exemplary embodiment, the subsequent preparation process may include: form pixel definition layer pattern earlier, then adopt coating by vaporization or ink jet printing technology to form organic luminescent layer, then form the negative pole on organic luminescent layer, then form the packaging structure layer, the packaging structure layer can be including the first encapsulated layer of establishing of folding, second encapsulated layer and third encapsulated layer, first encapsulated layer and third encapsulated layer can adopt inorganic material, the second encapsulated layer can adopt organic material, the second encapsulated layer sets up between first encapsulated layer and third encapsulated layer, can guarantee that external steam can't get into the luminescent structure layer.

(12) Forming a pixel defining layer pattern. In an exemplary embodiment, forming the pixel defining layer pattern may include: a pixel defining film is coated on the substrate on which the pattern is formed, the pixel defining film is patterned by a patterning process to form a pixel defining layer covering the anode conductive layer pattern, a plurality of pixel openings 400 are formed in the pixel defining layer, the pixel defining film in the pixel openings 400 is removed to expose the surface of the anode 90, as shown in fig. 18a and 18b, fig. 18a is a schematic diagram after one pixel defining layer pattern is formed according to an embodiment of the present disclosure, and fig. 17b is a schematic diagram after another pixel defining layer pattern is formed according to an embodiment of the present disclosure.

In one possible exemplary embodiment, the plurality of pixel openings provided for the display area, each having an edge near one side of the binding area, an edge of the plurality of pixel openings closest to the binding area being referred to as a pixel opening boundary, and the display area boundary BD of the exemplary embodiment of the present disclosure may be a straight line passing through the pixel opening boundary and extending along the first direction X.

Fig. 19 is a schematic plan view of a conventional display substrate, which is a pixel driving circuit structure of the M-1 th pixel row and the M-th pixel row in the display region near the binding region. As shown in fig. 19. The layout of the pixel driving circuit in the existing display substrate is as follows: the first transistor T1, the second transistor T2 and the fourth transistor T4 are located on the side of the third transistor T3 of the sub-pixel away from the display area boundary BD, and the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are located on the side of the third transistor T3 of the sub-pixel close to the display area boundary BD. According to the characteristic of the layout, in order to realize the sharing of the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 of the sub-pixels in the ith pixel row, the seventh transistor T7 in the sub-pixels in the ith pixel row is designed to be driven by the first scanning signal line 21 in the sub-pixels in the (i + 1) th pixel row (next row), i =1,2, \8230;, M. Due to such a driving feature, the pixel driving circuit of the sub-pixels of the mth pixel row (last row) needs to additionally provide the first scanning signal line 21 of the next row for driving the seventh transistor T7 and the second initial signal line 57 of the next row for supplying the second initial signal, and the additionally provided first scanning signal line 21 and second initial signal line 57 can be provided only outside the display area, that is, the additionally provided signal lines such as the first scanning signal line 21 and second initial signal line 57 are located on the side of the boundary BD of the display area near the binding area. Since the pixel driving circuit boundary PD formed by the additionally arranged first scanning signal line 21 and the second initial signal line 57 exceeds the display area boundary BD, the binding area can be correspondingly arranged only with reference to the pixel driving circuit boundary PD, thereby increasing the width of the lower frame. In an exemplary embodiment, the excess distance B between the display area boundary BD and the pixel driving circuit boundary PD is about 20 μm to 30 μm, and the larger the excess distance B, the larger the lower frame.

In the exemplary embodiment, although the position of the pixel driving circuit boundary may be adjusted by moving the pixel driving circuit upward as a whole to overlap the display area boundary BD with the pixel driving circuit boundary PD, in order to achieve the connection of the anode with the pixel driving circuit, such a processing scheme requires changing the position of the anode connection electrode such that the distance between the anode openings is reduced, which not only increases signal crosstalk, but also causes short defects. In addition, the scheme of moving the pixel driving circuit upwards as a whole can move the pixel opening of the pixel defining layer upwards as a whole, so that the distance between the metal mask (FMM) and the display area boundary is reduced, and under the existing process conditions, the display area is dark due to Shadow (Shadow) in the evaporation process, so that a greater risk of poor display exists.

As can be seen from the structure and the manufacturing process of the display substrate disclosed by the present disclosure, the display substrate provided by the exemplary embodiment of the present disclosure can effectively reduce the width of the lower frame by changing the layout of the pixel driving circuit. The present disclosure makes it possible to drive the seventh transistor T7 of the sub-pixels in the ith pixel row (this row) by the first scanning signal line 21 of the sub-pixels in the ith pixel row (this row) without additionally providing the pixel driving circuit of not only the sub-pixels in the mth pixel row (last row) but also the sub-pixels in the display area boundary PD region by locating the first scanning signal line 21, the second scanning signal line 32, the fourth scanning signal line 33, the first initialization signal line 31, and the second initialization signal line 57 of the sub-pixels in the storage capacitor 40 of this sub-pixel on the side close to the display area boundary BD, the emission control line 22 on the side of the storage capacitor 40 of this sub-pixel away from the display area boundary BD, the first transistor T1, the second transistor T2, and the fourth transistor T4 on the side of the third transistor T3 of this sub-pixel close to the display area boundary BD, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 on the side of the third transistor T3 of this sub-pixel away from the display area boundary BD, so that the seventh transistor T7 of the sub-pixels in the ith pixel row (this row) is driven by the first scanning signal line 21 of the sub-pixels in the ith pixel row (last row), and thus the sub-pixels in the mth pixel row (last row) can be located on the side away from the display area boundary PD. According to the driving circuit layout, the binding region can be set correspondingly not only according to the boundary BD of the display region as a reference, but also according to the boundary PD of the pixel driving circuit, so that the width of the lower frame is effectively reduced. In an exemplary embodiment, the distance L between the display area boundary BD and the pixel driving circuit boundary PD may be about 6 μm to 10 μm. For example, the distance L may be about 7.99 μm or so. Compared with the pixel driving circuit boundary PD beyond the display area boundary BD in the prior art, which is about 20 μm to about 30 μm, the display substrate according to the exemplary embodiment of the present disclosure may reduce the width of the lower bezel by about 30 μm to about 40 μm, which is advantageous for realizing a narrow bezel. In addition, the pixel driving circuit layout provided by the exemplary embodiment of the disclosure not only ensures the safe distance between the anode openings and the safe distance between the metal mask plate and the display area boundary, avoids short circuit defects and bad display risks in the evaporation process, but also can effectively save the layout space, and is beneficial to realizing high resolution. The preparation process disclosed by the invention can be well compatible with the existing preparation process, and is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.

The foregoing structure and the preparation process thereof in the present disclosure are merely exemplary illustrations, and in an exemplary embodiment, the corresponding structure may be changed and patterning processes may be added or reduced according to actual needs, and the present disclosure is not limited herein.

In an exemplary embodiment, the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, and the like, and the disclosure is not limited herein.

The present disclosure also provides a method for manufacturing a display substrate to manufacture the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a display area and a binding area at one side of the display area, the display area includes M pixel rows, M being a positive integer greater than 1; at least one pixel row comprises a scanning signal line and a plurality of sub-pixels which are sequentially arranged along the extending direction of the scanning signal line, at least one sub-pixel comprises a pixel driving circuit which is connected with the scanning signal line, the pixel driving circuit at least comprises a storage capacitor and a plurality of transistors, the plurality of transistors at least comprise a first transistor which is used as a first initialization transistor, the scanning signal line at least comprises a second scanning signal line, and the second scanning signal line is configured to control the first transistor to be switched on or switched off; the preparation method comprises the following steps:

The present disclosure also provides a display device, which includes the display substrate. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator, etc., but the embodiment of the present invention is not limited thereto.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims

1. A display substrate comprises a display area and a binding area positioned on one side of the display area, wherein the display area comprises M pixel rows which are sequentially arranged, and M is a positive integer greater than 1; at least one pixel row comprises a scanning signal line and a plurality of sub-pixels which are sequentially arranged along the extending direction of the scanning signal line, at least one sub-pixel comprises a pixel driving circuit which is connected with the scanning signal line, the pixel driving circuit at least comprises a storage capacitor and a plurality of transistors, the plurality of transistors at least comprise a first transistor which is used as a first initialization transistor, the scanning signal line at least comprises a second scanning signal line, and the second scanning signal line is configured to control the first transistor to be switched on or switched off; in at least one pixel row, the second scanning signal line is arranged on one side of the storage capacitor close to a display area boundary, and the display area boundary is the edge of the display area close to one side of the binding area.

2. The display substrate according to claim 1, wherein a first electrode of the first transistor is connected to a first initialization signal line provided on a side of the storage capacitor near a boundary of the display area.

3. The display substrate of claim 2, wherein an edge of the first initial signal line in the mth pixel row near a side of the binding region forms a pixel driving circuit boundary.

4. The display substrate of claim 3, wherein the pixel drive circuit boundary is on a side of the display area boundary away from the binding region.

5. The display substrate according to any one of claims 1 to 4, wherein the plurality of transistors further includes a seventh transistor which is a second initialization transistor, the scanning signal line further includes a first scanning signal line configured to control the seventh transistor to be turned on or off, the first scanning signal line being provided on a side of the storage capacitor away from a boundary of the display region.

6. The display substrate according to claim 5, wherein a first electrode of the seventh transistor is connected to a second initial signal line provided on a side of the storage capacitor away from the display area boundary.

7. The display substrate of claim 6, wherein an orthographic projection of the second initial signal line on the display substrate in an ith pixel row at least partially overlaps an orthographic projection of the second scanning signal line on the display substrate in an ith-1 pixel row, i =2,3, \ 8230; \8230;, M.

8. The display substrate according to claim 5, wherein the plurality of transistors further includes a second transistor which is a compensation transistor and a fourth transistor which is a data writing transistor, the scanning signal line further includes a third scanning signal line which controls the fourth transistor to be turned on or off and a fourth scanning signal line which controls the compensation transistor to be turned on or off, and the third scanning signal line and the fourth scanning signal line are provided on a side of the storage capacitor near a boundary of the display region.

9. The display substrate of claim 5, wherein the first scan signal line in the ith pixel row and the third scan signal line in the (i-1) th pixel row are in an integral structure, i =2,3, \8230;, M.

10. The display substrate according to claim 1, wherein the plurality of transistors further comprises a fifth transistor and a sixth transistor, the display region further comprises an emission control line configured to control the fifth transistor and the sixth transistor to be turned on or off, and the emission control line is provided on a side of the storage capacitor away from a boundary of the display region.

11. The display substrate according to claim 1, wherein the plurality of transistors further comprises a second transistor which is a compensation transistor, a third transistor which is a driving transistor, a fourth transistor which is a data writing transistor, fifth and sixth transistors which are light emitting transistors, and a seventh transistor which is a second initialization transistor; the first transistor, the second transistor, and the fourth transistor are provided on a side of the third transistor close to the boundary of the display area, and the fifth transistor, the sixth transistor, and the seventh transistor are provided on a side of the third transistor away from the boundary of the display area.

12. The display substrate according to claim 11, wherein the first transistor and the second transistor are oxide transistors, and the third transistor to the seventh transistor are low-temperature polysilicon transistors.

13. The display substrate according to claim 11, wherein the scan signal line includes a first scan signal line which controls the seventh transistor to be turned on or off, a second scan signal line which controls the first transistor to be turned on or off, a third scan signal line which controls the fourth transistor to be turned on or off, and a fourth scan signal line which controls the second transistor to be turned on or off; in at least one pixel row, the first scanning signal line, the fourth scanning signal line, the third scanning signal line, and the second scanning signal line are sequentially arranged along a direction close to a boundary of the display region.

14. The display substrate according to claim 13, wherein the display region further comprises a light emission control line which controls the fifth transistor and the sixth transistor to be turned on or off; in at least one pixel row, the first scanning signal line, the light emission control line, the fourth scanning signal line, the third scanning signal line, and the second scanning signal line are sequentially arranged along a direction close to a boundary of the display region.

15. The display substrate according to claim 14, wherein the display region further comprises a first initial signal line connected to a first pole of the first transistor; in at least one pixel row, along a direction close to a boundary of the display region, the first scanning signal line, the light emission control line, the fourth scanning signal line, the third scanning signal line, the second scanning signal line, and the first initial signal line are sequentially arranged.

16. The display substrate according to claim 11, wherein in at least one pixel row, the plurality of pixel driving circuits are respectively connected to the plurality of anode patterns, and a minimum distance between at least one anode pattern and the display area boundary is smaller than a minimum distance between a seventh transistor in the pixel driving circuit to which the anode pattern is connected and the display area boundary.

17. The display substrate of claim 16, wherein the plurality of anode patterns connected to the plurality of pixel driving circuits in the same pixel row include a first anode, a second anode, a third anode, and a fourth anode, and a minimum distance between the first anode or the second anode and the display area boundary is smaller than a minimum distance between the third anode and the display area boundary.

18. The display substrate according to claim 17, wherein the mth pixel row further comprises a first initial signal line connected to the first electrode of the first transistor, and wherein in the plurality of anode patterns connected to the plurality of pixel driving circuits in the mth pixel row, an orthographic projection of the first anode or the second anode on the display substrate at least partially overlaps an orthographic projection of the first initial signal line on the display substrate, and an orthographic projection of the third anode or the fourth anode on the display substrate does not overlap an orthographic projection of the first initial signal line on the display substrate.

19. The display substrate according to claim 17, wherein a second initial signal line connected to the first electrode of the seventh transistor is further included in the M-th pixel row, and in the plurality of anode patterns connected to the plurality of pixel driving circuits in the M-th pixel row, an orthogonal projection of the first anode or the second anode on the display substrate does not overlap an orthogonal projection of the second initial signal line on the display substrate, and an orthogonal projection of the third anode or the fourth anode on the display substrate does not overlap an orthogonal projection of the second initial signal line on the display substrate.

20. The display substrate according to claim 1, wherein the display substrate comprises a driving circuit layer disposed on a base and a light emitting structure layer disposed on a side of the driving circuit layer away from the base in a plane perpendicular to the display substrate; the driving circuit layer comprises a first semiconductor layer, a first conducting layer, a second semiconductor layer and a third conducting layer which are arranged along the direction far away from the substrate; the first semiconductor layer at least comprises an active layer of a plurality of polysilicon transistors, the first conducting layer at least comprises a first scanning signal line, a third scanning signal line, gate electrodes of the polysilicon transistors and a first polar plate of a storage capacitor, the second conducting layer at least comprises a second scanning signal line, a fourth scanning signal line, a first initial signal line, gate electrodes of the oxide transistors and a second polar plate of the storage capacitor, the second semiconductor layer at least comprises an active layer of the oxide transistors, and the third conducting layer at least comprises a second initial signal line.

21. A display device comprising the display substrate of any one of claims 1 to 20.

22. A preparation method of a display substrate comprises a display area and a binding area positioned on one side of the display area, wherein the display area comprises M pixel rows, and M is a positive integer greater than 1; at least one pixel row comprises a scanning signal line and a plurality of sub-pixels which are sequentially arranged along the extending direction of the scanning signal line, at least one sub-pixel comprises a pixel driving circuit which is connected with the scanning signal line, the pixel driving circuit at least comprises a storage capacitor and a plurality of transistors, the plurality of transistors at least comprise a first transistor which is used as a first initialization transistor, the scanning signal line at least comprises a second scanning signal line, and the second scanning signal line is configured to control the first transistor to be switched on or switched off; the preparation method comprises the following steps: