CN221081299U - Anti-interference circuit suitable for multipath parallel receiver - Google Patents
Anti-interference circuit suitable for multipath parallel receiver Download PDFInfo
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- CN221081299U CN221081299U CN202322878389.7U CN202322878389U CN221081299U CN 221081299 U CN221081299 U CN 221081299U CN 202322878389 U CN202322878389 U CN 202322878389U CN 221081299 U CN221081299 U CN 221081299U
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Abstract
The utility model discloses an anti-interference circuit suitable for a multipath parallel receiver, which comprises a first branch circuit and a second branch circuit; the first branch circuit comprises a power divider, a combiner and a coupler which are sequentially connected; the second branch comprises a first analog-to-digital conversion module, a transverse filter and a digital-to-analog converter; the input end of the analog-to-digital conversion module is connected with the output end of the power divider, and the output end of the digital-to-analog converter is connected with the input end of the combiner. The method provided by the utility model can be used for inhibiting the high-power interference signal in the original received signal, combining the high-power signal with the low-power signal after the amplitude of the high-power signal is reduced, and avoiding entering a saturated state during signal acquisition.
Description
Technical Field
The utility model relates to the technical field of multipath parallel receiving equipment, in particular to an anti-interference circuit suitable for a multipath parallel receiver.
Background
In order to greatly improve the system data transmission capability and the system bandwidth under large-scale application, the conventional communication equipment is changing the thinking mode of half duplex, single-shot receiving and single-shot receiving of the traditional equipment and simply depending on bandwidth expansion and speed improvement, and research on technologies such as broadband radio frequency front end, large dynamic range signal processing, full-band digital direct sampling, efficient multipath signal processing and the like is gradually developed. Multipath parallel reception, while capable of improving system performance, is facing increasingly complex electromagnetic environments and has higher requirements on the dynamic range and anti-interference capability of the receiver.
Since the receiver needs to receive multiple size signals at the same time and the frequencies of the size signals are discretely distributed in a wider working frequency band, the receiver needs to have the capability of covering a wide frequency band and an ultra-high instantaneous receiving dynamic range, however, the existing receiver also has the following problems:
The traditional receiver carries out the form of same attenuation and same amplification on a plurality of received signals simultaneously, so that the signal can enter a saturated state in advance when the signal is acquired in the later stage, and signal loss is caused.
For this reason, it is desirable to provide an anti-interference circuit suitable for a multipath parallel receiver. Providing high anti-interference capability for new generation communication devices.
Disclosure of utility model
Therefore, the utility model aims to provide an anti-interference circuit suitable for a multipath parallel receiver, which is used for inhibiting a high-power interference signal in an original received signal, reducing the amplitude of the high-power signal, combining the high-power signal with a low-power signal, and then passing through the low-power signal, so as to avoid entering a saturated state during signal acquisition.
In order to achieve the above object, an anti-interference circuit suitable for a multipath parallel receiver of the present utility model includes a first branch and a second branch; the first branch circuit comprises a power divider, a combiner and a coupler which are sequentially connected; the second branch comprises a first analog-to-digital conversion module, a transverse filter and a digital-to-analog converter which are sequentially connected; the input end of the analog-to-digital conversion module is connected with the output end of the power divider, and the output end of the digital-to-analog converter is connected with the input end of the combiner.
Further preferably, the device further comprises a second analog-to-digital conversion module, wherein one end of the second analog-to-digital conversion module is connected with the coupler, and the other end of the second analog-to-digital conversion module is connected with the transverse filter.
Further preferably, the output end of the coupler is connected with the input end of the sampling module, and the output end of the sampling module is connected with the input end of the main control module.
Further preferably, the sampling module is a sampling chip with a model CX8242 KA.
Further preferably, the main control module adopts an FPGA chip, and the model of the FPGA chip is XC7K325T.
The application discloses an anti-interference circuit suitable for a multipath parallel receiver, wherein one path of signals is sent to a main receiving channel after passing through a power divider, the other path of signals is sent to a transverse filter after being sampled and quantized by an ADC (analog-to-digital converter), the digital signals are converted into analog signals by a DAC (digital-to-analog converter) and then are combined with the signals of the main receiving channel in a combiner, the transverse filter inhibits high-power interference signals in original received signals, and the signals enter a saturated state when the signals are prevented from being acquired after the amplitudes of the high-power signals are reduced and are combined with low-power signals.
Drawings
Fig. 1 is a schematic diagram of an anti-interference circuit suitable for a multipath parallel receiver according to the present utility model.
In the figure:
1. a power divider; 2. a combiner; 3. a coupler; 4. a first analog-to-digital conversion module; 5. a transversal filter; 6. a digital-to-analog converter; 7. and a second analog-to-digital conversion module.
Detailed Description
The utility model is described in further detail below with reference to the drawings and the detailed description.
As shown in fig. 1, an anti-interference circuit suitable for a multipath parallel receiver according to an embodiment of the present utility model includes a first branch and a second branch; the first branch circuit comprises a power divider 1, a combiner 2 and a coupler 3 which are connected in sequence; the second branch comprises a first analog-to-digital conversion module 4, a transverse filter 5 and a digital-to-analog converter 6; the input end of the analog-to-digital conversion module is connected with the output end of the power divider 1, and the output end of the digital-to-analog converter is connected with the input end of the combiner 2.
The device also comprises a second analog-to-digital conversion module 7, wherein one end of the second analog-to-digital conversion module 7 is connected with the coupler 3, and the other end of the second analog-to-digital conversion module is connected with the transverse filter 5.
The output end of the coupler 3 is connected with the input end of the sampling module, and the output end of the sampling module is connected with the input end of the main control module.
The sampling module selects a sampling chip with the model CX8242 KA. The main control module adopts an FPGA chip.
The application discloses an anti-interference circuit suitable for a multipath parallel receiver, which is characterized in that after signals are received by an antenna, the signals pass through a power divider, small signals are sent into a main receiving channel, high-power interference signals are sampled and quantized by another path of ADC and then sent into a transverse filter, the transverse filter generates digital signals consistent with the main receiving channel, the digital signals are converted into analog signals by a DAC and then are combined with the signals of the main receiving channel in a combiner, the transverse filter suppresses the high-power interference signals in the original receiving signals, and after the amplitude of the high-power interference signals is reduced, the high-power interference signals are combined with the small-power signals, and the signals are prevented from entering a saturated state when being acquired. And the data are input into the FPGA after being sampled by a sampling module.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present utility model.
Claims (5)
1. An anti-interference circuit suitable for a multipath parallel receiver, characterized in that: comprises a first branch and a second branch; the first branch circuit comprises a power divider, a combiner and a coupler which are sequentially connected; the second branch comprises a first analog-to-digital conversion module, a transverse filter and a digital-to-analog converter which are sequentially connected; the input end of the first analog-to-digital conversion module is connected with the output end of the power divider, and the output end of the digital-to-analog converter is connected with the input end of the combiner.
2. The anti-interference circuit for a multipath parallel receiver of claim 1 further comprising a second analog to digital conversion module, wherein one end of the second analog to digital conversion module is connected to the coupler and the other end is connected to the transversal filter.
3. The anti-interference circuit for a multipath parallel receiver of claim 1, wherein the output end of the coupler is connected with the input end of a sampling module, and the output end of the sampling module is connected with the input end of a main control module.
4. An anti-interference circuit for a multipath parallel receiver according to claim 3, wherein the sampling module is a sampling chip with model CX8242 KA.
5. The anti-interference circuit for a multipath parallel receiver of claim 3 wherein the master control module employs an FPGA chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322878389.7U CN221081299U (en) | 2023-10-26 | 2023-10-26 | Anti-interference circuit suitable for multipath parallel receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322878389.7U CN221081299U (en) | 2023-10-26 | 2023-10-26 | Anti-interference circuit suitable for multipath parallel receiver |
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| Publication Number | Publication Date |
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| CN221081299U true CN221081299U (en) | 2024-06-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202322878389.7U Active CN221081299U (en) | 2023-10-26 | 2023-10-26 | Anti-interference circuit suitable for multipath parallel receiver |
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| CN (1) | CN221081299U (en) |
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2023
- 2023-10-26 CN CN202322878389.7U patent/CN221081299U/en active Active
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