CN221056845U - Circuit capable of automatically entering debugging mode, whole vehicle controller and vehicle - Google Patents
Circuit capable of automatically entering debugging mode, whole vehicle controller and vehicle Download PDFInfo
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- CN221056845U CN221056845U CN202322607517.4U CN202322607517U CN221056845U CN 221056845 U CN221056845 U CN 221056845U CN 202322607517 U CN202322607517 U CN 202322607517U CN 221056845 U CN221056845 U CN 221056845U
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Abstract
The utility model provides a circuit capable of automatically entering a debugging mode, a whole vehicle controller and a vehicle, wherein the circuit capable of automatically entering the debugging mode comprises a work awakening circuit and a debugging mode awakening circuit which are connected in parallel between a power supply module and a module to be debugged; the work wake-up circuit can output a work wake-up signal to a work wake-up port of the module to be debugged after receiving the output of the power supply module so as to enable the module to be debugged to enter a work state; the input end of the debugging mode wake-up circuit is connected with the power module, the output end of the debugging mode wake-up circuit is connected with the debugging mode wake-up port of the module to be debugged, and the debugging mode wake-up circuit can output the debugging mode wake-up signal to the debugging mode wake-up port after receiving the output of the power module and at a time later than the time when the work wake-up port receives the work wake-up signal, so that the module to be debugged enters a debugging mode. The circuit capable of automatically entering the Debug mode can realize that the chip automatically enters the Debug mode.
Description
Technical Field
The utility model relates to the technical field of controller debugging, in particular to a circuit capable of automatically entering a debugging mode, and simultaneously relates to a whole vehicle controller provided with the circuit capable of automatically entering the debugging mode and a vehicle provided with the whole vehicle controller.
Background
The SBC chip (System Basis Chip; system base chip) in the BMS system has two states, one is Normal mode (standard driving mode) and the other is Debug mode (Debug mode), in most cases, normal mode is used when the battery pack is off line, and Debug mode is needed in the development and Debug process.
At present, the method for entering the Debug mode by the SBC chip is complex, the Debug mode is needed to be entered by a manual short circuit mode after the power-on, the power-on sequence of each signal is needed to be kept in mind by a worker, and the state of each signal is manually switched, so that the production and the test efficiency are affected, and the failure of entering the Debug mode and even the chip damage are easily caused by manual reasons.
Disclosure of utility model
In view of the above, the present utility model is directed to a circuit for automatically entering Debug mode, so as to enable a chip to automatically enter Debug mode.
In order to achieve the above purpose, the technical scheme of the utility model is realized as follows:
A circuit capable of automatically entering a debugging mode comprises a work wake-up circuit and a debugging mode wake-up circuit which are connected in parallel between a power module and a module to be debugged;
The work wake-up circuit can output a work wake-up signal to a work wake-up port of the module to be debugged after receiving the output of the power supply module so as to enable the module to be debugged to enter a working state;
The input end of the debugging mode wake-up circuit is connected with the power module, the output end of the debugging mode wake-up circuit is connected with the debugging mode wake-up port of the module to be debugged, and the debugging mode wake-up circuit can output the debugging mode wake-up signal to the debugging mode wake-up port after receiving the output of the power module and at a time later than the time when the work wake-up port receives the work wake-up signal, so that the module to be debugged enters a debugging mode.
Further, the debug mode wake-up circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor and a PNP triode; the first end of the first resistor is respectively connected with the power supply module and the input end of the work awakening circuit; the second end of the first resistor is connected with the first end of the second resistor and the emitter of the PNP triode respectively; the second end of the second resistor is respectively connected with the first end of the fourth resistor and the first end of the first capacitor; the second end of the fourth resistor is connected with the base electrode of the PNP triode; the collector electrode of the PNP triode is respectively connected with the first end of the third resistor and the debug mode wake-up port; the second end of the first capacitor is connected with the second end of the third resistor and grounded.
Further, the debug mode wake-up circuit comprises a zener diode; the first end of the zener diode is respectively connected with the second end of the first resistor, the first end of the second resistor and the emitter of the PNP triode; the second end of the zener diode is respectively connected with the second end of the first capacitor and the second end of the third resistor, and is grounded.
Further, the work wake-up circuit comprises a filtering circuit, and the filtering circuit is used for filtering the output current of the power supply module.
Further, the filter circuit comprises a fifth resistor, a second capacitor and a third capacitor; the first end of the fifth resistor is connected with the power supply module, and the second end of the fifth resistor is connected with the work awakening port; the first end of the second capacitor is connected between the first end of the fifth resistor and the power module, and the second end of the second capacitor is connected with the second end of the third capacitor and grounded; the first end of the third capacitor is connected between the second end of the fifth resistor and the work wakeup port.
Further, the power module adopts a 12V power supply, and/or the module to be debugged adopts an SBC chip.
Compared with the prior art, the utility model has the following advantages:
The circuit capable of automatically entering the debugging mode can wake up the working state of the module to be debugged through the working wake-up circuit, and wake up the debugging mode through the debugging mode wake-up circuit at a time later than the time of receiving the working wake-up signal by the working wake-up port, namely, wake up the debugging mode in the working state, so that the module to be debugged enters the debugging mode, and therefore the chip can automatically enter the Debug mode, the problem of chip damage caused by manual operation is avoided, and the debugging efficiency is improved.
In addition, the Debug mode wake-up circuit mainly comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor and a PNP triode, and the high level output from the collector of the PNP triode to the Debug mode wake-up port can be changed into the low level, so that the condition of entering the Debug mode is triggered, the module to be debugged automatically enters the Debug mode, and meanwhile, the Debug mode wake-up circuit is simple in structure, easy to manufacture and low in cost.
In addition, the voltage stabilizing diode is beneficial to stabilizing the circuit voltage, protecting each electronic component in the circuit and preventing the electronic component from being broken down by high current. By arranging the filter circuit, abnormal signals can be filtered, and the work awakening port is ensured to receive stable work awakening signals. The filter circuit mainly comprises a fifth resistor, a second capacitor and a third capacitor, has a simple structure and is beneficial to arrangement and control of cost.
Meanwhile, another object of the present utility model is to provide a vehicle controller, which includes a module to be debugged, and a circuit for automatically entering a debug mode as described above, where the circuit is configured to enable the module to be debugged to automatically enter the debug mode.
Another object of the present utility model is to provide a vehicle having the vehicle control unit.
Compared with the prior art, the whole vehicle controller and the vehicle and the circuit for automatically entering the debugging mode have the same beneficial effects, and are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model. In the drawings:
FIG. 1 is a schematic diagram of a circuit for automatically entering debug mode according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of a circuit for automatically entering debug mode according to an embodiment of the present utility model;
Reference numerals illustrate:
10. A power module; 20. a module to be debugged; 30. a work wake-up circuit; 40. debug mode wake-up circuitry.
Detailed Description
It should be noted that, without conflict, the embodiments of the present utility model and features of the embodiments may be combined with each other.
In the description of the present utility model, it should be noted that, if terms indicating an orientation or positional relationship such as "upper", "lower", "inner", "outer", etc. are presented, they are based on the orientation or positional relationship shown in the drawings, only for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, if any, are also used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, in the description of the present utility model, the terms "mounted," "connected," and "connected," are to be construed broadly, unless otherwise specifically defined. For example, the connection can be fixed connection, detachable connection or integrated connection; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art in combination with specific cases.
The utility model will be described in detail below with reference to the drawings in connection with embodiments.
Example 1
The embodiment relates to a circuit capable of automatically entering a Debug mode, which can automatically enter a Debug mode by a chip, so that the problem of chip damage caused by manual operation is avoided.
In the overall design, as shown in fig. 1, the circuit for automatically entering the debug mode in this embodiment includes a work wake-up circuit 30 and a debug mode wake-up circuit 40 connected in parallel between the power module 10 and the module to be debugged 20.
The input end of the work wake-up circuit 30 is connected to the power module 10, the output end of the work wake-up circuit 30 is connected to the work wake-up port of the module to be debugged 20, and the work wake-up circuit 30 can output a work wake-up signal to the work wake-up port after receiving the output of the power module 10, so that the module to be debugged 20 enters a working state.
The input end of the debug mode wake-up circuit 40 is connected with the power module 10, the output end of the debug mode wake-up circuit 40 is connected with the debug mode wake-up port of the module to be debugged 20, and the debug mode wake-up circuit 40 can output the debug mode wake-up signal to the debug mode wake-up port at a time later than the time when the work wake-up port receives the work wake-up signal after receiving the output of the power module 10, so that the module to be debugged 20 enters the debug mode.
Based on the design concept described above, in this embodiment, as a preferred implementation manner, the power module 10 uses a 12V power supply, and the module to be debugged 20 uses an SBC chip.
Specifically, as shown in fig. 2, as an exemplary structure, the debug mode wake-up circuit 40 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, and a PNP transistor.
The first end of the first resistor R1 is connected to the input ends of the power module 10 and the operation wake-up circuit 30, respectively. The second end of the first resistor R1 is respectively connected with the first end of the second resistor R2 and the emitter of the PNP triode. The second end of the second resistor R2 is connected to the first end of the fourth resistor R4 and the first end of the first capacitor C1, respectively. The second end of the fourth resistor R4 is connected with the base electrode of the PNP triode. The collector of the PNP triode is respectively connected with the first end of the third resistor R3 and the debug mode wake-up port. The second end of the first capacitor C1 is connected to the second end of the third resistor R3 and to ground.
The advantage of this arrangement is mainly that the condition of entering the Debug mode can be triggered by changing the high level output from the collector of the PNP transistor to the Debug mode wake-up port to the low level, so that the module to be debugged 20 automatically enters the Debug mode, and meanwhile, the structure is simple, the circuit manufacturing is easy, and the cost is reduced.
Furthermore, in the present embodiment, the debug mode wake-up circuit 40 includes a zener diode as a preferred implementation form based on the consideration of circuit stability.
The first end of the zener diode is connected with the second end of the first resistor R1, the first end of the second resistor R2 and the emitter of the PNP triode respectively. The second end of the zener diode is respectively connected with the second end of the first capacitor C1 and the second end of the third resistor R3, and is grounded.
It can be understood that the arrangement of the zener diode is beneficial to stabilizing the circuit voltage, and protecting each electronic component in the circuit from being broken down by high current.
Further, as an exemplary structure, the operation wakeup circuit 30 includes a filter circuit for performing a filter process on the output current of the power supply module 10. That is, by providing the filter circuit, the abnormal signal can be filtered out, so that the work wake-up port is ensured to receive a stable work wake-up signal (here, a high level signal).
In addition, as a preferred implementation manner, the operation wake-up circuit 30 of the present embodiment includes the fifth resistor R5, the second capacitor C2 and the third capacitor C3 in a specific design.
The first end of the fifth resistor R5 is connected to the power module 10, and the second end is connected to the work wake-up port. The first end of the second capacitor C2 is connected between the first end of the fifth resistor R5 and the power module 10, and the second end is connected to the second end of the third capacitor C3 and grounded. The first end of the third capacitor C3 is connected between the second end of the fifth resistor R5 and the duty wake-up port.
It can be understood that the filter circuit is formed by adopting one resistor and two capacitors, so that the structure is simple and the arrangement and control of the cost are facilitated on the premise of realizing a good filter effect.
In use, the circuit for automatically entering Debug mode of the present embodiment, as shown in fig. 1 and 2, is to enter Debug mode if the WAKE1 (active WAKE port) in fig. 2 receives a high level (active WAKE signal), and the voltage at DBG (Debug mode WAKE port) has a pull-down pulse change from high level to low level (Debug mode WAKE signal).
Specifically, after the power module 10 is powered on, the WAKE input (12 v voltage) is input to the circuit, and the PNP transistor is initially turned on (the emitter E is turned on to the collector C), and at this time, the DBG receives a high level, and at the same time, the 12v voltage charges the first capacitor C1 through the first resistor R1 and the second resistor R2, and after the first capacitor C1 is charged, the voltage at the end of the fourth resistor R4 changes, so that the PNP junction becomes non-conductive (the emitter E is turned off to the collector C, and the collector C is turned on to the base B), so that the voltage at the DBG becomes low level due to the grounding through the third resistor R3, thereby realizing the high-low level change at the DBG, meeting the condition that the system enters the debuge mode, and automatically entering the debuge mode.
It should be mentioned that, in this embodiment, the charging time of the first capacitor C1 may be flexibly controlled by adjusting the sizes of the first resistor R1, the second resistor R2 and the first capacitor C1, so as to further realize the adjustment of the time of the high-low level change at the DBG, that is, the adjustment of the time of automatically entering the Debug mode.
According to the circuit capable of automatically entering the Debug mode, the work state of the module to be debugged 20 can be awakened by the work awakening circuit 30, and the Debug mode can be awakened by the Debug mode awakening circuit 40 at a time later than the time when the work awakening port receives the work awakening signal, namely, the Debug mode is awakened in the work state, so that the module to be debugged 20 enters the Debug mode, and therefore the chip can automatically enter the Debug mode, the problem of chip damage caused by manual operation is avoided, and the Debug efficiency is improved.
Example two
The present embodiment relates to a vehicle controller, which includes a module to be debugged 20, and a circuit for automatically entering a debug mode in the first embodiment, wherein the circuit is used for automatically entering the module to be debugged 20 into the debug mode. Meanwhile, the embodiment also relates to a vehicle provided with the whole vehicle controller.
The whole vehicle controller and the vehicle can realize that the chip automatically enters the Debug mode by arranging the circuit which automatically enters the Debug mode in the first embodiment, so that the normal operation of the chip is ensured, and the use experience is better.
The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the utility model.
Claims (8)
1. A circuit for automatically entering debug mode, comprising:
The system comprises a work wake-up circuit and a debug mode wake-up circuit which are connected in parallel between a power module and a module to be debugged;
The work wake-up circuit can output a work wake-up signal to a work wake-up port of the module to be debugged after receiving the output of the power supply module so as to enable the module to be debugged to enter a working state;
The input end of the debugging mode wake-up circuit is connected with the power module, the output end of the debugging mode wake-up circuit is connected with the debugging mode wake-up port of the module to be debugged, and the debugging mode wake-up circuit can output the debugging mode wake-up signal to the debugging mode wake-up port after receiving the output of the power module and at a time later than the time when the work wake-up port receives the work wake-up signal, so that the module to be debugged enters a debugging mode.
2. The circuit for automatically entering debug mode as recited in claim 1, wherein:
The debug mode wake-up circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor and a PNP triode;
The first end of the first resistor is respectively connected with the power supply module and the input end of the work awakening circuit;
The second end of the first resistor is connected with the first end of the second resistor and the emitter of the PNP triode respectively;
the second end of the second resistor is respectively connected with the first end of the fourth resistor and the first end of the first capacitor;
the second end of the fourth resistor is connected with the base electrode of the PNP triode;
The collector electrode of the PNP triode is respectively connected with the first end of the third resistor and the debug mode wake-up port;
the second end of the first capacitor is connected with the second end of the third resistor and grounded.
3. The circuit for automatically entering debug mode as recited in claim 2, wherein:
the debug mode wake-up circuit comprises a zener diode;
The first end of the zener diode is respectively connected with the second end of the first resistor, the first end of the second resistor and the emitter of the PNP triode;
The second end of the zener diode is respectively connected with the second end of the first capacitor and the second end of the third resistor, and is grounded.
4. The circuit for automatically entering debug mode as recited in claim 1, wherein:
the work awakening circuit comprises a filtering circuit, wherein the filtering circuit is used for filtering the output current of the power supply module.
5. The circuit for automatically entering debug mode as recited in claim 4, wherein:
the filter circuit comprises a fifth resistor, a second capacitor and a third capacitor;
the first end of the fifth resistor is connected with the power supply module, and the second end of the fifth resistor is connected with the work awakening port;
The first end of the second capacitor is connected between the first end of the fifth resistor and the power module, and the second end of the second capacitor is connected with the second end of the third capacitor and grounded;
The first end of the third capacitor is connected between the second end of the fifth resistor and the work wakeup port.
6. The circuit for automatically entering debug mode according to any one of claims 1 to 5, wherein:
The power module adopts a 12V power supply, and/or the module to be debugged adopts an SBC chip.
7. The utility model provides a whole car controller which characterized in that:
The whole vehicle controller comprises a module to be debugged and the circuit for automatically entering the debugging mode according to any one of claims 1 to 6, wherein the circuit is used for enabling the module to be debugged to automatically enter the debugging mode.
8. A vehicle, characterized in that:
The vehicle is provided with the whole vehicle controller as claimed in claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322607517.4U CN221056845U (en) | 2023-09-25 | 2023-09-25 | Circuit capable of automatically entering debugging mode, whole vehicle controller and vehicle |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322607517.4U CN221056845U (en) | 2023-09-25 | 2023-09-25 | Circuit capable of automatically entering debugging mode, whole vehicle controller and vehicle |
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| Publication Number | Publication Date |
|---|---|
| CN221056845U true CN221056845U (en) | 2024-05-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322607517.4U Active CN221056845U (en) | 2023-09-25 | 2023-09-25 | Circuit capable of automatically entering debugging mode, whole vehicle controller and vehicle |
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| Country | Link |
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| CN (1) | CN221056845U (en) |
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2023
- 2023-09-25 CN CN202322607517.4U patent/CN221056845U/en active Active
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