CN221040542U - Abnormal power-off control circuit for magnetic disk - Google Patents
Abnormal power-off control circuit for magnetic disk Download PDFInfo
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- CN221040542U CN221040542U CN202323159159.1U CN202323159159U CN221040542U CN 221040542 U CN221040542 U CN 221040542U CN 202323159159 U CN202323159159 U CN 202323159159U CN 221040542 U CN221040542 U CN 221040542U
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Abstract
The utility model provides a magnetic disk abnormal power-off control circuit, which comprises: the first switch is used for controlling the state of the change-over switch; the second switch is provided with a second control end, a second input end and a second output end which are connected with the first switch, the second input end is used for being connected with the first power supply, the second switch is used for receiving a switch state signal of the first switch through the second control end so as to switch the on-off state between the second input end and the second output end, and when the second switch is conducted, the second switch outputs a first magnetic disc power supply signal through the second output end and when the second switch is disconnected, the second switch cuts off power supply. By using the abnormal disk switching control circuit of the embodiment, the first switch is used for controlling the on-off of the second switch, and the on-off of the second switch influences the power supply to the disk to be tested. Therefore, abnormal power-off simulation of the disk to be tested can be realized by controlling the first switch, and whether the disk is lost or not is tested by controlling the abnormal power-off of the disk.
Description
Technical Field
The utility model relates to the technical field of magnetic disks, in particular to a magnetic disk abnormal power-off control circuit.
Background
In the related art, the electronic equipment has higher requirements on reliability, but the external use environment is sometimes uncontrollable, the electronic equipment which is normally running has abnormal power failure due to external power failure and other reasons, the abnormal power failure can cause the data loss of a disk of a storage device, and the problems that a system cannot be started and data cannot be recovered occur.
Therefore, it is necessary to test whether data loss occurs under abnormal power failure of the disk.
Disclosure of utility model
In view of the problems in the prior art, an object of the present utility model is to provide a disk abnormal power-off control circuit for testing whether data loss occurs to a disk by performing abnormal power-off control to the disk.
The embodiment of the utility model provides a disk abnormal power-off control circuit, which comprises:
The first switch is used for controlling the state of the change-over switch;
The second switch is provided with a second control end, a second input end and a second output end which are connected with the first switch, the second input end is used for being connected with the first power supply, the second switch is used for receiving a switch state signal of the first switch through the second control end so as to switch the on-off state between the second input end and the second output end, and when the second switch is conducted, the second switch outputs a first magnetic disc power supply signal through the second output end and when the second switch is disconnected, the second switch cuts off power supply.
In some embodiments, the first switch has a first control terminal, a first input terminal, and a first output terminal, the first switch being configured to be controlled by the first control terminal to switch a switch state between the first input terminal and the first output terminal and to output a switch state signal.
In some embodiments, the first switch and the second switch are both MOS transistors.
In some embodiments, the first switch is an NMOS transistor and the second switch is a PMOS transistor;
the first input end and the second control end are both used for being connected with a first power supply, and the first output end is grounded.
In some embodiments, the disk exception power down control circuit further comprises:
a first capacitor coupled between the second input terminal and the second control terminal;
The first node between the first capacitor and the second input terminal is used for coupling to a first power supply.
In some embodiments, the disk exception power down control circuit further comprises:
A first filter circuit is coupled to the first node.
In some embodiments, the first filter circuit includes a first set of capacitors coupled in parallel between the first node and the ground, the first set of capacitors including capacitors of different capacitance values.
In some embodiments, the disk exception power down control circuit further comprises:
the third switch is provided with a third control end, a third input end and a third output end which are connected with the first switch, the third input end is used for being connected with a third power supply, the third switch is used for receiving a switch state signal of the first switch through the third control end so as to switch the on-off state between the third input end and the third output end, and when the third switch is conducted, a second magnetic disc power supply signal is output through the third output end, and when the third switch is disconnected, power supply is cut off.
In some embodiments, the disk exception power down control circuit further comprises:
A fourth capacitor coupled between the third input terminal and the third control terminal;
the second node between the fourth capacitor and the third input terminal is used for coupling to a third power supply.
In some embodiments, the disk exception power down control circuit further comprises:
and a second filter circuit coupled to the second node.
The abnormal power-off control circuit for the magnetic disk provided by the utility model has the following advantages:
The abnormal power-off control circuit of the magnetic disk comprises: the first switch is used for controlling the state of the change-over switch; the second switch is provided with a second control end, a second input end and a second output end which are connected with the first switch, the second input end is used for being connected with the first power supply, the second switch is used for receiving a switch state signal of the first switch through the second control end so as to switch the on-off state between the second input end and the second output end, and when the second switch is conducted, the second switch outputs a first magnetic disc power supply signal through the second output end and when the second switch is disconnected, the second switch cuts off power supply. By using the abnormal disk switching control circuit of the embodiment, the first switch is used for controlling the on-off of the second switch, and the on-off of the second switch influences the power supply to the disk to be tested. Therefore, abnormal power-off simulation of the disk to be tested can be realized by controlling the first switch, and whether the disk is lost or not is tested by controlling the abnormal power-off of the disk.
Drawings
Other features, objects, and advantages of the present utility model will become more apparent from the detailed description set forth below with reference to the accompanying drawings.
FIG. 1 shows a schematic circuit diagram of a disk abnormal power-off control circuit provided in an embodiment of the disclosure;
FIG. 2 shows a circuit diagram of a disk abnormal power down control circuit provided by an embodiment of the present disclosure;
FIG. 3 shows a schematic interface diagram of a power connector cooperatively connected with the disk abnormal power-down control circuit shown in FIG. 2;
Fig. 4 shows a schematic interface diagram of a data transmission connector P1 mated with the power connector shown in fig. 3;
FIG. 5 shows a circuit diagram of another disk abnormal power down control circuit provided by an embodiment of the present disclosure;
FIG. 6 shows a schematic interface diagram of a connector cooperatively connected with the disk abnormal power-down control circuit shown in FIG. 5.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Fig. 1 shows a schematic circuit structure of a disk abnormal power-off control circuit according to an embodiment of the present disclosure, where, as shown in fig. 1, the disk abnormal power-off control circuit includes, but is not limited to, the following elements:
a first switch 11 for controlling the switching state;
The second switch 12 has a second control terminal 12a, a second input terminal 12b and a second output terminal 12c, where the first switch 11 is connected, the second input terminal 12b is used to connect to the first power source V1, the second switch 12 is used to receive a switch state signal of the first switch 11 through the second control terminal 12a to switch the on-off state between the second input terminal 12b and the second output terminal 12c, and output a first disk power supply signal through the second output terminal 12c when being on and cut off power supply when being off.
With the disk abnormality switching control circuit of the present embodiment, the first switch 11 is used for controlling the on-off of the second switch 12, and the on-off of the second switch 12 will affect the power supply to the disk to be tested. Therefore, the abnormal power-off simulation of the magnetic disk to be tested can be realized by controlling the first switch 11, so that whether the magnetic disk is lost or not is tested by performing the abnormal power-off control on the magnetic disk.
The test logic using the disk abnormal power-down control circuit of this embodiment is described as follows:
1. Disk test parameters such as a disk to be tested (disk), a test buffer size (bs), a time interval (time_on/time_off) of powering on and powering off the disk and the like are set.
2. Initializing a test environment according to the set test parameters: checking whether the disk to be tested exists or not, generating a test buffer with a specified size, filling the buffer with random data for writing in and comparing during test, and setting the power-on or power-off initial value of the disk to be tested if the time_on or the time_off is 0.
3. Sequentially starting a cache data writing thread, a disk data checking thread and a disk power supply control thread:
(1) And the cache data writing thread sequentially writes the initialized cache data into the disk when the disk is on line, the write-once size of the data is bs, and the writing address is incremented after the write-once is successful so as to write next time.
① If the writing of the cache data fails, the writing address is not increased, and the cache data is attempted to be rewritten from the original address.
② If the thread detects that the disk is offline, the thread stops writing data and waits for the disk to be re-online, and after the disk is re-online, the thread continues to write data backwards from the thread stop position.
③ And when the lead of the written position of the thread relative to the verification position of the data verification thread exceeds a certain value, the thread pauses for waiting, and when the data verification thread catches up with the progress of the written thread, the thread continues to write data.
(2) The disk data checking thread mainly reads a section of data with fixed size (bs) from the disk in sequence when the disk is on line, compares the section of data with the original data in the test cache (byte-by-byte comparison), if the section of data is different, the section of data is reported to be wrong, and the check address is increased to check the next position (whether the data is consistent or not) after the section of data is checked.
① If the disk data fails to read, the check address is not increased, and the cache data is attempted to be read again from the failed address.
② If the checking thread detects that the disk is offline, the thread stops checking data and waits for the disk to be on line again, and after the disk is on line again, the thread continues checking data from the thread stop position.
③ And stopping data verification when the data verification position exceeds the data writing position, and continuing to verify the data from the waiting position after the writing thread writes enough data.
(3) The disk power control thread can control the power-on and power-off of the disk according to the set power-on interval (time_on) and power-off interval (time_off). When the time_on or the time_off is 0, the power control interval adopts random values (time_on: 30s-60s, time_off:60s-180 s), otherwise, the set power-on and power-off interval is used.
① The disk is powered down after waiting for a time_off time after the disk is powered up. If time_on is 0, resetting the time interval of the next power-on of the magnetic disk, otherwise, using the set fixed value.
② The disk is powered up after waiting for a time_on time after the disk is powered down. If the time_off is 0, resetting the time interval of the next power-down of the magnetic disk, otherwise, using the set fixed value.
4. And if the check of one round is completed, regenerating the test cache and continuing the check of the new round.
In the above test logic, the first switch 11 is controlled to simulate the power-on and power-off of the disk to be tested, and whether the disk is lost or not is tested by simulating abnormal power-off. Specifically, a random time sequence is adopted to realize the design of the power-on and power-off time intervals of the magnetic disk to be tested so as to simulate the randomness problem of equipment power failure in the actual use scene and fit the actual use scene.
By combining the disk test logic of the disk abnormal power-off control circuit, the embodiment can realize automatic test on the integrity of disk data, data writing and data verification are respectively processed by independent threads, the disk bandwidth is utilized to the greatest extent, and the test efficiency is improved. In addition, the progress synchronization of data writing and data verification can be realized, and the problem that the progress of the data writing and the progress of the data verification are inconsistent in the test process is solved.
In one embodiment of the present disclosure, as shown in fig. 2, the first switch 11 has a first control terminal 11a, a first input terminal 11b, and a first output terminal 11c, and the first switch 11 is configured to be controlled by the first control terminal 11a to switch a switching state between the first input terminal 11b and the first output terminal 11c and output a switching state signal.
In one embodiment, as shown in fig. 2, the first switch 11 may select a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, chinese name of Metal-Oxide semiconductor field effect transistor) transistor, which is a voltage controlled device, and the MOS transistor may be kept on or off as long as there is a holding voltage when it is in normal operation (in an on or off steady state condition) without requiring current.
For example, the first switch 11 may select the NMOS transistor Q1, the first control terminal 11a corresponds to the gate G of the intermediate Q1, the first input terminal 11b corresponds to the drain D of the intermediate Q1, and the first output terminal 11c corresponds to the source S of the intermediate Q1. Q1 (i.e. the first switch 11), when the gate G receives a high level signal, the source S and the drain D are turned on, and Q1 is turned on. Conversely, when the gate G receives a low signal, the signal between the source S and the drain D is interrupted, and Q1 is turned off.
Specifically, the gate G (the first control terminal 11 a) of Q1 is connected to the power source pow_1_en, and the switching of the high-low level signal is realized by controlling the power on/off of the power source pow_1_en. The first resistor R1 is connected in series between the power source pow_1_en and the first control terminal 11a, and functions as a voltage divider.
In addition, the first switch can also use a PMOS tube, and a low-level signal is applied to the first control end to control the first switch to be turned on, and a high-level signal is applied to the first control end to control the first switch to be turned off.
In another embodiment, the first switch may also select a triode switch, a darlington switch using a triode cascade, or a thyristor switch, etc., without limitation.
As shown in fig. 2, the second switch 12 may select a MOS transistor.
For example, the second switch 12 selects the PMOS transistor Q2, the gate G of the Q2 corresponds to the second control terminal 12a, and the source S and the drain D of the Q2 are turned on by receiving the low level signal, the source S of the Q2 corresponds to the second input terminal 12b, and the drain D corresponds to the second input terminal 12c. Conversely, when gate G of Q2 receives a high signal, Q2 is turned off.
Specifically, as shown in fig. 2, the first input terminal 11b of the first switch 11 and the second control terminal 12a of the second switch 12 are both used for connecting to the second power source V2, and the first output terminal 11c is set to be grounded. When Q1 is turned off, the second power V2 is used to provide a high level signal to the gate G of Q2, so that it is in an off state. When the power supply is turned on, an electric signal of the second power supply V2 is transmitted through Q1, and the gate G potential of Q2 is a ground signal, so that the power supply V is turned off.
In another embodiment, the second switch may also use an NMOS transistor, where the input terminal of the first switch is separately connected to the power supply. At this time, when the first switch is turned on, a high level signal is supplied to the second switch to turn it on, whereas when the first switch is turned off, a low level signal is supplied to the second switch to turn it off.
Therefore, the types of the MOS transistors selected by the first switch and the second switch are not limited, the MOS transistors can be selected according to the needs, and the on-off state of the second switch can be switched finally through mutual cooperation.
In another embodiment, the second switch may also select a triode switch, a darlington switch using a triode cascade, or a thyristor switch, etc., without limitation.
In the embodiment of the present disclosure, as shown in fig. 2, the abnormal power-off control circuit for a disk further includes:
a first capacitor C1 coupled between the second input terminal 12b and the second control terminal 12 a;
the first node n1 between the first capacitor C1 and the second input terminal 12b is configured to be coupled to the first power source V1.
In this embodiment, the first capacitor C1 acts as a soft start for the second switch 12. As shown in fig. 2, in a normal case, the first power V1 charges the first capacitor C1. When the first switch 11 is turned on, the first capacitor C1 starts to discharge, so that the potential of the gate G of Q2 is slowly reduced, so that Q2 is slowly turned on, and the stress on the magnetic disk to be tested is reduced during power transmission, thereby prolonging the service life of the element and improving the reliability of the system.
The first power supply V1 provides a first disk power supply signal of the disk to be tested. The first power V1 may provide 12V or other voltage, and the second power V2 may provide 5V or other voltage.
In the embodiment of the present disclosure, a second resistor R2 is connected in series between the first capacitor C1 and the first input terminal 11b, and the second resistor R2 plays a role of voltage division. The resistance of the second resistor R2 is not limited in this embodiment.
In the embodiment of the present disclosure, as shown in fig. 2, the abnormal power-off control circuit for a disk further includes:
A first filter circuit 13 coupled to the first node n 1.
The first filter circuit 13 filters the power supply signal supplied from the first power supply V1.
In this embodiment, the first filter circuit 13 includes a first set of capacitors coupled between the first node n1 and the ground in parallel, and the first set of capacitors includes capacitors with different capacitance values. The first filter circuit 13 includes a second capacitor C2 and a third capacitor C3, wherein the second capacitor C2 and the third capacitor C3 are one-size and one-size, and together perform a filtering function.
In another embodiment, the first filter circuit may further adopt an electronic filter, an electronic voltage stabilizing filter, an inductive filter, etc., which is not limited herein.
As shown in fig. 2, the abnormal power-off control circuit of the disk further includes:
The third switch 14 has a third control terminal 14a, a third input terminal 14b and a third output terminal 14c connected to the first switch 11, the third input terminal 14b is used for being connected to the third power supply V3, the third switch 14 is used for receiving a switch state signal of the first switch 11 through the third control terminal 14a to switch the on-off state between the third input terminal 14b and the third output terminal 14c, and outputting a second disk power supply signal through the third output terminal 14c when being on and cutting off power supply when being off.
In the present embodiment, the second switch 12 and the third switch 14 are respectively connected to different power sources, and the voltage provided by the first power source V1 is different from the voltage provided by the third power source V3, so as to respectively correspond to the start voltages of different magnetic discs to be tested. In an actual process, if a single disk to be tested has two power supplies, the second switch 12 and the third switch 14 are connected to the single power supply on the single disk to be tested.
As shown in fig. 2, the third switch 14 may select a MOS transistor.
For example, the third switch 14 selects the PMOS transistor Q3, the gate G of the Q3 corresponds to the third control terminal 14a, the source S and the drain D of the Q3 are turned on by receiving the low level signal, the source S of the Q3 corresponds to the third input terminal 14b, and the drain D corresponds to the first input terminal 14c. Conversely, when gate G of Q3 receives a high signal, Q3 is turned off.
Specifically, as shown in fig. 2, the first input terminal 11b of the first switch 11 and the third control terminal 14a of the third switch 14 are both used for connecting to the second power source V2, and the first output terminal 11c is set to be grounded. When Q1 is turned off, the second power V2 is used to provide a high level signal to the gate G of Q3, so that it is in an off state. When the third power supply V3 is turned on, an electric signal of the third power supply V3 is transmitted through Q1, and the gate G potential of Q3 is a ground signal, so that the third power supply V is turned off.
In another embodiment, the third switch may also use an NMOS transistor, where the input terminal of the first switch is separately connected to the power supply. At this time, when the first switch is turned on, a high level signal is supplied to the third switch to turn it on, whereas when the first switch is turned off, a low level signal is supplied to the third switch to turn it off.
Therefore, the type of the MOS tube selected by the third switch is not limited, the MOS tube can be selected according to the requirement, and the on-off state of the third switch is finally switched by being matched with the first switch.
In another embodiment, the third switch may also select a triode switch, a darlington switch using a triode cascade, or a thyristor switch, etc., without limitation.
In the embodiment of the present disclosure, the second switch 12 and the third switch 14 are both fabricated on the same circuit board, which may promote circuit element layout rationality. Moreover, the abnormal power-off control can be carried out on two magnetic disks to be tested at the same time, so that the test of the lost data of the magnetic disks can be carried out.
In the embodiment of the disclosure, the abnormal power-off control circuit of the magnetic disk further comprises:
A fourth capacitor C4 coupled between the third input terminal 14b and the third control terminal 14 a;
The second node n2 between the fourth capacitor C4 and the third input terminal 14b is configured to be coupled to the third power source V3.
In this embodiment, the fourth capacitor C4 acts as a slow start for the third switch 14. As shown in fig. 2, in a normal case, the third power supply V3 charges the fourth capacitor C4. When the first switch 11 is turned on, the fourth capacitor C4 starts to discharge, so that the potential of the gate G of Q3 is slowly reduced, so that Q3 is slowly turned on, and the stress on the magnetic disk to be tested is reduced during power transmission, thereby prolonging the service life of the element and improving the reliability of the system.
In the embodiment of the present disclosure, a third resistor R3 is connected in series between the fourth capacitor C4 and the first input terminal 11b, and the third resistor R3 plays a role of voltage division. The resistance of the third resistor R3 is not limited in this embodiment.
In the embodiment of the disclosure, the abnormal power-off control circuit of the magnetic disk further comprises:
A second filter circuit 15 coupled to the second node n 2.
The second filter circuit 15 filters the power supply signal supplied from the third power supply V3.
In this embodiment, the second filter circuit 15 includes a second set of capacitors coupled between the second node n2 and the ground in parallel, and the second set of capacitors includes capacitors with different capacitance values. The second filter circuit 15 includes a fifth capacitor C5 and a sixth capacitor C6, wherein the fifth capacitor C5 and the sixth capacitor C6 are one-size and one-size, and together perform a filtering function.
In another embodiment, the second filter circuit may further adopt an electronic filter, an electronic voltage stabilizing filter, an inductive filter, etc., which is not limited herein.
As shown in fig. 2, the second output end 12c is provided with a first interface A1, and the first interface A1 is used for performing mating connection with a corresponding interface of the magnetic disk to be tested. The third output end 14c is provided with a second interface A2, and the second interface A2 is used for being in matched connection with a corresponding interface of the magnetic disk to be tested.
Referring to fig. 3, fig. 3 shows an interface schematic diagram of a power connector J1, where a pin 1 of the interface schematic diagram is connected to a first interface A1 of a disk abnormal power-off control circuit to provide a first power V1, such as 12V dc. Pin 4 of J1 is connected with a second interface A2 of the abnormal power-off control circuit of the magnetic disk to provide a third power supply V3, such as 5V direct current.
Fig. 4 shows an interface schematic of a data transmission connector P1, in which two pairs of power interfaces tx+ and TX-are shown and correspond to two pairs of disk interfaces, one pair of disk interfaces being sata_1_txp and sata_1_txn and the other pair of disk interfaces being sata_1_rxn and sata_1_rxp, respectively. Two pairs of power interfaces TX+ and TX-are connected with the connector J1 and the test disk, and the two pairs of disk interfaces are respectively connected with the test disk with the SATA interface.
In one embodiment, pow_1_en is connected to the normal GPIO pin of the X86 small system, defaults to low after power up, and the disk is in a powered down state. Q1, Q2 and Q3 are MOS tubes, and the power on and off of the test disk is controlled by controlling the V GS level of Q1. When V GS of Q1 is high level, the Q1 pipe is opened to conduct the Q2 pipe and the Q3 pipe, and the test disk is powered on; when V GS is at low level, the Q1 pipe is turned off, so that the Q2 pipe and the Q3 pipe are cut off, and the test of the powering down of the magnetic disk is completed.
In further embodiments of the present disclosure, as shown in fig. 5, the disk abnormal power-off control circuit includes only a first switch 51 (corresponding to Q4) and a second switch 52 (corresponding to Q5), and the disk abnormal power-off control circuit is used for testing a disk with an m.2 interface.
Fig. 6 shows an interface schematic of connector H1 of the m.2 interface test disc, in this embodiment the power interface connector and the data transfer connector are integrated onto the same circuit board. Wherein, the two power interfaces A4 and A5 may be separately connected to the third interface A3 shown in fig. 5. Accordingly, two pairs of disk interfaces sata_2_txp and sata_2_txn, and sata_2_rxn and sata_2_rxp are connected to the disk under test.
The foregoing is a further detailed description of the utility model in connection with the preferred embodiments, and it is not intended that the utility model be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the utility model, and these should be considered to be within the scope of the utility model.
Claims (10)
1. An abnormal power-off control circuit for a magnetic disk, comprising:
The first switch is used for controlling the state of the change-over switch;
The second switch is provided with a second control end, a second input end and a second output end which are connected with the first switch, the second input end is used for being connected with a first power supply, the second switch is used for receiving a switch state signal of the first switch through the second control end so as to switch the on-off state between the second input end and the second output end, and outputting a first magnetic disc power supply signal through the second output end when the second switch is connected and cutting off power supply when the second switch is disconnected.
2. The disk abnormal power-down control circuit according to claim 1, wherein the first switch has a first control terminal, a first input terminal, and a first output terminal, and the first switch is configured to be controlled by the first control terminal to switch a switching state between the first input terminal and the first output terminal and output a switching state signal.
3. The abnormal power-off control circuit of claim 2, wherein the first switch and the second switch are MOS transistors.
4. The abnormal power-off control circuit of claim 3, wherein the first switch is an NMOS transistor and the second switch is a PMOS transistor;
The first input end and the second control end are both used for being connected with a first power supply, and the first output end is grounded.
5. The disk power down anomaly control circuit of claim 1, further comprising:
a first capacitor coupled between the second input terminal and the second control terminal;
A first node between the first capacitor and the second input terminal is for coupling to the first power supply.
6. The disk power down anomaly control circuit of claim 5, further comprising:
a first filter circuit is coupled to the first node.
7. The disk power down anomaly control circuit of claim 6, wherein the first filter circuit comprises a first set of capacitors coupled in parallel between the first node and ground, the first set of capacitors comprising capacitors of different capacitance values.
8. The disk power down anomaly control circuit of claim 1, further comprising:
The third switch is provided with a third control end, a third input end and a third output end which are connected with the first switch, the third input end is used for being connected with a third power supply, the third switch is used for receiving a switch state signal of the first switch through the third control end so as to switch the on-off state between the third input end and the third output end, and outputting a second magnetic disc power supply signal through the third output end when the third switch is turned on and cutting off power supply when the third switch is turned off.
9. The disk power down anomaly control circuit of claim 8, further comprising:
A fourth capacitor coupled between the third input terminal and the third control terminal;
A second node between the fourth capacitor and the third input is for coupling to the third power supply.
10. The disk power down anomaly control circuit of claim 9, further comprising:
and a second filter circuit coupled to the second node.
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| CN202323159159.1U CN221040542U (en) | 2023-11-23 | 2023-11-23 | Abnormal power-off control circuit for magnetic disk |
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| CN202323159159.1U CN221040542U (en) | 2023-11-23 | 2023-11-23 | Abnormal power-off control circuit for magnetic disk |
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