CN216901640U - High-efficiency system capable of reading EDID under power failure - Google Patents
High-efficiency system capable of reading EDID under power failure Download PDFInfo
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- CN216901640U CN216901640U CN202220343983.9U CN202220343983U CN216901640U CN 216901640 U CN216901640 U CN 216901640U CN 202220343983 U CN202220343983 U CN 202220343983U CN 216901640 U CN216901640 U CN 216901640U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The utility model discloses an efficient system capable of reading EDID (extended display identification data) under power failure, which comprises a first controllable switch, a second controllable switch and an EEPROM (electrically erasable programmable read-only memory), wherein the first controllable switch and the second controllable switch have the following characteristics: if the fifth pin is electrified, the fifth pin is closed, the third pin and the fourth pin are connected in a default mode, when the fifth pin is electrified and the sixth pin is input with a high level, the fourth pin is switched to be connected with the first pin from the original mode that the fourth pin is connected with the third pin, if the fifth pin is not electrified, the fifth pin is disconnected, six pins of the first controllable switch and the second controllable switch are connected according to preset conditions, the main control chip is connected with the EEPROM in a corresponding state, the main control chip writes one simulated EDID into the EEPROM and the video coding and decoding chip respectively, and the simulated EDID is automatically generated for the main control chip. The utility model can accelerate the normal output efficiency of the display screen, and can read the EDID when the equipment is powered off.
Description
Technical Field
The utility model relates to the technical field of video reading EDID, in particular to a system which is efficient and can read EDID under power failure.
Background
EDID, also known as extended display identification data, in chinese, contains parameters related to the display and its performance, such as vendor information, maximum image size, color settings, vendor presets, limits on frequency range, and string of display name, display serial number, etc. When a computer host or other devices is connected to the display, the computer host reads the EDID from the DDC memory of the display through the DDC channel, so that the video output to the display is consistent with the display, for example, the size, color, and the like of the image are consistent with the display.
In some current applications, for example, after the video transmission box is powered on, the video source can read the EDID of the display screen through the HDMI connection line, once the video transmission box is powered off, the EDID cannot be read, so that the application is inconvenient, and the time from powering on to normally starting to transmit the video is long when the EDID is read after the video transmission box is powered on. Therefore, the conventional device for reading the EDID is often low in efficiency and cannot successfully read the EDID under the condition of power failure.
SUMMERY OF THE UTILITY MODEL
Aiming at the defects of the prior art, the utility model provides an efficient system capable of reading EDID under power failure, which can solve the problem that EDID cannot be read under power failure.
The technical scheme for realizing the purpose of the utility model is as follows: an efficient and power-down readable EDID system comprising an EEPROM and at least two controllable switches, the controllable switches comprising first to sixth pins, the six pins having the following characteristics:
if the fifth pin is electrified, the fifth pin is closed, the third pin and the fourth pin are connected by default, when the fifth pin is electrified and the sixth pin has high level input, the fourth pin is switched from being connected with the third pin to being connected with the first pin, if the fifth pin is not electrified, the fifth pin is disconnected,
the two controllable switches are respectively denoted as a first controllable switch and a second controllable switch,
in the first controllable switch, one end of a fifth pin is used for connecting an external video source through an external interface wire, the other end of the fifth pin is used for connecting with a common end under the condition of no electrification and connecting with one end of a fourth pin under the condition of electrification, the other end of the fourth pin is used for connecting with the first pin under the first condition, otherwise, the fourth pin is switched to be connected with a third pin, one end of a sixth pin is used for connecting with an external equipment power supply, the other end of the sixth pin is connected with the fourth pin, the first pin is used for connecting with a DDC memory in an external video decoding chip, the DDC memory is used for storing EDID written by the external main control chip to the video decoding chip, the third pin is used for connecting with a first pin of a second controllable switch, the second pin is grounded together with a second pin of the second controllable switch,
in the first case: the fifth pin is high and the sixth pin is high,
in the second controllable switch, one end of a fifth pin is used for being connected with an EEPROM (electrically erasable programmable read-only memory), the EEPROM is used for storing the EDID written by the main control chip, the other end of the fifth pin is used for being disconnected under the condition of no electrification and is connected with the common terminal and one end of a fourth pin under the condition of electrification, the other end of the fourth pin is used for being connected with the first pin under the first condition, otherwise, the connection is switched to be connected with a third pin, one end of a sixth pin is used for being connected with the common terminal, the other end of the sixth pin is connected with the fourth pin, and the third pin is used for being connected with the main control chip,
wherein the common end is a fourth pin of the second controllable switch, the power output end of the video source is connected with the connection node of the equipment power supply,
when the video coding and decoding chip is in the first state, the main control chip is communicated with the EEPROM, the main control chip writes a simulated EDID into the EEPROM and the video coding and decoding chip respectively, the simulated EDID is automatically generated for the main control chip,
the first state: the fifth pin and the fourth pin of the second controllable switch are connected, and the fourth pin of the second controllable switch and the third pin of the second controllable switch are connected.
Further, the first controllable switch and the second controllable switch are of the type ON-NC7SB 315796X.
Further, the external interface line is an HDMI line.
Furthermore, one end of a fifth pin of the first controllable switch is connected with an external HDMI socket, and the HDMI socket is used for being connected with the HDMI cable.
Further, the external device power supply is a device power supply which is independent and external to the first controllable switch and the second controllable switch or an internal independent device power supply which is integrated with the first controllable switch and the second controllable switch.
Further, a switch is arranged on the external device power supply or between the external device power supply and the first controllable switch, and between the external device power supply and the second controllable switch, when the switch is closed, the external device power supply supplies power outwards, otherwise, the external device power supply does not supply power outwards.
The utility model has the beneficial effects that: the video source can directly read the EDID from the EEPROM without reading the EDID from the display screen again, thereby greatly accelerating the normal output efficiency of the display screen. When the equipment is powered off, namely the power supply of the equipment can not provide power, the EDID can be stored when the HDMI wire is connected (namely the HDMI wire is inserted into the HDMI socket), namely the EDID can be read only by inserting the HDMI wire when the equipment is not powered on, and the video source can also be successfully read under the condition of power failure.
Drawings
FIG. 1 is a state diagram of situation one;
FIG. 2 is a state diagram of case two;
FIG. 3 is a state diagram of case three;
FIG. 4 is a state diagram of case four;
in the figure, 1-video source, 2-HDMI socket, 3-self-learning EDID module, 4-first controllable switch, 5-DDC memory, 6-video decoding chip, 7-main control chip, 8-equipment power supply, 9-second controllable switch and 10-EEPROM.
Detailed Description
The utility model is further described with reference to the accompanying drawings and the specific embodiments.
As shown in fig. 1-4, an efficient system for reading EDID in power-down condition includes a self-learning module and a peripheral circuit module connected to the self-learning module. The peripheral circuit module comprises a video source 1, an HDMI socket 2, a device power supply 8, a video decoding chip 6 and a main control chip 7, and the self-learning module comprises a first controllable switch 4, a second controllable switch 9 and an EEPROM10(Electrically Erasable Programmable read only memory).
In this embodiment, the self-learning module is equivalent to an internal component of the system which is efficient and can read the EDID when power is down, and the EDID can be read by connecting the self-learning module to the peripheral circuit module.
The first controllable switch 4 and the second controllable switch 9 have the following characteristics:
if the fifth pin is electrified (namely, electrified), the fifth pin is closed, and the third pin and the fourth pin are connected by default, namely, the third pin and the fourth pin are connected together; when the fifth pin is charged and the sixth pin has a high level input (i.e., charged, default charged is high level, and when the sixth pin is not charged, the sixth pin is low level (0V)), the fourth pin is connected with the first pin, that is, the fourth pin is switched from being originally connected with the third pin to being connected with the first pin. And when the fifth pin is not electrified, the fifth pin is disconnected.
One end of a fifth pin of the first controllable switch 4 is used for being connected with the HDMI socket 2, the HDMI socket 2 is also an HDMI physical interface, and the HDMI is connected with the video source 1 through an HDMI cable. The other end of the fifth pin is used to be connected to the common terminal or one end of the fourth pin in different states, that is, the fifth pin is not connected to the common terminal (disconnected from the fourth pin at this time) and is not connected to the fourth pin (disconnected from the common terminal at this time), and the common terminal is a connection node where the fourth pin of the second controllable switch 9 and the power output terminal of the video source 1 are connected to the device power supply 8. The other end of the fourth pin is used for being connected with the first pin or the third pin in different states, that is, the fourth pin is not connected with the first pin (disconnected with the third pin at the moment) and is not connected with the third pin (disconnected with the first pin at the moment), so that the fourth pin is switched and connected with one of the first pin and the third pin. One end of a sixth pin of the first controllable switch 4 is used for being connected with the equipment power supply 8, and the other end of the sixth pin is connected with the fourth pin. Although in fig. 1-4 the device power supply 8 is located inside the self-learning module, the device power supply 8 is typically an external stand-alone power supply, although the device power supply 8 may also be integrated in the self-learning module as a stand-alone sub-module in the self-learning module. In practical applications, the device power supply 8 itself has a switch or a switch is disposed between the device power supply 8 and the sixth pin, only when the switch is turned on, the device power supply 8 provides a high level to the sixth pin, and when the switch is turned off, although the device power supply 8 is connected to the sixth pin, the device power supply 8 does not provide power to the sixth pin at this time. The first pin of the first controllable switch 4 is used for connecting with the DDC memory 5 in the video decoding chip 6, the DDC memory 5 is used for storing EDID, and the video decoding chip 6 is connected with the main control chip 7. The third pin of the first controllable switch is connected to the first pin of the second controllable switch 9. The second pin of the first controllable switch 4 and the second pin of the second controllable switch 9 are commonly grounded.
The other end of the fifth pin is used for being connected with the common end or one end of the fourth pin in different states, and the fifth pin is connected with the fourth pin when the fifth pin is electrified, and the fifth pin is connected with the common end when the fifth pin is not electrified. The other end of the fourth pin is used for being in switching connection with the first pin or the third pin in different states, and the switching connection means that when the fifth pin is powered and the sixth pin is at a high level, the fourth pin is connected with the first pin, and under other conditions, the fourth pin is connected with the first pin by default, that is, when the fifth pin is powered and the sixth pin is at a high level, the fourth pin is connected with the first pin, otherwise, the fourth pin is switched from being connected with the first pin to being connected with the third pin.
One end of the fifth pin of the second controllable switch 9 is used for being connected with the EEPROM10, and the other end of the fifth pin is used for being connected with or disconnected from the common terminal and one end of the fourth pin in different states, that is, the fifth pin is not connected with the common terminal and the fourth pin, but is not connected with the common terminal and the fourth pin, and the common terminal is a connection node between the fifth pin of the second controllable switch 9 and the power output terminal of the video source 1. The other end of the fourth pin is used for being connected with the first pin or the third pin in different states, that is, the fourth pin is not connected with the first pin (disconnected with the third pin at this time) and is not connected with the third pin (disconnected with the first pin at this time). One end of a sixth pin of the second controllable switch 9 is used for being connected with the common end, and the other end is connected with a fourth pin. Although in fig. 1-4 the device power supply 8 is located inside the self-learning module, the device power supply 8 is typically an external stand-alone power supply, although the device power supply 8 may also be integrated in the self-learning module as a stand-alone sub-module in the self-learning module. A first pin of the second controllable switch 9 is used for being connected with a third pin of the first controllable switch 4, and a third pin of the second controllable switch 9 is used for being connected with the main control chip 7. A second pin of the second controllable switch 9 and a second pin of the first controllable switch 4 are commonly grounded.
The other end of the fifth pin is used for being connected or disconnected with the common terminal and one end of the fourth pin in different states, and the fifth pin is connected with the common terminal and the fourth pin when the fifth pin is electrified, and disconnected with the common terminal and the fourth pin when the fifth pin is not electrified. The other end of the fourth pin is used for being in switching connection with the first pin or the third pin in different states, and the switching connection means that when the fifth pin is powered and the sixth pin is at a high level, the fourth pin is connected with the first pin, under other conditions, the fourth pin is connected with the first pin by default, that is, when the fifth pin is powered and the sixth pin is at a high level, the fourth pin is connected with the first pin, and otherwise, the fourth pin is switched to be connected with the third pin from being connected with the first pin.
The working principle is as follows: as shown in fig. 1, in case of this situation, the fourth pins of the first controllable switch 4 and the second controllable switch 9 are connected to the third pin in a default state, the fifth pin of the first controllable switch 4 is connected to the common terminal and disconnected from the fourth pin of the first controllable switch 4, the fifth pin of the first controllable switch 4 is connected to the common terminal, and the fifth pin of the second controllable switch 9 is disconnected from the EEPROM 10.
Wherein, the first case is: the device power supply 8 is not energized outward and does not access the HDMI line. The HDMI cable is not connected, that is, the HDMI socket 2 is not connected to the HDMI cable, and the first controllable switch 4 is not connected to the video source 1.
As shown in fig. 2, in case two, in the first controllable switch 4, the connection of the fourth pin with the third pin is switched to be connected with the first pin, the fifth pin is still disconnected from the fourth pin, and the fifth pin is connected with the common terminal. In the second controllable switch 9, the fifth pin is connected to the third pin, and the fourth pin is connected to the third pin.
The second case is: the device power supply 8 is powered out and does not access the HDMI line.
In case two, the fifth pin of the second controllable switch 9 is powered by the device power supply 8 and is conducted with the fourth pin, and the fourth pin is conducted with the third pin by default, so that the main control chip 7 and the EEPROM10 are conducted. When the main control chip 7 is connected with the EEPROM10, the main control chip 7 writes an analog EDID into the EEPROM10 and the video codec chip, respectively. The simulated EDID is automatically generated by the main control chip 7, namely the main control chip 7 simulates a virtual EDID, and the virtual EDID can be suitable for most display screens, because the display screens of most models have the EDID corresponding to the models at present, so that the virtual EDID can be consistent with the real EDID.
As shown in fig. 3, in case three, in the first controllable switch 4, the fifth pin is connected to the fourth pin, the fifth pin is connected to the HDMI socket 2 (i.e. connected to the HDMI cable), the fifth pin is disconnected from the common terminal, and the fourth pin is connected to the third pin. In the second controllable switch 9, the fifth pin is connected to the fourth pin, and the fourth pin is connected to the first pin, that is, the fourth pin is switched to be connected to the first pin from the default state to the third pin.
The third case is: the device power supply 8 is unpowered and accesses the HDMI line. At this time, since the HDMI line is connected, the HDMI line can supply a voltage (usually 5V), and the fifth pins of the first controllable switch 4 and the second controllable switch 9 are both turned on with the corresponding fourth pins due to electrification. The sixth pin of the second controllable switch 9 is also charged by receiving the voltage provided by the HDMI line, so that the fourth pin is switched to be connected to the first pin, the DDC channel of the video source 1 is connected to the EEPROM10 through the HDMI line, and EDID written into the EEPROM10 by the main controller can be read. In the first controllable switch 4, the sixth pin is not powered because the device power supply 8 is not supplying power, and the fourth pin is still connected to the third pin.
As shown in fig. 4, in the case of the fourth case, in the first controllable switch 4, the fifth pin is connected to the fourth pin, the fifth pin is disconnected from the common terminal, and the fourth pin is connected to the first pin. In the second controllable switch 9, the fifth pin is connected to the fourth pin, the fifth pin is connected to the EEPROM10 and the common terminal, and the fourth pin is connected to the first pin. The respective fifth pins of the first controllable switch 4 and the second controllable switch 9 are powered, so that the fifth pin of the first controllable switch 4 is connected with the HDMI socket 2, and the fifth pin of the second controllable switch 9 is connected with the EEPROM 10. And the sixth pin of the second controllable switch 9 is powered, the fourth pin of the second controllable switch 9 will be switched to be connected with the first pin of the second controllable switch 9. The device power supply 8 supplies power and the fourth pin of the first controllable switch 4 is switched from being on with the third pin by default to being on with the first pin. The video source 1 can be connected with the video codec chip through the HDMI cable, and reads EDID from the DDC memory 5 in the video codec chip.
The fourth case is: the device power supply 8 supplies power and is connected to the HDMI line.
In the above embodiments, the video source 1 is connected to an HDMI line and supplied with power, and in actual use, another video connection line, for example, a DP line, may be used.
According to the four situations, when the power supply 8 of the device is powered on, the video source 1 does not need to read the EDID from the display screen (that is, the display screen where the video codec chip is located in the figure) again, but can directly read the EDID from the EEPROM10, so that the normal output efficiency of the display screen can be greatly improved. When the equipment is powered off, namely the equipment power supply 8 can not provide power, the EDID can be stored when the HDMI line is connected (namely the HDMI line is inserted into the HDMI socket 2), namely the EDID can be read only by inserting the HDMI line when the equipment is not powered on, and the video source 1 can also be successfully read under the condition of power failure.
The first controllable switch 4 and the second controllable switch 9 are of the type ON-NC7SB315796X, but in practical applications, other types of controllable switches including the above-mentioned features may be used.
The embodiments disclosed in this description are only an exemplification of the single-sided characteristics of the utility model, and the scope of protection of the utility model is not limited to these embodiments, and any other functionally equivalent embodiments fall within the scope of protection of the utility model. Various other changes and modifications to the above-described embodiments and concepts will become apparent to those skilled in the art from the above description, and all such changes and modifications are intended to be included within the scope of the present invention as defined in the appended claims.
Claims (6)
1. The system capable of reading the EDID efficiently under the condition of power failure is characterized by comprising an EEPROM and at least two controllable switches, wherein the controllable switches comprise a first pin and a sixth pin, and the six pins have the following characteristics:
if the fifth pin is electrified, the fifth pin is closed, the third pin and the fourth pin are connected by default, when the fifth pin is electrified and the sixth pin has high level input, the fourth pin is switched from being connected with the third pin to being connected with the first pin, if the fifth pin is not electrified, the fifth pin is disconnected,
the two controllable switches are respectively denoted as a first controllable switch and a second controllable switch,
in the first controllable switch, one end of a fifth pin is used for connecting an external video source through an external interface wire, the other end of the fifth pin is used for connecting with a common end under the condition of no electrification and connecting with one end of a fourth pin under the condition of electrification, the other end of the fourth pin is used for connecting with the first pin under the first condition, otherwise, the fourth pin is switched to be connected with a third pin, one end of a sixth pin is used for connecting with an external equipment power supply, the other end of the sixth pin is connected with the fourth pin, the first pin is used for connecting with a DDC memory in an external video decoding chip, the DDC memory is used for storing EDID written by the external main control chip to the video decoding chip, the third pin is used for connecting with a first pin of a second controllable switch, the second pin is grounded together with a second pin of the second controllable switch,
in the first case: the fifth pin is high and the sixth pin is high,
in the second controllable switch, one end of a fifth pin is used for being connected with an EEPROM (electrically erasable programmable read-only memory), the EEPROM is used for storing the EDID written by the main control chip, the other end of the fifth pin is used for being disconnected under the condition of no electrification and is connected with the common terminal and one end of a fourth pin under the condition of electrification, the other end of the fourth pin is used for being connected with the first pin under the first condition, otherwise, the connection is switched to be connected with a third pin, one end of a sixth pin is used for being connected with the common terminal, the other end of the sixth pin is connected with the fourth pin, and the third pin is used for being connected with the main control chip,
wherein the common end is a fourth pin of the second controllable switch, the power output end of the video source is connected with the connection node of the equipment power supply,
when the video coding and decoding chip is in the first state, the main control chip is communicated with the EEPROM, the main control chip writes a simulated EDID into the EEPROM and the video coding and decoding chip respectively, the simulated EDID is automatically generated for the main control chip,
the first state: the fifth pin and the fourth pin of the second controllable switch are connected, and the fourth pin of the second controllable switch and the third pin of the second controllable switch are connected.
2. The system for efficient and power down readable EDID according to claim 1, wherein the first controllable switch and the second controllable switch are of the type ON-NC7SB 315796X.
3. The system for efficient and power down readable EDID according to claim 1, wherein the external interface lines are HDMI lines.
4. The system according to claim 3, wherein one end of the fifth pin of the first controllable switch is connected to an external HDMI socket, and the HDMI socket is used for connecting to the HDMI cable.
5. The system according to claim 1, wherein the external device power supply is a device power supply that is independent of the first and second controllable switches or an internal independent device power supply that is integrated with the first and second controllable switches.
6. The system according to claim 1 or 5, wherein a switch is provided on or between the external device power supply and the first controllable switch, the external device power supply and the second controllable switch, and when the switch is closed, the external device power supply supplies power, otherwise the external device power supply does not supply power.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220343983.9U CN216901640U (en) | 2022-02-18 | 2022-02-18 | High-efficiency system capable of reading EDID under power failure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220343983.9U CN216901640U (en) | 2022-02-18 | 2022-02-18 | High-efficiency system capable of reading EDID under power failure |
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| CN216901640U true CN216901640U (en) | 2022-07-05 |
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| CN202220343983.9U Active CN216901640U (en) | 2022-02-18 | 2022-02-18 | High-efficiency system capable of reading EDID under power failure |
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Address after: No. 56 Nanli East Road, Shiqi Town, Panyu District, Guangzhou City, Guangdong Province, 510000 Patentee after: Guangdong Baolun Electronics Co.,Ltd. Address before: No.19 Chuangyuan Road, Zhongcun street, Panyu District, Guangzhou, Guangdong 510000 Patentee before: GUANGZHOU ITC ELECTRONIC TECHNOLOGY Co.,Ltd. |
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