CN220983380U - Power failure detection circuit - Google Patents
Power failure detection circuit Download PDFInfo
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- CN220983380U CN220983380U CN202420847804.4U CN202420847804U CN220983380U CN 220983380 U CN220983380 U CN 220983380U CN 202420847804 U CN202420847804 U CN 202420847804U CN 220983380 U CN220983380 U CN 220983380U
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Abstract
The utility model provides a power failure detection circuit, which comprises a first detection module, a second detection module and a first detection module, wherein the first detection module is configured to detect whether an input voltage is lower than a set first threshold value; a second detection module configured to detect whether a falling slope of the input voltage satisfies a set second threshold; the second detection module includes: the device comprises a first comparator, a second comparator, a fixed delay module and an AND gate; the first comparator is used for comparing the input voltage with the set first reference voltage, the output end of the first comparator is connected with the input end of the fixed delay module, and the output end of the fixed delay module is connected with the first input end of the AND gate; the second comparator is used for comparing the input voltage with a set second reference voltage, and the output end of the second comparator is connected with the second input end of the AND gate. The utility model can realize the detection of the fast power-down scene through the falling slope of the input voltage, and can realize the detection of the slow power-down scene through the comparison of the input voltage and the undervoltage threshold value.
Description
Technical Field
The utility model relates to the technical field of power failure detection, in particular to a power failure detection circuit.
Background
At present, our lives are full of various devices which rely on electric energy to provide energy, and the devices bring great convenience to our production and life. For some devices that rely on electrical energy to provide energy, a power loss can have a significant impact on the proper operation of the device, such as loss of power, damage to hardware, loss of data and files, and the like. The power failure detection circuit can monitor the system voltage of the equipment, gives an alarm signal when the equipment is detected to be powered down, and can trigger the equipment to take corresponding protection measures at the same time so as to avoid serious consequences.
The Chinese patent application with the application number 202310037321.8 discloses a silencing circuit and a chip, wherein the silencing circuit comprises a power amplification module and a power-down detection module, the power-down detection module comprises a plurality of detection modes, the detection of the power-down condition of the power supply voltage under different scenes can be realized, the application range of the power-down detection is improved, and the specific circuit of the power-down detection module is not disclosed.
The invention of China with the application number 201811083339.7 discloses a power-down detection circuit and a control method thereof, wherein the power-down detection circuit comprises a power-down detection sub-circuit, the power-down detection sub-circuit is used for acquiring the output voltage of a low-voltage side power supply, determining whether a power-down event occurs in the low-voltage side power supply according to the output voltage of the low-voltage side power supply, and sending a power-down signal to a controller if the power-down event is determined. Although this application discloses several specific implementations of the power down detection sub-circuit, it is not capable of power down detection in different scenarios.
Disclosure of utility model
In order to solve at least one of the above technical problems, the utility model provides a power failure detection circuit.
A power loss detection circuit comprising:
a first detection module configured to detect whether an input voltage is below a set first threshold;
A second detection module configured to detect whether a falling slope of the input voltage satisfies a set second threshold;
The second detection module includes: the device comprises a first comparator, a second comparator, a fixed delay module and an AND gate; the first comparator is used for comparing the input voltage with a set first reference voltage, the output end of the first comparator is connected with the input end of the fixed delay module, and the output end of the fixed delay module is connected with the first input end of the AND gate; the second comparator is used for comparing the input voltage with a set second reference voltage, and the output end of the second comparator is connected with the second input end of the AND gate; the output end of the AND gate is used as the output end of the second detection module.
Preferably, the fixed delay module includes a switching tube, a current source, a capacitor and a schmitt trigger, where the switching tube is connected with an output end of the first comparator, and is used for changing a voltage of an end of the capacitor far away from ground according to an output of the first comparator, the capacitor is disposed between the output end of the current source and ground, an input end of the schmitt trigger is connected with an end of the capacitor far away from ground, and an output end of the schmitt trigger is used as an output end of the fixed delay module and connected with a first input end of the and gate.
In any of the above schemes, preferably, the switch tube is an NMOS tube, a gate thereof is connected to an output terminal of the first inverter, a source thereof is grounded, and a drain thereof is connected to an end of the capacitor remote from ground; the input end of the first inverter is connected with the output end of the first comparator; the positive input end of the first comparator inputs the first reference voltage, and the negative input end is connected with the input voltage VIN.
In any of the above schemes, preferably, the switch tube is an NMOS tube, a gate thereof is directly connected to an output terminal of the first comparator, a source thereof is grounded, and a drain thereof is connected to an end of the capacitor remote from ground; the reverse input end of the first comparator inputs the first reference voltage, and the forward input end is connected with the input voltage VIN.
In any of the above schemes, preferably, the second reference voltage is input to the positive input terminal of the second comparator, the negative input terminal is connected to the input voltage VIN, and the output terminal is directly connected to the second input terminal of the and gate.
In any of the above schemes, preferably, the second reference voltage is input to the reverse input terminal of the second comparator, the forward input terminal is connected to the input voltage VIN, the output terminal is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the second input terminal of the and gate.
In any of the above schemes, preferably, the first detection module includes a third comparator, the reverse input end of the third comparator inputs the voltage VIN, the forward input end inputs the undervoltage threshold voltage, and the output end of the second detection module are respectively connected with two input ends of an or gate.
In any of the above schemes, preferably, the first detection module includes a third comparator, where a forward input end of the third comparator inputs the voltage VIN, a reverse input end inputs the undervoltage threshold voltage, an output end of the third comparator is connected with an input end of the third inverter, and an output end of the third inverter and an output end of the second detection module are respectively connected with two input ends of an or gate.
In any of the above aspects, preferably, an output end of the or gate is connected to an input end of an output module, and the output module is configured according to an output signal of the or gate.
The power failure detection circuit has the following beneficial effects:
1. The detection of the fast power-down scene can be realized through the falling slope of the input voltage, and the detection of the slow power-down scene can be realized through the comparison of the input voltage and the undervoltage threshold value;
2. The situations that response is delayed and actions cannot be fed back in time only through threshold detection can be avoided; the situation that smooth power failure cannot be identified only through slope detection can be avoided;
3. The circuit is simple, and the power failure detection under different scenes can be simultaneously met.
Drawings
Fig. 1 is a schematic diagram of the overall structure of a preferred embodiment of a power down detection circuit according to the present utility model.
Fig. 2 is a schematic structural diagram of a preferred embodiment of a second detection module of the power-down detection circuit according to the present utility model.
Fig. 3 is a signal diagram of the second detection module of the power-down detection circuit according to the present utility model for power-down detection according to the embodiment shown in fig. 2.
Fig. 4 is a schematic structural diagram of a preferred embodiment of a first detection module of the power-down detection circuit according to the present utility model.
Fig. 5 is a signal diagram of the first detection module of the power-down detection circuit according to the present utility model for power-down detection according to the embodiment shown in fig. 5.
Fig. 6 is a schematic structural diagram of another embodiment of a second detection module of the power-down detection circuit according to the present utility model.
Detailed Description
The utility model will be described in more detail with reference to specific examples.
Example 1: as shown in fig. 1, a power-down detection circuit includes:
a first detection module configured to detect whether an input voltage is below a set first threshold;
A second detection module configured to detect whether a falling slope of the input voltage satisfies a set second threshold;
The input ends of the first detection module and the second detection module are connected with input voltage VIN, the output ends of the first detection module and the second detection module are respectively connected with two input ends of an OR gate G1, the output end of the OR gate G1 is connected with the input end of the output module so as to output an Enable signal to the output module, and the output module outputs a corresponding signal according to the Enable signal. In this embodiment, it is preferable that the Output module outputs the first Output signal Output1 and the second Output signal Output2 according to the Enable signal.
In this embodiment, as shown in fig. 2, preferably, the second detection module includes: a first comparator CMP1, a second comparator CMP2, a fixed delay module and an and gate G2; the first comparator CMP1 is configured to compare the input voltage VIN with a set first reference voltage ref1, an output end of the first comparator CMP1 is connected to an input end of the fixed delay module, and an output end of the fixed delay module is connected to a first input end of the and gate G2; the second comparator CMP2 is configured to compare the input voltage VIN with a set second reference voltage ref2, and an output terminal thereof is connected to a second input terminal of the and gate G2; the output end of the and gate G2 is used as the output end of the second detection module, that is, the output end of the and gate G2 is connected with one input end of the or gate G1. The value of the first reference voltage ref1 is larger than the value of the second reference voltage ref 2.
In this embodiment, as shown in fig. 2, it is further preferable that the fixed delay module includes a switching tube, a current source I, a capacitor C, and a schmitt trigger G4, where the switching tube is connected to an output end of the first comparator CMP1, and is configured to change a voltage of an end of the capacitor C away from the ground GND according to an output of the first comparator CMP1, the capacitor C is disposed between the output end of the current source I and the ground GND, an input end of the schmitt trigger G4 is connected to an end of the capacitor C away from the ground GND, and an output end of the schmitt trigger G4 is connected to a first input end of the and gate G2 as an output end of the fixed delay module.
In this embodiment, as shown in fig. 2, the switching tube adopts an NMOS tube MN1, the gate of which is connected to the output terminal of the first inverter G3, the source is grounded GND, and the drain is connected to the output terminal of the current source I; the input end of the first inverter G3 is connected with the output end of the first comparator CMP 1; the positive input end of the first comparator CMP1 inputs the first reference voltage ref1, and the negative input end is connected to the input voltage VIN.
In this embodiment, as shown in fig. 2, it is still further preferable that the second reference voltage ref2 is input to the positive input terminal of the second comparator CMP2, the negative input terminal is connected to the input voltage VIN, and the output terminal is directly connected to the second input terminal of the and gate G2.
As shown in fig. 3, when the value of the input voltage VIN is higher than the first reference voltage ref1, the first comparator CMP1 and the second comparator CMP2 both output low-level signals, at this time, the first inverter G3 outputs high-level signals, the NMOS tube MN1 is turned on, one end of the capacitor C far from the ground GND is low-level, and the schmitt trigger G4 outputs high-level; at this time, the and gate G2 outputs a low level.
When the input voltage VIN starts to drop below ref1, the first comparator CMP1 outputs a high level signal to the first inverter G3, the first inverter G3 outputs a low level signal to the gate of the NMOS transistor MN1, the NMOS transistor MN1 is turned off, and the current source I starts to charge the capacitor C. Assuming that the output signal of the schmitt trigger G4 transitions from a high level to a low level after the current source I charges the capacitor C for T time; meanwhile, assume that the Time taken for the input voltage VIN to drop from ref1 to ref2 is Pulse Time. If Pulse Time is greater than or equal to T, when the input voltage VIN drops to ref2, the output of the Schmitt trigger G4 is already converted into a low level, at this Time, the output of the second comparator CMP2 is a high level, and the AND gate G2 outputs a low level; at this time, the falling slope of the input voltage VIN does not satisfy the set second threshold. If Pulse Time is less than T, when the input voltage VIN is reduced to ref2, the output of the Schmitt trigger G4 is still at a high level, and the second comparator CMP2 outputs a high level and the AND gate G2 outputs a high level; at this time, it is explained that the falling slope of the input voltage VIN satisfies the set second threshold.
It should be understood that, if the and gate G2 outputs a high level signal, it is indicated that the falling slope of the input voltage VIN meets the set second threshold, and it is determined that a fast power-down occurs at this time. Through the detection of the falling slope of the input voltage VIN, the occurrence of the rapid power failure condition can be rapidly identified, and the situations that the response is delayed and the action cannot be fed back in time when the threshold value is detected are avoided. When judging that the quick power failure occurs, the or gate G1 changes the Enable signal Output by the Output module from low level to high level, and the signal Output by the Output module correspondingly changes according to the change of the Enable signal, for example, output1 changes from high level to low level, output2 changes from low level to high level, and further other circuit parts can take corresponding protection measures according to the signal Output by the Output module so as to avoid serious consequences caused by power failure. It should be noted that, the change of the signal output by the output module in this embodiment is only illustrative, and not limiting.
As shown in fig. 4, the first detection module includes a third comparator CMP3, where an inverting Input terminal of the third comparator CMP3 is connected to the Input voltage VIN, a forward Input terminal inputs the under-voltage threshold voltage Input uvlo_f (i.e., a first threshold value), and an output terminal of the second detection module is connected to another Input terminal of the or gate G1.
As shown in fig. 5, when the Input voltage VIN decreases to the undervoltage threshold voltage Input uvlo_f, the third comparator CMP3 outputs a signal that changes from a low level to a high level, and at this time, it is determined that a smooth power failure has occurred. By comparing the Input voltage VIN with the under-voltage threshold voltage Input uvlo_f, a smooth power loss can be identified, avoiding the situation that the smooth power loss cannot be identified when passing the slope detection. When it is judged that smooth power failure occurs, an Enable signal Output by the or gate G1 to the Output module is changed from a low level to a high level, and a signal Output by the Output module is correspondingly changed according to the change of the Enable signal, for example, output1 is changed from a high level to a low level, output2 is changed from a low level to a high level, and further, other subsequent circuit parts can take corresponding protection measures according to the signal Output by the Output module, so that serious consequences caused by power failure are avoided. It should be noted that, the change of the signal output by the output module in this embodiment is only illustrative, and not limiting.
Example 2: this embodiment is similar to the foregoing embodiment, except that in this embodiment, it is preferable that, as shown in fig. 6, the first reference voltage ref1 is input to the inverting input terminal of the first comparator CMP1, the input voltage VIN is connected to the forward input terminal, and the output terminal is directly connected to the gate of the NMOS transistor MN 1.
Meanwhile, the second reference voltage ref2 is input to the reverse input end of the second comparator CMP2, the input voltage VIN is connected to the forward input end, the output end is connected to the input end of the second inverter G5, and the output end of the second inverter G5 is connected to the second input end of the and gate G2.
Example 3: the present embodiment is similar to the foregoing embodiment, except that in this embodiment, it is preferable that the forward Input terminal of the third comparator CMP3 is connected to the Input voltage VIN, the reverse Input terminal is Input with the under-voltage threshold voltage Input uvlo_f, the output terminal is connected to the Input terminal of the third inverter, and the output terminal of the third inverter and the output terminal of the second detection module are respectively connected to the two Input terminals of the or gate G1.
It should be noted that, the technical solutions of the present utility model relate to improvements in hardware, and do not relate to improvements in software; for each part of which the model is not indicated, the part can be selected from common parts in the prior art, and is not limited by the model; for each component of the model specified in the embodiments, only for describing the technical solution of the present utility model in detail, it should be understood that the technical solution to be protected by the present utility model is not limited by the model, and there are many alternatives in the prior art for replacing the component.
The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting thereof; while the foregoing embodiments are illustrative of the present utility model in detail, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents, which do not depart from the scope of the technical scheme of the present utility model.
Claims (9)
1. A power loss detection circuit comprising:
a first detection module configured to detect whether an input voltage is below a set first threshold; the method is characterized in that: further comprises:
A second detection module configured to detect whether a falling slope of the input voltage satisfies a set second threshold;
The second detection module includes: the device comprises a first comparator, a second comparator, a fixed delay module and an AND gate; the first comparator is used for comparing the input voltage with a set first reference voltage, the output end of the first comparator is connected with the input end of the fixed delay module, and the output end of the fixed delay module is connected with the first input end of the AND gate; the second comparator is used for comparing the input voltage with a set second reference voltage, and the output end of the second comparator is connected with the second input end of the AND gate; the output end of the AND gate is used as the output end of the second detection module and is connected with the first input end of an OR gate.
2. The power down detection circuit of claim 1, wherein: the fixed delay module comprises a switching tube, a current source, a capacitor and a Schmitt trigger, wherein the switching tube is connected with the output end of the first comparator and is used for changing the voltage of one end of the capacitor far away from the ground according to the output of the first comparator, the capacitor is arranged between the output end of the current source and the ground, the input end of the Schmitt trigger is connected with one end of the capacitor far away from the ground, and the output end of the Schmitt trigger is used as the output end of the fixed delay module and is connected with the first input end of the AND gate.
3. The power down detection circuit of claim 2, wherein: the switching tube adopts an NMOS tube, the grid electrode of the switching tube is connected with the output end of the first phase inverter, the source electrode of the switching tube is grounded, and the drain electrode of the switching tube is connected with one end of the capacitor far away from the ground; the input end of the first inverter is connected with the output end of the first comparator; the positive input end of the first comparator inputs the first reference voltage, and the negative input end is connected with the input voltage VIN.
4. The power down detection circuit of claim 2, wherein: the switching tube adopts an NMOS tube, the grid electrode of the switching tube is directly connected with the output end of the first comparator, the source electrode of the switching tube is grounded, and the drain electrode of the switching tube is connected with one end of the capacitor far away from the ground; the reverse input end of the first comparator inputs the first reference voltage, and the forward input end is connected with the input voltage VIN.
5. The power down detection circuit of claim 2, wherein: the positive input end of the second comparator inputs the second reference voltage, the negative input end is connected with the input voltage VIN, and the output end is directly connected with the second input end of the AND gate.
6. The power down detection circuit of claim 2, wherein: the reverse input end of the second comparator inputs the second reference voltage, the forward input end is connected with the input voltage VIN, the output end is connected with the input end of the second inverter, and the output end of the second inverter is connected with the second input end of the AND gate.
7. The power down detection circuit of claim 1, wherein: the first detection module comprises a third comparator, the reverse input end of the third comparator inputs voltage VIN, the forward input end inputs undervoltage threshold voltage, and the output end is connected with the second input end of the OR gate.
8. The power down detection circuit of claim 1, wherein: the first detection module comprises a third comparator, the forward input end of the third comparator inputs voltage VIN, the reverse input end inputs undervoltage threshold voltage, the output end of the third comparator is connected with the input end of the third inverter, and the output end of the third inverter is connected with the second input end of the OR gate.
9. The power down detection circuit of claim 1, wherein: the output end of the OR gate is connected with the input end of an output module, and the output module outputs signals according to the output signals of the OR gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202420847804.4U CN220983380U (en) | 2024-04-23 | 2024-04-23 | Power failure detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202420847804.4U CN220983380U (en) | 2024-04-23 | 2024-04-23 | Power failure detection circuit |
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| Publication Number | Publication Date |
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| CN220983380U true CN220983380U (en) | 2024-05-17 |
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| CN202420847804.4U Active CN220983380U (en) | 2024-04-23 | 2024-04-23 | Power failure detection circuit |
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| CN (1) | CN220983380U (en) |
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