CN220965497U - Metal oxide OLED array substrate structure - Google Patents
Metal oxide OLED array substrate structure Download PDFInfo
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- CN220965497U CN220965497U CN202322964772.4U CN202322964772U CN220965497U CN 220965497 U CN220965497 U CN 220965497U CN 202322964772 U CN202322964772 U CN 202322964772U CN 220965497 U CN220965497 U CN 220965497U
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 35
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 title claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 239000011521 glass Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 175
- 239000000463 material Substances 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229910052809 inorganic oxide Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 8
- 230000004069 differentiation Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 239000010405 anode material Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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Abstract
The utility model provides a metal oxide OLED array substrate structure, which comprises a glass substrate; a first insulating layer disposed on the glass substrate; the first metal layer comprises a first grid electrode and a second grid electrode, the first grid electrode is positioned on the first insulating layer, and the second grid electrode is positioned on the glass substrate; the second insulating layer is arranged on the first metal layer, is provided with a first through hole and exposes the upper surface of the second grid electrode; a semiconductor layer disposed on the second insulating layer, the semiconductor layer including a first semiconductor unit and a second semiconductor unit; the film layer structure corresponding to the first grid electrode is a first back channel metal oxide TFT, the film layer structure corresponding to the second grid electrode is a second back channel metal oxide TFT, and the structures of the first back channel metal oxide TFT and the second back channel metal oxide TFT are different. The utility model carries out structure differentiation arrangement on different TFTs in the array substrate, so that the display panel has higher stability and better driving effect.
Description
[ Field of technology ]
The utility model relates to the field of display panels, in particular to a metal oxide OLED array substrate structure.
[ Background Art ]
Along with the diversification of the demands of the consumer market, AMOLED, mini-LED, micro-LED, VR equipment and other equipment gradually become the main stream of the consumer market, and the display technology is further developed towards high color saturation, high resolution, high refresh rate, multi-screen joint display and other directions. In order to realize high-precision driving control of a display panel, a driving technique or a compensation technique required for the panel tends to be complicated, and thus, higher demands are made on the performance and switching characteristics of TFTs. Oxide TFT devices have the advantages of small leakage current, high field effect mobility, and large region uniformity, and are favored by people, but for high-end display devices, further research is needed on how to manufacture high-stability metal oxide TFTs that are adapted to the requirements of the driving circuits.
In order to reduce the use of driving ICs, a plurality of sets of driving circuits are generally disposed in the panel Array substrate, where the driving circuits are composed of a plurality of sets of devices such as TFTs, metal lines, capacitors, and the like with different sizes, which are commonly called GIP (Gate Driver In Panel) or GOA (GATE DRIVER On Array), or a voltage stabilizing circuit composed of a plurality of TFTs is disposed in each pixel of the active light emitting display panel to ensure the current stability of the light emitting device, which is called a voltage stabilizing circuit or a compensation circuit. If the driving requirements of different nodes can be further improved, the initial working electrical property of some TFTs can be independently controlled in the circuit, and then the circuit can realize some more complex functions or more stable effects.
In order to meet the requirement of adapting circuit functionality to the actual operating state of the device to achieve the optimized circuit driving effect, it is necessary to provide a differential TFT structure design.
[ utility model ]
The utility model aims to solve the technical problem of providing a metal oxide OLED array substrate structure, which is used for carrying out structure differentiation on different TFTs in an array substrate, so that a display panel has higher stability and better driving effect.
The utility model is realized in the following way:
a metal oxide OLED array substrate structure comprising:
A glass substrate;
A first insulating layer disposed on the glass substrate;
A first metal layer including a first gate electrode and a second gate electrode, the first gate electrode being on the first insulating layer, the second gate electrode being on the glass substrate;
The second insulating layer is arranged on the first metal layer, a first through hole is formed in the second insulating layer, and the first through hole is positioned above the second grid electrode and exposes the upper surface of the second grid electrode;
A semiconductor layer disposed on the second insulating layer, the semiconductor layer including a first semiconductor unit corresponding to the first gate electrode and a second semiconductor unit corresponding to the second gate electrode;
The second metal layer is arranged on the semiconductor layer and comprises a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, the first source electrode and the first drain electrode are respectively overlapped at two ends of the first semiconductor unit, and the other end of the first drain electrode is connected with the second grid electrode through a first through hole; the second source electrode and the second drain electrode are respectively lapped at two ends of the second semiconductor unit;
a third insulating layer disposed on the second metal layer;
The first organic insulating layer is arranged on the third insulating layer, a second through hole is formed in the first organic insulating layer, and the second through hole penetrates through the third insulating layer downwards and exposes the upper surface of the second drain electrode;
The third metal layer is arranged on the first organic insulating layer and is connected with the second drain electrode through the second through hole;
The second organic insulating layer is arranged on the third metal layer, a third through hole is formed in the second organic insulating layer, and the upper surface of the third metal layer is exposed;
The first electrode layer is arranged on the second organic insulating layer and is connected with the third metal layer through the third through hole;
The film layer structure corresponding to the first grid electrode is a first back channel metal oxide TFT, the film layer structure corresponding to the second grid electrode is a second back channel metal oxide TFT, and the first back channel metal oxide TFT and the second back channel metal oxide TFT are different in structure.
Further, the method further comprises the following steps:
The third organic insulating layer is arranged on the first electrode layer, a fourth through hole is formed in the third organic insulating layer, and the upper surface of the first electrode layer is exposed;
And a fourth organic insulating layer disposed on the third organic insulating layer, the fourth organic insulating layer including isolation pillars.
Further, the first metal layer, the second metal layer and the third metal layer are selected from one of aluminum, molybdenum, titanium, nickel, copper, silver and tungsten to form a single-layer structure, or a multi-layer structure formed by more than two materials, or an alloy formed by more than two materials;
The first insulating layer, the second insulating layer and the third insulating layer are of a single-layer or multi-layer structure, and inorganic oxide or insulating compound is selected as a material.
The utility model has the advantages that:
The utility model provides a differential TFT structure design, which aims at the difference of working states required by different nodes of a TFT in a circuit, optimizes the structure of the TFT, ensures that two back channel metal oxide TFTs have different structures, can be better distinguished, ensures that the TFTs of a driving circuit can independently control the electrical characteristics according to the functions exerted by the TFTs, optimizes the driving effect of the circuit, and has higher stability and better driving effect.
[ Description of the drawings ]
The utility model will be further described with reference to examples of embodiments with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a metal oxide OLED array substrate structure according to the present utility model.
FIG. 2 is a flowchart of steps 1-6 of a method for fabricating a metal oxide OLED array substrate structure according to the present utility model.
FIG. 3 is a flowchart of steps 7-10 of a method for fabricating a metal oxide OLED array substrate structure according to the present utility model.
Reference numerals illustrate:
A glass substrate 1;
a first insulating layer 2;
A first metal layer 3, a first gate electrode 31, a second gate electrode 32;
a second insulating layer 4, a first via 41;
A semiconductor layer 5, a first semiconductor unit 51, a second semiconductor unit 52;
a second metal layer 6, a first source electrode 61, a first drain electrode 62, a second source electrode 63, and a second drain electrode 64;
a third insulating layer 7;
A first organic insulating layer 8, a second via 81;
A third metal layer 9;
A second organic insulating layer 10, a third via 101;
A first electrode layer 11;
A third organic insulating layer 12, a fourth via 121;
a fourth organic insulating layer 13, isolation pillars 131;
A first back channel metal oxide TFT 100; and a second back channel metal oxide TFT 200.
[ Detailed description ] of the invention
The technical solutions of the present utility model will be clearly and completely described below with reference to fig. 1 to 3 and the detailed description. In the description of the present utility model, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1, a metal oxide OLED array substrate structure of the present utility model includes:
A glass substrate 1;
A first insulating layer 2 provided on the glass substrate 1;
A first metal layer 3, wherein the first metal layer 3 comprises a first gate electrode 31 and a second gate electrode 32, the first gate electrode 31 is positioned on the first insulating layer 2, and the second gate electrode 32 is positioned on the glass substrate 1;
A second insulating layer 4 disposed on the first metal layer 3, wherein a first through hole 41 is disposed on the second insulating layer 4, and the first through hole 41 is located above the second gate electrode 32 and exposes an upper surface of the second gate electrode 32;
a semiconductor layer 5 disposed on the second insulating layer 4, the semiconductor layer 5 including a first semiconductor unit 51 and a second semiconductor unit 52, the first semiconductor unit 51 corresponding to the first gate electrode 31, the second semiconductor unit 52 corresponding to the second gate electrode 32;
A second metal layer 6 disposed on the semiconductor layer 5, where the second metal layer 6 includes a first source electrode 61, a first drain electrode 62, a second source electrode 63, and a second drain electrode 64, the first source electrode 61 and the first drain electrode 62 are respectively overlapped at two ends of the first semiconductor unit 51, and the other end of the first drain electrode 62 is further connected to the second gate electrode 32 through a first via 41; the second source electrode 63 and the second drain electrode 64 are respectively overlapped at two ends of the second semiconductor unit 52;
a third insulating layer 7 disposed on the second metal layer 6;
The first organic insulating layer 8 is disposed on the third insulating layer 7, a second through hole 81 is formed in the first organic insulating layer 8, and the second through hole 81 penetrates through the third insulating layer 7 downwards and exposes the upper surface of the second drain electrode 64;
A third metal layer 9 disposed on the first organic insulating layer 8, the third metal layer 9 being connected to the second drain electrode 64 through a second via 81;
A second organic insulating layer 10 disposed on the third metal layer 9, where a third through hole 101 is formed in the second organic insulating layer 10 and exposes the upper surface of the third metal layer 9;
A first electrode layer 11, the first electrode layer 11 being disposed on the second organic insulating layer 10, the first electrode layer 11 being connected to the third metal layer 9 through the third via hole 101;
The film structure corresponding to the first gate 31 is a first back channel metal oxide TFT 100, the film structure corresponding to the second gate 32 is a second back channel metal oxide TFT 100, and the first back channel metal oxide TFT 100 and the second back channel metal oxide TFT 200 have different structures.
The array substrate structure further includes:
A third organic insulating layer 12 disposed on the first electrode layer 11, where a fourth through hole 121 is formed in the third organic insulating layer 12 and exposes the upper surface of the first electrode layer 11;
A fourth organic insulating layer 13 disposed on the third organic insulating layer 12, the fourth organic insulating layer 13 including isolation pillars 131.
The first metal layer 3, the second metal layer 6 and the third metal layer 9 are made of one of aluminum, molybdenum, titanium, nickel, copper, silver and tungsten to form a single-layer structure, or a multi-layer structure formed by more than two materials, or an alloy formed by more than two materials;
The first insulating layer 2, the second insulating layer 4 and the third insulating layer 7 are in a single-layer or multi-layer structure, and inorganic oxide or insulating compound is selected as a material.
Referring to fig. 2-3, in another embodiment, the preparation method of the present utility model is as follows:
step 1, forming a first insulating layer 2 on a glass substrate 1, and preparing a clearance area in a specific area by utilizing an etching process to expose the surface of the glass substrate 1;
Step 2, forming a first metal layer 3 on the first insulating layer 2 to serve as a driving circuit wiring or a TFT device grid electrode, namely a first grid electrode 31 and a second grid electrode 32;
Step 3, continuously forming a second insulating layer 4 as a gate insulating layer and a semiconductor layer 5 on the first metal layer 3, firstly patterning the semiconductor layer 5 by using an etching process to prepare a semiconductor channel region and a contact region of a required TFT device, namely, the semiconductor channel region comprises a first semiconductor unit 51 and a second semiconductor unit 52, and preparing a first through hole 41 by using the etching process to expose the surface of the second gate 32;
the semiconductor layer 5 is made of a metal oxide semiconductor material;
Step 4, forming a second metal layer 6 on the semiconductor layer 5, wherein the process and material selection are the same as those of the first metal layer 3, and the second metal layer 6 can be designed into a data signal line, an electrode signal line, a TFT signal input source/drain (i.e. including a first source electrode 61, a first drain electrode 62, a second source electrode 63, a second drain electrode 64), and other signal lines according to circuit design;
the first drain electrode 62 may be connected to the second gate electrode 32 through the first via hole 41;
Step 5, forming a third insulating layer 7 on the second metal layer 6, wherein the material is selected from inorganic oxide or insulating compound, continuously preparing a first organic insulating layer 8 (organic flat layer) on the third insulating layer 7, and preparing a second through hole 81 by exposure and etching processes to expose the surface of the second drain electrode 64;
step 6, forming a third metal layer 9 on the first organic insulating layer 8, wherein the process and the material are selected from the same as those of the first metal layer 3, and the second drain electrode 64 is connected through a second through hole 81;
Step 7, preparing a second organic insulating layer 10 on the third metal layer 9, and preparing a third through hole 101 through an exposure and development process to expose the surface of the third metal layer 9;
Step 8, preparing a first electrode layer 11, namely an anode of the OLED device (preferably Ag is used as an anode material, and an anode is prepared by adopting an ITO/Ag/ITO laminated structure) on the second organic insulating layer 10, wherein one side of the first electrode layer 11 is connected with the surface of the third metal layer 9 through a third through hole 101;
Step 9, preparing a third organic insulating layer 12, namely a pixel definition layer, by using an organic insulating material, and developing an RGB pattern opening (a fourth through hole 121) to expose the first electrode layer 11, namely the upper surface of the anode;
Step 10, preparing the isolation column 131 by using an organic insulating material to play a role of supporting the cover plate.
The utility model provides a differential TFT structure design, which aims at the difference of working states required by different nodes of a TFT in a circuit, optimizes the structure of the TFT, ensures that two back channel metal oxide TFTs have different structures, can be better distinguished, ensures that the TFTs of a driving circuit can independently control the electrical characteristics according to the functions exerted by the TFTs, optimizes the driving effect of the circuit, and has higher stability and better driving effect.
While specific embodiments of the utility model have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the utility model, and that equivalent modifications and variations of the utility model in light of the spirit of the utility model will be covered by the claims of the present utility model.
Claims (3)
1. The utility model provides a metal oxide OLED array substrate structure which characterized in that: comprising the following steps:
A glass substrate;
A first insulating layer disposed on the glass substrate;
A first metal layer including a first gate electrode and a second gate electrode, the first gate electrode being on the first insulating layer, the second gate electrode being on the glass substrate;
The second insulating layer is arranged on the first metal layer, a first through hole is formed in the second insulating layer, and the first through hole is positioned above the second grid electrode and exposes the upper surface of the second grid electrode;
A semiconductor layer disposed on the second insulating layer, the semiconductor layer including a first semiconductor unit corresponding to the first gate electrode and a second semiconductor unit corresponding to the second gate electrode;
The second metal layer is arranged on the semiconductor layer and comprises a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, the first source electrode and the first drain electrode are respectively overlapped at two ends of the first semiconductor unit, and the other end of the first drain electrode is connected with the second grid electrode through a first through hole; the second source electrode and the second drain electrode are respectively lapped at two ends of the second semiconductor unit;
a third insulating layer disposed on the second metal layer;
The first organic insulating layer is arranged on the third insulating layer, a second through hole is formed in the first organic insulating layer, and the second through hole penetrates through the third insulating layer downwards and exposes the upper surface of the second drain electrode;
The third metal layer is arranged on the first organic insulating layer and is connected with the second drain electrode through the second through hole;
The second organic insulating layer is arranged on the third metal layer, a third through hole is formed in the second organic insulating layer, and the upper surface of the third metal layer is exposed;
The first electrode layer is arranged on the second organic insulating layer and is connected with the third metal layer through the third through hole;
The film layer structure corresponding to the first grid electrode is a first back channel metal oxide TFT, the film layer structure corresponding to the second grid electrode is a second back channel metal oxide TFT, and the first back channel metal oxide TFT and the second back channel metal oxide TFT are different in structure.
2. The metal oxide OLED array substrate structure of claim 1, wherein: further comprises:
The third organic insulating layer is arranged on the first electrode layer, a fourth through hole is formed in the third organic insulating layer, and the upper surface of the first electrode layer is exposed;
And a fourth organic insulating layer disposed on the third organic insulating layer, the fourth organic insulating layer including isolation pillars.
3. The metal oxide OLED array substrate structure of claim 1, wherein: the first metal layer, the second metal layer and the third metal layer are selected from one of aluminum, molybdenum, titanium, nickel, copper, silver and tungsten to form a single-layer structure, or a multi-layer structure formed by more than two materials, or an alloy formed by more than two materials;
The first insulating layer, the second insulating layer and the third insulating layer are of a single-layer or multi-layer structure, and inorganic oxide or insulating compound is selected as a material.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322964772.4U CN220965497U (en) | 2023-11-02 | 2023-11-02 | Metal oxide OLED array substrate structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322964772.4U CN220965497U (en) | 2023-11-02 | 2023-11-02 | Metal oxide OLED array substrate structure |
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| Publication Number | Publication Date |
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| CN220965497U true CN220965497U (en) | 2024-05-14 |
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| CN202322964772.4U Active CN220965497U (en) | 2023-11-02 | 2023-11-02 | Metal oxide OLED array substrate structure |
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